SANTA CLARA, USA: GEO Semiconductor Inc., a leader in high performance, programmable 2/3D video and geometric pixel processor IC solutions that enable large new markets in LED-backlit LCD displays and smartphone cameras (optics through sensor), announced more than $1 million in funding comprised of convertible debt and equity. GEO is pleased that the former lead investor in Genesis Microchip has now become a major investor in the company.
GEO plans to utilize the proceeds from this funding to support multiple new design wins for applications in LED backlighting for LCD flat panel displays, smartphone cameras, video conferencing, surveillance, laser 3D TV, digital cinema, medical displays, broadcast and 2D/3D projection. With a clear strategy in place, large emerging markets for its products, and many new design wins with industry leaders, GEO is now well positioned to initiate series B financing efforts to fund the next generation of products.
GEO Semiconductor’s chairman and CEO, Paul Russo, said: "I am very pleased to have raised this capital and welcomed a major new investor to GEO. This financing will enable us to further capitalize on high-volume high-growth opportunities that include correcting color & brightness uniformity issues in LED-backlit LCD displays, correcting optical anomalies and sensor pixel non-uniformity issues in smartphones as well as enabling major new features.
"Because of the nature of its origins as a technology buy-out from an established business, GEO is essentially the equivalent of a typical series C or D stage fabless semiconductor company. As a result, many early stage development risks associated with technology and IC development, customer acceptance and IP protection have already been overcome, which gives me confidence that our series B will be well received by investors. I want to extend my appreciation to our existing stakeholders and all of our committed employees for their continued support, and I look forward to sharing with them our future growth and success."
Thursday, March 31, 2011
Fairchild achieves first-pass silicon success with DesignWare USB 2.0 nanoPHY IP
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Fairchild Semiconductor (Fairchild) has achieved first-pass silicon success for its FUSB2500 UTMI+ Low-Pin Interface (ULPI) USB On-The-Go (OTG) transceiver chip utilizing Synopsys' DesignWare USB 2.0 nanoPHY IP.
Fairchild selected Synopsys' silicon-proven DesignWare IP because it was low in power and area and offered impressive technical features, including auto-detect functionality and ULPI interface. In addition, the tunability of the PHY enabled Fairchild to easily conduct post-silicon adjustments without incurring the cost of a metal respin.
Fairchild was able to easily integrate the DesignWare USB 2.0 nanoPHY IP within weeks and had convenient access to a knowledgeable, responsive technical support team. This combination enabled Fairchild to lower integration risk and speed their time-to-market.
Targeting the high-end handset market, the Fairchild FUSB2500 USB 2.0 OTG transceiver chip was an extremely complex design that would be their first 130 nanometer (nm) chip to be integrated by a major manufacturer. Fairchild acquired USB IP from Synopsys, an established IP provider, to allow them to focus on their product differentiation and meet their critical 14 month project schedule. Using Synopsys' DesignWare USB 2.0 nanoPHY IP enabled Fairchild to successfully launch their leading FUSB2500 transceiver chip into the market on schedule.
"With a tight development schedule and complex design requirements, we wanted to partner with a trusted and established IP vendor such as Synopsys," said Jerry Johnston, senior director of switch and interface at Fairchild. "The Synopsys' DesignWare USB 2.0 nanoPHY IP offered us a solution that would incorporate all of our design needs and meet our time-to-market window. Synopsys' DesignWare IP is a high-quality product and will continue to be a key element of our future product developments."
"As companies such as Fairchild develop differentiated products that help their customers maintain a competitive edge, they can rely on Synopsys to help provide them with the necessary IP to meet their critical time-to-market window," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "As a leading provider of USB IP, with over 2,000 design wins and millions of units shipping in volume, Synopsys invests heavily in developing high-quality DesignWare USB IP that delivers key functionality to address our customer's design requirements and reduce integration risk."
Fairchild selected Synopsys' silicon-proven DesignWare IP because it was low in power and area and offered impressive technical features, including auto-detect functionality and ULPI interface. In addition, the tunability of the PHY enabled Fairchild to easily conduct post-silicon adjustments without incurring the cost of a metal respin.
Fairchild was able to easily integrate the DesignWare USB 2.0 nanoPHY IP within weeks and had convenient access to a knowledgeable, responsive technical support team. This combination enabled Fairchild to lower integration risk and speed their time-to-market.
Targeting the high-end handset market, the Fairchild FUSB2500 USB 2.0 OTG transceiver chip was an extremely complex design that would be their first 130 nanometer (nm) chip to be integrated by a major manufacturer. Fairchild acquired USB IP from Synopsys, an established IP provider, to allow them to focus on their product differentiation and meet their critical 14 month project schedule. Using Synopsys' DesignWare USB 2.0 nanoPHY IP enabled Fairchild to successfully launch their leading FUSB2500 transceiver chip into the market on schedule.
"With a tight development schedule and complex design requirements, we wanted to partner with a trusted and established IP vendor such as Synopsys," said Jerry Johnston, senior director of switch and interface at Fairchild. "The Synopsys' DesignWare USB 2.0 nanoPHY IP offered us a solution that would incorporate all of our design needs and meet our time-to-market window. Synopsys' DesignWare IP is a high-quality product and will continue to be a key element of our future product developments."
"As companies such as Fairchild develop differentiated products that help their customers maintain a competitive edge, they can rely on Synopsys to help provide them with the necessary IP to meet their critical time-to-market window," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "As a leading provider of USB IP, with over 2,000 design wins and millions of units shipping in volume, Synopsys invests heavily in developing high-quality DesignWare USB IP that delivers key functionality to address our customer's design requirements and reduce integration risk."
Mentor Graphics proceeds with convertible debt offering
WILSONVILLE, USA: Mentor Graphics Corp. announced that the company’s Board of Directors had affirmed its decision to proceed with the $253 million offering of 4.00 percent Convertible Subordinated Debentures due 2031 (the “4.00% Debentures”) announced on March 29, 2011.
The offering of the 4.00 percent Debentures allows the company to replace not only its outstanding 6.25 percent Convertible Subordinated Debentures due 2026 but also its $18.5 million secured term loan. The offering provides the following financial benefits:
* Reduces the cash interest rate on outstanding debentures from 6.25 percent to 4.00 percent;
* Increases the conversion price on Mentor’s debentures from $17.97 to $20.54 per share;
* Reduces dilution by using $25.0 million of proceeds to repurchase approximately 1.7 million shares;
* Extends the date on which debenture holders can force repayment by five years, from 2013 to 2018;
* Provides Mentor the ability to negotiate an amendment to extend the term of its existing revolving credit facility beyond 2013; and
* Effectively reduces interest costs from the company’s secured term loan from 4.81 percent to 4.00 percent.
The initial purchasers of the 4.00 percent Debentures exercised their over-allotment option to purchase $33 million of additional 4.00 percent Debentures on March 30, 2011.
Gregory K. Hinckley, president and CFO of Mentor, stated, “The high level of institutional investor interest in our new convertible debt offering resulted in attractive terms for the company and demonstrated strong investor support for Mentor’s business strategy and long-term prospects.”
The offering of the 4.00 percent Debentures allows the company to replace not only its outstanding 6.25 percent Convertible Subordinated Debentures due 2026 but also its $18.5 million secured term loan. The offering provides the following financial benefits:
* Reduces the cash interest rate on outstanding debentures from 6.25 percent to 4.00 percent;
* Increases the conversion price on Mentor’s debentures from $17.97 to $20.54 per share;
* Reduces dilution by using $25.0 million of proceeds to repurchase approximately 1.7 million shares;
* Extends the date on which debenture holders can force repayment by five years, from 2013 to 2018;
* Provides Mentor the ability to negotiate an amendment to extend the term of its existing revolving credit facility beyond 2013; and
* Effectively reduces interest costs from the company’s secured term loan from 4.81 percent to 4.00 percent.
The initial purchasers of the 4.00 percent Debentures exercised their over-allotment option to purchase $33 million of additional 4.00 percent Debentures on March 30, 2011.
Gregory K. Hinckley, president and CFO of Mentor, stated, “The high level of institutional investor interest in our new convertible debt offering resulted in attractive terms for the company and demonstrated strong investor support for Mentor’s business strategy and long-term prospects.”
AppliedMicro’s PacketPro multi-core APM8639x SoC family supports subsystem isolation with asymmetric multiprocessing
SUNNYVALE, USA: Applied Micro Circuits Corp. announced the availability of “Diamondback” APM86392 and APM86391, the newest members of its PacketPro family of multi-core embedded processing devices.
Through an innovative asymmetric multiprocessing (AMP) capability, these devices enable two or more independent subsystems to operate concurrently with effective isolation on a single chip. This feature improves application performance and offers higher reliability. It is also designed to provide an easier migration to multicore designs with greater flexibility for a wide range of embedded applications in networking, storage, printing, imaging, and multimedia access systems.
Traditional multi-core processors force software engineers to dedicate one of the cores as a master to control the operations of the other slave cores. By harnessing innovative features of the PacketPro family enabled by AppliedMicro’s Scalable Lightweight Intelligent Management processor (SLIMpro) subsystem, developers can implement AMP on APM8639x processors without dedicating one of the cores as a master.
This enables completely separate and isolated partitions on a single chip, each with independent operating systems, applications, software, processing bandwidth, I/O and cache. Each subsystem is decoupled from other subsystems during software updates, crashes, rebooting, peak performance demands or other events that can interrupt continuous operations.
“In instances of a system fail requiring complete reboot, the PacketPro allows the decoupling of cores without interruption or impact of other subsystems running on the same embedded SoC device,” said Jim Johnston, senior Director of Marketing at AppliedMicro. “Before this, both subsystems would have to be taken down to reboot one operating system due to dependencies from shared cache memory and other resources. AppliedMicro’s approach provides each processor with separate and virtualized access to processor resources that one subsystem can continue operation even if any of the other ones becomes inoperative.”
Additionally, AppliedMicro’s AMP approach is designed to aid developers who are migrating from single-core to multi-core designs by allowing them to consolidate several applications onto one SoC without the re-engineering that typically accompanies porting of software to a multi-core environment, thereby reducing overall development time and bill-of-material costs while accelerating time to market. The PacketPro family of devices also utilizes the SLIMpro subsystem to manage multiple power islands on the SoC to meet low-power, energy efficiency requirements.
“Working hand-in-hand with our customers gave AppliedMicro great insight on the needs of next-generation platforms,” said Vinay Ravuri, VP and GM, Processor Business Unit. “PacketPro asymmetric multiprocessing is one of the capabilities developers need because they must effectively manage multiple operating systems and applications on a single chip. The non-blocking architecture of PacketPro is arbitrated by superior queue management and traffic management so that each individual application never suffers from a lack of processing resources, ensuring the highest reliability and uninterrupted performance.”
AppliedMicro’s Diamondback APM86391 single core devices and APM86292 dual-core processors feature PowerPC 465 processing cores operating at up to 1.0GHz with floating point units, 32 KB I- and 32KB D-cache, 256 KB L2 cache per processor, 32-bit DDR at 1066 Mbps DDR3 memory controller with optional ECC. High-speed interfaces consist of GE ports with in-line classification, security and TCP/IP offload, three single lane PCI-e Gen 2, two USB 2.0 host with integrated PHYs, one USB 2.0 OTG with integrated PHY, and one SATA 2.0 ports.
The Serengeti evaluation platform is available now running up to 1.0GHz and exposes all interfaces available on the SoC. The PacketPro family is supported by an ecosystem of third-party suppliers such as WindRiver, VxWorks, Free BSD, Enea, NetBSD and others.
Through an innovative asymmetric multiprocessing (AMP) capability, these devices enable two or more independent subsystems to operate concurrently with effective isolation on a single chip. This feature improves application performance and offers higher reliability. It is also designed to provide an easier migration to multicore designs with greater flexibility for a wide range of embedded applications in networking, storage, printing, imaging, and multimedia access systems.
Traditional multi-core processors force software engineers to dedicate one of the cores as a master to control the operations of the other slave cores. By harnessing innovative features of the PacketPro family enabled by AppliedMicro’s Scalable Lightweight Intelligent Management processor (SLIMpro) subsystem, developers can implement AMP on APM8639x processors without dedicating one of the cores as a master.
This enables completely separate and isolated partitions on a single chip, each with independent operating systems, applications, software, processing bandwidth, I/O and cache. Each subsystem is decoupled from other subsystems during software updates, crashes, rebooting, peak performance demands or other events that can interrupt continuous operations.
“In instances of a system fail requiring complete reboot, the PacketPro allows the decoupling of cores without interruption or impact of other subsystems running on the same embedded SoC device,” said Jim Johnston, senior Director of Marketing at AppliedMicro. “Before this, both subsystems would have to be taken down to reboot one operating system due to dependencies from shared cache memory and other resources. AppliedMicro’s approach provides each processor with separate and virtualized access to processor resources that one subsystem can continue operation even if any of the other ones becomes inoperative.”
Additionally, AppliedMicro’s AMP approach is designed to aid developers who are migrating from single-core to multi-core designs by allowing them to consolidate several applications onto one SoC without the re-engineering that typically accompanies porting of software to a multi-core environment, thereby reducing overall development time and bill-of-material costs while accelerating time to market. The PacketPro family of devices also utilizes the SLIMpro subsystem to manage multiple power islands on the SoC to meet low-power, energy efficiency requirements.
“Working hand-in-hand with our customers gave AppliedMicro great insight on the needs of next-generation platforms,” said Vinay Ravuri, VP and GM, Processor Business Unit. “PacketPro asymmetric multiprocessing is one of the capabilities developers need because they must effectively manage multiple operating systems and applications on a single chip. The non-blocking architecture of PacketPro is arbitrated by superior queue management and traffic management so that each individual application never suffers from a lack of processing resources, ensuring the highest reliability and uninterrupted performance.”
AppliedMicro’s Diamondback APM86391 single core devices and APM86292 dual-core processors feature PowerPC 465 processing cores operating at up to 1.0GHz with floating point units, 32 KB I- and 32KB D-cache, 256 KB L2 cache per processor, 32-bit DDR at 1066 Mbps DDR3 memory controller with optional ECC. High-speed interfaces consist of GE ports with in-line classification, security and TCP/IP offload, three single lane PCI-e Gen 2, two USB 2.0 host with integrated PHYs, one USB 2.0 OTG with integrated PHY, and one SATA 2.0 ports.
The Serengeti evaluation platform is available now running up to 1.0GHz and exposes all interfaces available on the SoC. The PacketPro family is supported by an ecosystem of third-party suppliers such as WindRiver, VxWorks, Free BSD, Enea, NetBSD and others.
ChipStart selects S2C to facilitate prototyping ChipStart’s SoC system management options
PALO ALTO, USA: ChipStart LLC, a semiconductor intellectual property solution company, announced that it has selected S2C, Inc. as a target vendor for prototyping and low volume deployment of ChipStart’s SSM SoC System Manager.
Today’s SoCs often include multiple processors and other high functionality hardware blocks supplied by multiple internal and external sources. Each one of these blocks has unique system management requirements, such as reset and boot sequencing, as well as power and security management. SSM enables system management functions to be abstracted and centrally controlled using software.
The SSM controller accepts software based command sequences in real time and communicates with each of the IP blocks via a simple SSM bus. This bus is represented as a ring, is easy to implement, and can operate across multiple clock domains. A small SSM register block is connected to each IP block to facilitate mapping the software based commands into specific signal transitions communicated to each of the hardware blocks over the SSM bus.
“For certain applications, such as communications appliances, personalizing the SoC happens more frequently and this can cause a lot of design and test complexity at the system level. In these cases there are economic advantages to having a small FPGA next to the SoC which hosts the SSM controller, rather than incorporating the entire SSM architecture into the SoC,” said Howard Pakosh, president and CEO ChipStart LLC. “Certainly this is the case when prototyping systems management schemes for the first time, but this solution can also offer more flexibility for real time personalization of several ASICs at the board level after the appliances have been shipped into the field.”
ChipStart is offering SSM on the S2C Single Virtex-5 110 TAI Logic Module. This logic module is designed for rapid SoC/ASIC prototyping and can hold designs with up to 1.1M ASIC gates. This design can be ported to higher capacity S2C prototyping boards.
“Combining IP subsystems such a SSM with flexible prototyping vehicles such as Virtex-5 not only accelerates architecture development but also delivers the predictable system behavior early in the SoC design cycle that shaves months off of a typical time to market schedule. By controlling the system state transitions using a software scheme, developing and debugging software on the target hardware is much more efficient than traditional approaches,” said Toshio Nakama, CEO of S2C.
SoC System Management is rapidly becoming one of the most difficult and expensive design challenges for SoC developers. The proliferation of applications, such as Facebook, Twitter, and YouTube across appliances has re-oriented user expectations of having the same experience across all their appliances, whether it be a cell phone, Internet TV, laptop or tablet computers. As a result, SoC developers are now faced with the challenge of building SoC “platforms” that must comprehend uniform user experience requirements, even if their target SoC is vertically aligned.
“The dynamics of a consistent user experience anywhere and on any appliance means that SoCs targeted for a specific appliance must in some way comprehend how the application will be executed on other appliances,” said Rich Wawryzniak, Senior Analyst, Semico Research. “Adding personalization through real time programmability into the SoC is now a necessity, and incorporating subsystem IP SoC methodologies that includes SoC system management delivers superior business economics.”
SSM is the only merchant SoC Subsystem Management IP available today. SSM provides power and security management, error recovery, boot and reset sequencing, using a software-based sequencing methodology that is effective for normal operation sequences and exception handling and can transition as the applications are selected by the end user.
Today’s SoCs often include multiple processors and other high functionality hardware blocks supplied by multiple internal and external sources. Each one of these blocks has unique system management requirements, such as reset and boot sequencing, as well as power and security management. SSM enables system management functions to be abstracted and centrally controlled using software.
The SSM controller accepts software based command sequences in real time and communicates with each of the IP blocks via a simple SSM bus. This bus is represented as a ring, is easy to implement, and can operate across multiple clock domains. A small SSM register block is connected to each IP block to facilitate mapping the software based commands into specific signal transitions communicated to each of the hardware blocks over the SSM bus.
“For certain applications, such as communications appliances, personalizing the SoC happens more frequently and this can cause a lot of design and test complexity at the system level. In these cases there are economic advantages to having a small FPGA next to the SoC which hosts the SSM controller, rather than incorporating the entire SSM architecture into the SoC,” said Howard Pakosh, president and CEO ChipStart LLC. “Certainly this is the case when prototyping systems management schemes for the first time, but this solution can also offer more flexibility for real time personalization of several ASICs at the board level after the appliances have been shipped into the field.”
ChipStart is offering SSM on the S2C Single Virtex-5 110 TAI Logic Module. This logic module is designed for rapid SoC/ASIC prototyping and can hold designs with up to 1.1M ASIC gates. This design can be ported to higher capacity S2C prototyping boards.
“Combining IP subsystems such a SSM with flexible prototyping vehicles such as Virtex-5 not only accelerates architecture development but also delivers the predictable system behavior early in the SoC design cycle that shaves months off of a typical time to market schedule. By controlling the system state transitions using a software scheme, developing and debugging software on the target hardware is much more efficient than traditional approaches,” said Toshio Nakama, CEO of S2C.
SoC System Management is rapidly becoming one of the most difficult and expensive design challenges for SoC developers. The proliferation of applications, such as Facebook, Twitter, and YouTube across appliances has re-oriented user expectations of having the same experience across all their appliances, whether it be a cell phone, Internet TV, laptop or tablet computers. As a result, SoC developers are now faced with the challenge of building SoC “platforms” that must comprehend uniform user experience requirements, even if their target SoC is vertically aligned.
“The dynamics of a consistent user experience anywhere and on any appliance means that SoCs targeted for a specific appliance must in some way comprehend how the application will be executed on other appliances,” said Rich Wawryzniak, Senior Analyst, Semico Research. “Adding personalization through real time programmability into the SoC is now a necessity, and incorporating subsystem IP SoC methodologies that includes SoC system management delivers superior business economics.”
SSM is the only merchant SoC Subsystem Management IP available today. SSM provides power and security management, error recovery, boot and reset sequencing, using a software-based sequencing methodology that is effective for normal operation sequences and exception handling and can transition as the applications are selected by the end user.
Ambarella A7 IP Camera SoC brings 1080p60 performance into video surveillance mainstream
ISC West 2011, SANTA CLARA, USA: Ambarella Inc., a leader in low-power, HD video compression and image processing semiconductors, announced the A7 IP Camera SoC, bringing high-quality 1080p60 H.264 performance to the video surveillance market. The A7 integrates a high performance image sensor pipeline with up to 500 MHz pixel capture rate with a multi-streaming 1080p60 H.264 encoder and power consumption below 1.5 Watts.
The A7 leverages Ambarella’s professional broadcast encoding and 3D noise reduction technology to deliver high-quality video at exceptionally low bitrates, even in complex high-motion and low-light scenes. A wide selection of CMOS sensors are supported, including the newest generation of 14 megapixel resolution and Wide Dynamic Range (WDR) devices. Ambarella will demonstrate the A7 performance during the International Security Conference & Expo (ISC West 2011) to be held in Las Vegas, April 6-8 (www.iscwest.com).
“As Ambarella’s flagship SoC for IP cameras, the new A7 delivers flexible, 1080p60 high-definition capabilities for the next generation of IP cameras,” said Fermi Wang, president & CEO of Ambarella. “The A7 extends our growing IP camera product portfolio and further demonstrates Ambarella’s commitment to the video surveillance market.”
The A7 offers a number of industry-firsts and innovations for IP camera applications:
* 500 MHz pixel capture rate (equivalent to 8 Megapixels at 60 frames per second) - supports oversampling for the highest image quality and enables multi-window digital Pan Tilt Zoom (PTZ).
* 3D motion compensated noise reduction eliminates the motion smearing and ghosting artifacts that are commonly associated with motion adaptive 3D filtering.
* Digital WDR adjusts the contrast of each pixel to enhance visibility in challenging lighting conditions.
* Flexible video engine delivers up to 1080p60 + VGA H.264 High Profile encoding, or the combination of streams, such as two 1080p30, four 720p30 streams, or 5 Megapixel at 24 fps.
* Flexible multiple-stream encoding with independent frame rate, resolution, bit rate, Group of Pictures (GOP) and profile. Achieves optimal encoding efficiency for both storage and viewing streams.
* Large motion estimation search range and support for hierarchical B-frames enable high compression efficiency and superior motion handling.
* Sub-frame encoding delay for improved real-time communications.
* Low power consumption (below 1.5W) improves reliability, simplifies design, and enables compact form factors.
The A7 leverages Ambarella’s professional broadcast encoding and 3D noise reduction technology to deliver high-quality video at exceptionally low bitrates, even in complex high-motion and low-light scenes. A wide selection of CMOS sensors are supported, including the newest generation of 14 megapixel resolution and Wide Dynamic Range (WDR) devices. Ambarella will demonstrate the A7 performance during the International Security Conference & Expo (ISC West 2011) to be held in Las Vegas, April 6-8 (www.iscwest.com).
“As Ambarella’s flagship SoC for IP cameras, the new A7 delivers flexible, 1080p60 high-definition capabilities for the next generation of IP cameras,” said Fermi Wang, president & CEO of Ambarella. “The A7 extends our growing IP camera product portfolio and further demonstrates Ambarella’s commitment to the video surveillance market.”
The A7 offers a number of industry-firsts and innovations for IP camera applications:
* 500 MHz pixel capture rate (equivalent to 8 Megapixels at 60 frames per second) - supports oversampling for the highest image quality and enables multi-window digital Pan Tilt Zoom (PTZ).
* 3D motion compensated noise reduction eliminates the motion smearing and ghosting artifacts that are commonly associated with motion adaptive 3D filtering.
* Digital WDR adjusts the contrast of each pixel to enhance visibility in challenging lighting conditions.
* Flexible video engine delivers up to 1080p60 + VGA H.264 High Profile encoding, or the combination of streams, such as two 1080p30, four 720p30 streams, or 5 Megapixel at 24 fps.
* Flexible multiple-stream encoding with independent frame rate, resolution, bit rate, Group of Pictures (GOP) and profile. Achieves optimal encoding efficiency for both storage and viewing streams.
* Large motion estimation search range and support for hierarchical B-frames enable high compression efficiency and superior motion handling.
* Sub-frame encoding delay for improved real-time communications.
* Low power consumption (below 1.5W) improves reliability, simplifies design, and enables compact form factors.
Mentor Graphics FloTHERM wins 2011 Design News Golden Mousetrap Award for Best Design Tools Product
WILSONVILLE, USA: Mentor Graphics Corp. announced that it has received the 2011 Design News Golden Mousetrap Award for Best Product in the Design Tools Category for its FloTHERM 3D computational fluid dynamics (CFD) software.
The FloTHERM 9 product features an industry-first, patent-pending technology for Bottleneck (Bn) and Shortcut (Sc) fields that identifies where heat flow congestion occurs in the electronic design and why, and identifies optimum thermal shortcuts to efficiently resolve the design problem.
“The products highlighted in this year's Golden Mousetrap winners and finalists clearly demonstrate both cutting-edge design ideas and the practical evolution of technologies for systems and product design engineers,” stated David Greenfield, editorial director of Design News Magazine. “Design News congratulates all the engineers and their companies who have been recognized with the Golden Mousetrap Award, and we are grateful for their contribution to this year's competition.”
For more than two decades, the Design News Awards Program has recognized engineering innovation and creativity in product design. This year, Golden Mousetrap awards were given in four major categories: Electronics & Test, Automation & Control, Design Tools: Hardware & Software, and Materials & Assembly.
Managing Editor Jennifer Campbell gathered a record number of entries, distributing them to their beat editors for judging. Based on their expertise in each technology area, 18 winners and 95 finalists were selected. Mentor Graphics also received a Golden Mousetrap Award in 2010 for its innovative FloEFD concurrent CFD software that provides rapid virtual prototyping.
The industry-leading FloTHERM software reduces thermal verification by 33 percent and reduces PCB design re-spins by 500% compared to other solutions, according to a survey conducted by the Aberdeen Group (Maintaining Design Integrity through the PCB Process, 2007). The new Bn and Sc capabilities revolutionize the way designers solve their heat management challenges. When used in conjunction with the FloTHERM classic thermal analysis, designers will be guided with intelligent suggestions based on the Bn and Sc fields instead of experimenting with trial and error solutions.
“We are honored to receive our second consecutive Design News Golden Mousetrap Award now for our patent-pending Bn and Sc technology in our FloTHERM software,” stated Erich Buergel, general manager of Mentor Graphics Mechanical Analysis Division. “This innovative technology has helped reduce our customers’ development costs while improving product quality in shorter timeframes.”
The FloTHERM 9 product features an industry-first, patent-pending technology for Bottleneck (Bn) and Shortcut (Sc) fields that identifies where heat flow congestion occurs in the electronic design and why, and identifies optimum thermal shortcuts to efficiently resolve the design problem.
“The products highlighted in this year's Golden Mousetrap winners and finalists clearly demonstrate both cutting-edge design ideas and the practical evolution of technologies for systems and product design engineers,” stated David Greenfield, editorial director of Design News Magazine. “Design News congratulates all the engineers and their companies who have been recognized with the Golden Mousetrap Award, and we are grateful for their contribution to this year's competition.”
For more than two decades, the Design News Awards Program has recognized engineering innovation and creativity in product design. This year, Golden Mousetrap awards were given in four major categories: Electronics & Test, Automation & Control, Design Tools: Hardware & Software, and Materials & Assembly.
Managing Editor Jennifer Campbell gathered a record number of entries, distributing them to their beat editors for judging. Based on their expertise in each technology area, 18 winners and 95 finalists were selected. Mentor Graphics also received a Golden Mousetrap Award in 2010 for its innovative FloEFD concurrent CFD software that provides rapid virtual prototyping.
The industry-leading FloTHERM software reduces thermal verification by 33 percent and reduces PCB design re-spins by 500% compared to other solutions, according to a survey conducted by the Aberdeen Group (Maintaining Design Integrity through the PCB Process, 2007). The new Bn and Sc capabilities revolutionize the way designers solve their heat management challenges. When used in conjunction with the FloTHERM classic thermal analysis, designers will be guided with intelligent suggestions based on the Bn and Sc fields instead of experimenting with trial and error solutions.
“We are honored to receive our second consecutive Design News Golden Mousetrap Award now for our patent-pending Bn and Sc technology in our FloTHERM software,” stated Erich Buergel, general manager of Mentor Graphics Mechanical Analysis Division. “This innovative technology has helped reduce our customers’ development costs while improving product quality in shorter timeframes.”
Combined sales of tablet and NB contributed to an 18.1 percent YoY increase in mobile PC shipments
TAIWAN: According to DRAMeXchange, a research department of Trendforce, the weak end-market demand and impacts from the Japan earthquake on NB supply chain are placing increasing uncertainty on the 2Q shipments by ODM manufacturers. Even though the demand will likely be deferred to 2H11, but it will also be compromised by the considerable surge of the tablet shipments.
Source: DRAMeXchange, Taiwan.
It is expected that the crowding out effect will repress growth of NB. Therefore, DRAMeXchange estimates that in 2011, the shipments of NB, including netbook, will only be 208 million units with a mere 7.3 percent YoY increase; the shipments of netbook will plummet 25 percent from last year, with a total of 25 million units; the shipments of tablet will surge to 39.5 million with a 152.4 percent YoY increase.
As for the outlook of PC industry, due to the fact that tablet manufactures continue to launch new models and that the market share of emerging markets is on a gradual rise, the industrial ecology is bound to change in 2011.
Fig. 1 is a predication of the growth within PC industry in 2011. On account of the fact that desktop market is close to reaching saturation, the demand in emerging markets will contribute to the most part of growth in 2011. Currently, the average selling price of All-In-One computers is still significantly higher than that of traditional desktops. Hence, as far as the shipments of desktops are concerned, AIO computers will not be much of a help until 2012 or 2013.
In addition, affected by the cannibalization from notebook sales, the YoY increase of desktop sales is expected to be no more than 2.7 percent. However, notebook sales are not immune to cannibalization from netbook and are badly affected by the budget constraint. As a result, despite of the cannibalization on desktops, growth of notebook may not be as impressive as usual, which will be primarily underpinned by the demand in emerging markets and from business procurements.
In general, the cannibalization notebooks face from tablets is eminent. The total shipments of Mobile PC in 2010, including regular notebook, netbook and tablet, reached 209.6 million with a 31.2 percent YoY increase, which DRAMeXchange expects to advance to 247.5 million in 2011 with an 18.1 percent YoY increase, continuing to deliver the usual ~20 percent growth of notebook shipments and keep the growth momentum of PC industry going.
Source: DRAMeXchange, Taiwan.
Source: DRAMeXchange, Taiwan. It is expected that the crowding out effect will repress growth of NB. Therefore, DRAMeXchange estimates that in 2011, the shipments of NB, including netbook, will only be 208 million units with a mere 7.3 percent YoY increase; the shipments of netbook will plummet 25 percent from last year, with a total of 25 million units; the shipments of tablet will surge to 39.5 million with a 152.4 percent YoY increase.
As for the outlook of PC industry, due to the fact that tablet manufactures continue to launch new models and that the market share of emerging markets is on a gradual rise, the industrial ecology is bound to change in 2011.
Fig. 1 is a predication of the growth within PC industry in 2011. On account of the fact that desktop market is close to reaching saturation, the demand in emerging markets will contribute to the most part of growth in 2011. Currently, the average selling price of All-In-One computers is still significantly higher than that of traditional desktops. Hence, as far as the shipments of desktops are concerned, AIO computers will not be much of a help until 2012 or 2013.
In addition, affected by the cannibalization from notebook sales, the YoY increase of desktop sales is expected to be no more than 2.7 percent. However, notebook sales are not immune to cannibalization from netbook and are badly affected by the budget constraint. As a result, despite of the cannibalization on desktops, growth of notebook may not be as impressive as usual, which will be primarily underpinned by the demand in emerging markets and from business procurements.
In general, the cannibalization notebooks face from tablets is eminent. The total shipments of Mobile PC in 2010, including regular notebook, netbook and tablet, reached 209.6 million with a 31.2 percent YoY increase, which DRAMeXchange expects to advance to 247.5 million in 2011 with an 18.1 percent YoY increase, continuing to deliver the usual ~20 percent growth of notebook shipments and keep the growth momentum of PC industry going.
Source: DRAMeXchange, Taiwan.
Toshiba Imaging presents high def 3CCD and CMOS cameras
NAB 2011, IRVINE, USA: Toshiba Imaging Systems Division will be co-exhibiting with Polecam in Booth #C8013, at NAB 2011, demonstrating new, high definition cameras, the IK-HD1 and the IK-HR1H.
Ideal for broadcast applications, Toshiba's IK-HD1 is the smallest, 3CCD remote-head camera available. The tiny head is only 1.6 inches and 2.3 ounces, and delivers the clearest, true color imagery available with 1920 x 1080 output at 30 frames per second.
Toshiba's recently introduced IK-HR1H is an affordable CMOS high definition camera with an ultra-small, remote head (only 1.18 in. x 1.37 in. x 1.41 in.) housing. For added flexibility, two versions of this small, lightweight HD camera are available for applications where space is limited.
One version, the IK-HR1CD, offers 8-bit (RGB) DVI-I connector and DVI-I with selectable outputs of 1080p at 60 fps, 1080i at 30 fps, and 720p at 60 fps. The second small remote-head CMOS model, the IK-HR1CS, features HD-SDI output with 1080i at 30 fps and 720p at 60 fps.
Remote-head, high definition cameras from Toshiba Imaging are successfully being used in camera-car rigs to chase storms for Discovery Channels' "Storm Chasers" series, to capture feature film background plates for process playback, to capture 3D imagery, and in many other film, TV, sports, documentary, drama, and Internet productions.
Ideal for broadcast applications, Toshiba's IK-HD1 is the smallest, 3CCD remote-head camera available. The tiny head is only 1.6 inches and 2.3 ounces, and delivers the clearest, true color imagery available with 1920 x 1080 output at 30 frames per second.
Toshiba's recently introduced IK-HR1H is an affordable CMOS high definition camera with an ultra-small, remote head (only 1.18 in. x 1.37 in. x 1.41 in.) housing. For added flexibility, two versions of this small, lightweight HD camera are available for applications where space is limited.
One version, the IK-HR1CD, offers 8-bit (RGB) DVI-I connector and DVI-I with selectable outputs of 1080p at 60 fps, 1080i at 30 fps, and 720p at 60 fps. The second small remote-head CMOS model, the IK-HR1CS, features HD-SDI output with 1080i at 30 fps and 720p at 60 fps.
Remote-head, high definition cameras from Toshiba Imaging are successfully being used in camera-car rigs to chase storms for Discovery Channels' "Storm Chasers" series, to capture feature film background plates for process playback, to capture 3D imagery, and in many other film, TV, sports, documentary, drama, and Internet productions.
Freescale intros KwikStik development tool for Kinetis MCUs
AUSTIN, USA: Freescale Semiconductor announced the KwikStik development tool, a cost-effective, all-in-one development tool used for evaluating, developing and debugging with Freescale’s Kinetis line of microcontrollers (MCUs) built on the ARM Cortex-M4 core. Complementing the larger Freescale Tower System development platform, the KwikStik development tool provides an additional toolset option in a small-form-factor design for developers using Kinetis MCUs.
The KwikStik development tool combines a J-Link debug probe, low-power touch sensing, a segment LCD user interface and a suite of development and run-time software. It is designed to be used several ways – as a standalone, battery-operated tool for development using the on-board Kinetis K40 MCU; as an additional tool with the Tower System or as a J-Link debugger.
By combining the KwikStik development tool with the Tower System, developers have access to multiple system expansion options using Freescale and third-party peripheral modules that offer sensing and wireless and industrial connectivity (including Wi-Fi). The integrated SEGGER J-Link debug interface eliminates the need for a separate debug probe, providing a significant cost savings.
“We created KwikStik to give developers a small, economical tool option for rapid development with our Kinetis MCUs,” said Jeff Bock, director of product marketing for Freescale’s Industrial and Multi-Market MCU business. “It gives developers easy access to the industry-proven SEGGER J-link on the board and an expansive collection of Tower System development cards.”
“Freescale's decision to include the SEGGER J-link technology offers their customers the optimal debug solution,” said Shane Titus, SEGGER managing director for U.S. Operations. “We believe the KwikStik is one of the best embedded development kits in the market.”
The KwikStik development tool offers a range of low-power, mixed-signal, human machine interface and connectivity and communications peripherals. The Kinetis K40 MCU at the core of the KwikStik features 256 KB of on-chip flash memory and an equivalent amount of FlexMemory, allowing ample space for application code. The bundled Processor Expert tool supporting Kinetis MCUs helps designers write application code for even complex software requirements.
Using Freescale’s Processor Expert auto-code generator, developers can quickly build their own custom peripheral driver library, optimized and validated to their needs. This feature, embedded within the Eclipse-based CodeWarrior 10.1 integrated development environment (IDE), simplifies a developer’s software architecture and can reduce development time.
The KwikStik development tool combines a J-Link debug probe, low-power touch sensing, a segment LCD user interface and a suite of development and run-time software. It is designed to be used several ways – as a standalone, battery-operated tool for development using the on-board Kinetis K40 MCU; as an additional tool with the Tower System or as a J-Link debugger.
By combining the KwikStik development tool with the Tower System, developers have access to multiple system expansion options using Freescale and third-party peripheral modules that offer sensing and wireless and industrial connectivity (including Wi-Fi). The integrated SEGGER J-Link debug interface eliminates the need for a separate debug probe, providing a significant cost savings.
“We created KwikStik to give developers a small, economical tool option for rapid development with our Kinetis MCUs,” said Jeff Bock, director of product marketing for Freescale’s Industrial and Multi-Market MCU business. “It gives developers easy access to the industry-proven SEGGER J-link on the board and an expansive collection of Tower System development cards.”
“Freescale's decision to include the SEGGER J-link technology offers their customers the optimal debug solution,” said Shane Titus, SEGGER managing director for U.S. Operations. “We believe the KwikStik is one of the best embedded development kits in the market.”
The KwikStik development tool offers a range of low-power, mixed-signal, human machine interface and connectivity and communications peripherals. The Kinetis K40 MCU at the core of the KwikStik features 256 KB of on-chip flash memory and an equivalent amount of FlexMemory, allowing ample space for application code. The bundled Processor Expert tool supporting Kinetis MCUs helps designers write application code for even complex software requirements.
Using Freescale’s Processor Expert auto-code generator, developers can quickly build their own custom peripheral driver library, optimized and validated to their needs. This feature, embedded within the Eclipse-based CodeWarrior 10.1 integrated development environment (IDE), simplifies a developer’s software architecture and can reduce development time.
HDL Design House adopts Magma’s full suite of software to accelerate SoC and IP development
BANGALORE, INDIA: Magma Design Automation Inc., a provider of chip design software, and HDL Design House, creators of re-usable IP cores, verification components and behavioral simulation models, announced that HDL Design House has adopted the full suite of Magma chip design software, including the Talus digital IC implementation system and the Titan mixed-signal design platform.
With Magma as its primary EDA vendor, HDL Design House will now be able to provide its clients with complete mixed-signal system on chip (SoC) design services, and be able to augment their current family of soft digital IP cores with analog IP. Its proven technology leadership was crucial in HDL Design House’s decision to standardize on Magma’s digital and analog implementation, simulation, and verification and characterization software.
“Our customers range from small start-up companies to multi-national corporations in the semiconductor, wireless and medical industries and have varying design requirements,” said Predrag Markovic, president and CEO, HDL Design House. “With Magma’s full suite of design software, we can accelerate the delivery of our portfolio of design IP, and meet our customers’ varying requirements with a combination of world class expertise in, and best-in-class tools for, digital and analog design, verification and characterization.”
“Magma offers a broad portfolio of leading-edge technology that solves designers’ toughest problems,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “By providing advanced capabilities, fast performance and high levels of automation, Magma provides HDL Design House with comprehensive solutions that deliver outstanding quality of results and faster turnaround time.”
Magma: “Fastest Path to Silicon”
Offering a truly integrated IC design system and highly automated flow, Magma provides designers with the "Fastest Path to Silicon." The Talus digital implementation system combines traditionally separate front-end and back-end chip design into an integrated flow that's designed to eliminate iterations between the synthesis and place-and-route processes, accelerate the design cycle and reduce IC development costs.
The Titan environment includes the comprehensive Titan Mixed-Signal Design Platform, and the Titan Accelerators, a set of breakthrough point-tool technologies that integrate with and augment existing analog/mixed-signal design flows. The Titan Accelerators provide unique capabilities that dramatically improve analog design productivity, and enable true analog design reuse.
Unlike legacy flows, the Titan Accelerators are next-generation design technologies that provide capabilities for rapidly designing, analyzing and optimizing circuit designs and layouts, and implementing them in today’s advanced process geometries. The Titan Mixed-Signal Design Platform tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing a quantum leap in efficiency and productivity for analog designers.
With Magma as its primary EDA vendor, HDL Design House will now be able to provide its clients with complete mixed-signal system on chip (SoC) design services, and be able to augment their current family of soft digital IP cores with analog IP. Its proven technology leadership was crucial in HDL Design House’s decision to standardize on Magma’s digital and analog implementation, simulation, and verification and characterization software.
“Our customers range from small start-up companies to multi-national corporations in the semiconductor, wireless and medical industries and have varying design requirements,” said Predrag Markovic, president and CEO, HDL Design House. “With Magma’s full suite of design software, we can accelerate the delivery of our portfolio of design IP, and meet our customers’ varying requirements with a combination of world class expertise in, and best-in-class tools for, digital and analog design, verification and characterization.”
“Magma offers a broad portfolio of leading-edge technology that solves designers’ toughest problems,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit. “By providing advanced capabilities, fast performance and high levels of automation, Magma provides HDL Design House with comprehensive solutions that deliver outstanding quality of results and faster turnaround time.”
Magma: “Fastest Path to Silicon”
Offering a truly integrated IC design system and highly automated flow, Magma provides designers with the "Fastest Path to Silicon." The Talus digital implementation system combines traditionally separate front-end and back-end chip design into an integrated flow that's designed to eliminate iterations between the synthesis and place-and-route processes, accelerate the design cycle and reduce IC development costs.
The Titan environment includes the comprehensive Titan Mixed-Signal Design Platform, and the Titan Accelerators, a set of breakthrough point-tool technologies that integrate with and augment existing analog/mixed-signal design flows. The Titan Accelerators provide unique capabilities that dramatically improve analog design productivity, and enable true analog design reuse.
Unlike legacy flows, the Titan Accelerators are next-generation design technologies that provide capabilities for rapidly designing, analyzing and optimizing circuit designs and layouts, and implementing them in today’s advanced process geometries. The Titan Mixed-Signal Design Platform tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing a quantum leap in efficiency and productivity for analog designers.
MunEDA unveils industry’s first commercially available automated solution for process technology porting of circuit schematics and IP
MUNICH, GERMANY: MunEDA, developer of the industry’s broadest family of advanced circuit analysis, modeling and optimization solutions, announced that it has launched the WiCkeDTM SPT Schematic Porting Tool, the first commercially-available electronic design automation (EDA) software tool to automate the time-consuming task of porting circuit schematics and intellectual property (IP) between different process technologies and process design kits (PDKs).
As the newest member of MunEDA’s advanced tool suite WiCkeD, SPT executes 10-100X faster than manual schematic porting, significantly reducing design time and effort. The tool supports migration paths in major TSMC process technologies such as from tsmcN65 (65nm) to tsmcN40 (40nm), but can be configured also for different process migration paths. MunEDA will present SPT at the TSMC 2011 USA Technology Symposium in San Jose, Calif. on April 5th, in Austin, Texas on April 7th, and in Boston, Mass., on April 12th, 2011.
“IP and schematic porting is one of the key topics of the industry,” said Andreas Ripp, MunEDA VP, Sales & Marketing. “Migrating circuit schematics between different process technologies and PDKs can be a very time-consuming task for circuit designers, and we see a clear customer need for an automated solution. MunEDA invested in the development of this advanced technology and methodology, which significantly increases designer productivity and is much simpler than manual schematic porting.”
MunEDA WiCkeD SPT supports designers with an efficient design migration path, automatically replacing cells in the source PDK with corresponding cells for the target PDK. It provides flexible property mapping and automated shrinking, and handles all kinds of devices such as MOS transistors, resistors, capacitors and others. It is configurable for many source and target process technologies, and initially is available in TSMC processes. MunEDA can set up further process technologies on request. MunEDA WiCkeD SPT is fully integrated into the Cadence Virtuoso-based unified custom/analog flow.
Michael Pronath, MunEDA VP of Products & Solutions, said: “SPT addresses the ever-growing challenge of migrating many design blocks – and even entire SoCs – from one process to another in a short time, often with limited engineering capacity. Migrating analog/mixed-signal (AMS) designs, RF designs, IP libraries and high-speed interfaces is particularly challenging, because there is no simple rule for shrinking them. Most blocks need individual adjustment of topology, geometries, biasing, etc., even if the specifications don’t change. It is therefore necessary to migrate and port the schematics individually to conform to the technology constraints and to meet performance specifications. Manual migration is effort-intensive, and threatens to be a bottleneck. SPT solves these problems.”
MunEDA WiCkeD SPT will begin shipping in April 2011. Pricing for a single license starts at $25,000 USD for a one-year time-based license.
As the newest member of MunEDA’s advanced tool suite WiCkeD, SPT executes 10-100X faster than manual schematic porting, significantly reducing design time and effort. The tool supports migration paths in major TSMC process technologies such as from tsmcN65 (65nm) to tsmcN40 (40nm), but can be configured also for different process migration paths. MunEDA will present SPT at the TSMC 2011 USA Technology Symposium in San Jose, Calif. on April 5th, in Austin, Texas on April 7th, and in Boston, Mass., on April 12th, 2011.
“IP and schematic porting is one of the key topics of the industry,” said Andreas Ripp, MunEDA VP, Sales & Marketing. “Migrating circuit schematics between different process technologies and PDKs can be a very time-consuming task for circuit designers, and we see a clear customer need for an automated solution. MunEDA invested in the development of this advanced technology and methodology, which significantly increases designer productivity and is much simpler than manual schematic porting.”
MunEDA WiCkeD SPT supports designers with an efficient design migration path, automatically replacing cells in the source PDK with corresponding cells for the target PDK. It provides flexible property mapping and automated shrinking, and handles all kinds of devices such as MOS transistors, resistors, capacitors and others. It is configurable for many source and target process technologies, and initially is available in TSMC processes. MunEDA can set up further process technologies on request. MunEDA WiCkeD SPT is fully integrated into the Cadence Virtuoso-based unified custom/analog flow.
Michael Pronath, MunEDA VP of Products & Solutions, said: “SPT addresses the ever-growing challenge of migrating many design blocks – and even entire SoCs – from one process to another in a short time, often with limited engineering capacity. Migrating analog/mixed-signal (AMS) designs, RF designs, IP libraries and high-speed interfaces is particularly challenging, because there is no simple rule for shrinking them. Most blocks need individual adjustment of topology, geometries, biasing, etc., even if the specifications don’t change. It is therefore necessary to migrate and port the schematics individually to conform to the technology constraints and to meet performance specifications. Manual migration is effort-intensive, and threatens to be a bottleneck. SPT solves these problems.”
MunEDA WiCkeD SPT will begin shipping in April 2011. Pricing for a single license starts at $25,000 USD for a one-year time-based license.
Alchimer continues Asian expansion through agreement with Kromax in Taiwan
MASSY, FRANCE: In a move that underscores growing demand for its wet deposition process in Asia, Alchimer S.A. has signed an agreement with Kromax International Corp., a Taiwanese company that represents leading semiconductor and flat-panel equipment manufacturers and material suppliers in the Asian market.
Kromax will represent Alchimer’s total through-silicon via (TSV) solution in Taiwan, including its Electrografting (eG) wet deposition technology. Electrografting is Alchimer’s breakthrough electrochemical process that enables the growth of extremely high-quality nanometric films for TSVs, semiconductor interconnects, MEMS and other electronic applications.
“This is further recognition in one of the most important chip-producing markets that Alchimer’s mature technology is recognized as a cost-effective solution for high aspect ratio TSVs, and we are pleased to announce this expansion of sales and service for our Taiwanese customers,” said Steve Lerner, Alchimer CEO. “Kromax’s history of operations in Taiwan and the rest of Asia, its strong relationships with Alchimer’s customers, and its excellent reputation for bringing breakthrough technologies to the market make it a very good fit for Alchimer.”
“Kromax is pleased to add Alchimer to our portfolio of leading tool and materials companies serving the IC and flat-panel markets,” said Kell Hwang, chairman of Kromax. “The company’s wet-deposition process has been solidly demonstrated as a leading solution for cost-effective, conformal high-aspect ratio TSVs.”
Alchimer’s expansion in Taiwan follows closely on the revenue success it has had in both South Korea and Japan, where it also has agreements with regional firms.
Kromax will represent Alchimer’s total through-silicon via (TSV) solution in Taiwan, including its Electrografting (eG) wet deposition technology. Electrografting is Alchimer’s breakthrough electrochemical process that enables the growth of extremely high-quality nanometric films for TSVs, semiconductor interconnects, MEMS and other electronic applications.
“This is further recognition in one of the most important chip-producing markets that Alchimer’s mature technology is recognized as a cost-effective solution for high aspect ratio TSVs, and we are pleased to announce this expansion of sales and service for our Taiwanese customers,” said Steve Lerner, Alchimer CEO. “Kromax’s history of operations in Taiwan and the rest of Asia, its strong relationships with Alchimer’s customers, and its excellent reputation for bringing breakthrough technologies to the market make it a very good fit for Alchimer.”
“Kromax is pleased to add Alchimer to our portfolio of leading tool and materials companies serving the IC and flat-panel markets,” said Kell Hwang, chairman of Kromax. “The company’s wet-deposition process has been solidly demonstrated as a leading solution for cost-effective, conformal high-aspect ratio TSVs.”
Alchimer’s expansion in Taiwan follows closely on the revenue success it has had in both South Korea and Japan, where it also has agreements with regional firms.
AltoBeam releases fourth generation CTTB/DVB-C demodulator on 55nm node
BEIJING, CHINA: AltoBeam, a Digital Television (DTV) demodulator IC maker, announced the worldwide release of its fourth generation CTTB/DVB-C demodulator, the ATBM8859, for the China DTV market.
The ATBM8859 is in full compliance with the GB20600-2006 (DTMB, used in CTTB broadcasting), China's terrestrial DTV broadcasting standard, and the GY/T 170-2001, China's equivalent to the DVB-C standard ITU-T J.83 (Annexes A and C). It supports CTTB/DVB-C reception of both high definition and standard definition signals.
"The ATBM8859 is manufactured on the advanced 55nm technology node. As such, while maintaining the smooth reception standard established by AltoBeam's industry leading ATBM884x family, the ATBM8859 consumes less power, and is housed in a smaller footprint, fewer pin-count package than its predecessor," said Dr. Steve Chaohuang Zeng, founder and CEO of AltoBeam.
"The release of the ATBM8859 further widens the already substantial technological gap between AltoBeam and our competitors, making AltoBeam the clear choice of demodulator supplier for global TV and module makers."
"Nowadays, premium DTV receivers need to stay competitive and relevant in three ways: functionally, they must provide smooth reception to create satisfactory user experience; electrically, they must support lower power operations to be in compliance with various environmental initiatives; and aesthetically, they must be thin to produce the harmonic appeal in modern home interior," added Qi Deng, VP of International Sales of AltoBeam. "With the ATBM8859 offering smooth reception, low power consumption and small package, brand conscious TV and module makers can design cutting-edge products with ease."
The ATBM8859 is in full compliance with the GB20600-2006 (DTMB, used in CTTB broadcasting), China's terrestrial DTV broadcasting standard, and the GY/T 170-2001, China's equivalent to the DVB-C standard ITU-T J.83 (Annexes A and C). It supports CTTB/DVB-C reception of both high definition and standard definition signals.
"The ATBM8859 is manufactured on the advanced 55nm technology node. As such, while maintaining the smooth reception standard established by AltoBeam's industry leading ATBM884x family, the ATBM8859 consumes less power, and is housed in a smaller footprint, fewer pin-count package than its predecessor," said Dr. Steve Chaohuang Zeng, founder and CEO of AltoBeam.
"The release of the ATBM8859 further widens the already substantial technological gap between AltoBeam and our competitors, making AltoBeam the clear choice of demodulator supplier for global TV and module makers."
"Nowadays, premium DTV receivers need to stay competitive and relevant in three ways: functionally, they must provide smooth reception to create satisfactory user experience; electrically, they must support lower power operations to be in compliance with various environmental initiatives; and aesthetically, they must be thin to produce the harmonic appeal in modern home interior," added Qi Deng, VP of International Sales of AltoBeam. "With the ATBM8859 offering smooth reception, low power consumption and small package, brand conscious TV and module makers can design cutting-edge products with ease."
ASP of mainstream NAND Flash increased 5~15 percent in March due to Japan earthquake
TAIWAN: According to DRAMeXchange, a research department of Trendforce, after the strike of the 9.0 earthquake in Japan Tohoku area on March 11th, at first, there was a rapid spot price increase in the NAND Flash market, in response to the uncertain concern of an upcoming short supply. But, since the impacts caused by the earthquake on NAND Flash supply chain were unknown at the time, some NAND Flash suppliers did not change the contract price in the first half of March. Then, the damage to the work in process (WIP) materials at Toshiba and SanDisk’s Yokkaichi plant came out.
Supplies of some raw materials for IC manufacturings were also reported. NAND Flash suppliers started to raise the contract price of NAND Flash in the second half of March. Average selling price of mainstream NAND Flash increased 5~15 percent in March.
On the other hand, due to certain suppliers’ strategies of lowering the price of the 2xnm TLC products in order to increase sales by memory card and UFD makers at the end of 1Q, some contract price of TLC decreased about 10% in the second half of March.
Source: DRAMeXchange, Taiwan.
In 2Q, uncertainty factors will continue to affect the demand and supply in NAND Flash market. In regard to supply:
a) On account of the fact that the loss of WIPs at Toshiba and SanDisk’s Yokkaichi plants and that a possible shortage of silicon wafer supply in the second half of 2Q, DRAMeXchange estimates the bit output of Yokkaichi plants will decrease up to 10 percent in 2Q, which will likely cause up to 4 percent decrease in global NAND Flash bit output in 2Q.
b) As for the supply of upstream silicon wafer in 2Q, the shutdown of Shin-Etsu Chemical’s Shirakawa plant will cause significant harm, because its capacity accounts for about 20 percent of global silicon wafer capacity. Due to equipment examination and electrical brownouts, there is still no definite date for its production to resume.
As for SUMCO’s Yonezawa plant and MEMC’s Utsunomiya plant, although they are temporary shut down due to electrical brownouts, but their capacities are comparatively smaller, so the effects they cause to silicon wafer supply in 2Q are limited. According to the current inventory levels of NAND Flash suppliers and their internal allocation and diversified procurement strategy of silicon wafers, it is expected there will be no effects on NAND Flash productions before the end of May.
c) If the short supply of silicon wafer remains unchanged in 2Q, manufacturers will rearrange the silicon wafer reallocation in respect to different products. However, manufacturers are still observing the future development of supply and demand in NAND Flash market in 2Q.
d) Mitsubishi Gas Chemical and Hitachi Chemical, the main suppliers of BT resin used in semiconductor products, plan to resume part of their production lines in affected areas at the end of March. Therefore, DRAMeXchange expects the shortage effects on BT resin supply to be eased in the beginning of May.
With regard to NAND Flash demand:
a) In 2Q, the retail memory card and UFD market will still be affected by the slow season effect.
b) After the Japan earthquake, some plants, located in the same afflicted area, that supply components to the NAND Flash end-products, like Tablet PC, Smartphone and PC, were shut down due to electricity brownouts, raw material shortage and equipment maintenance. According to downstream manufacturers’ inventory level and the slow sales of end-products in 2Q, it is expected that NAND Flash alone will not disrupt their production plans before mid-May. In addition, downstream manufacturers have started to search and test feasible alternatives in response to a possible component shortage in late 2Q.
c) Due to the fact that the demand for end-products in Japanese market is expected to decrease after the earthquake and that the shipments of end-products will be compromised by other component shortages and the delayed launch of new products from some vendors, sales of NAND Flash end-products will likely decrease in 2Q and 3Q.
Source: DRAMeXchange, Taiwan.
On the bright side, the transport facilities in affected areas have been gradually restored, and experts from several countries have been working on ways to resolve Fukushima Daiichi nuclear power plant crisis. It seems that some problems in affected areas are on their way to recovery shortly.
In addition, Japan is planning to restart part of back-up thermo power plants and coming up with electricity supply plans for this summer peak-period, in hope of reducing the impact caused by electricity brownouts on domestic production in the mid-term.
In general, DRAMeXchange expects the demand and supply in NAND Flash market will both decrease slightly in 2Q. Due to the fact that there has already been a considerable surge of NAND Flash contract price in March in response to the supply uncertainty the contract price is expected to remain steady in April with all the above-mentioned demand and supply factors considered. However, as the supply of electricity gradually comes back to normal in mid-2Q, NAND Flash contract price will likely dip down due to the slow season effect of 2Q.
Supplies of some raw materials for IC manufacturings were also reported. NAND Flash suppliers started to raise the contract price of NAND Flash in the second half of March. Average selling price of mainstream NAND Flash increased 5~15 percent in March.
On the other hand, due to certain suppliers’ strategies of lowering the price of the 2xnm TLC products in order to increase sales by memory card and UFD makers at the end of 1Q, some contract price of TLC decreased about 10% in the second half of March.
Source: DRAMeXchange, Taiwan.In 2Q, uncertainty factors will continue to affect the demand and supply in NAND Flash market. In regard to supply:
a) On account of the fact that the loss of WIPs at Toshiba and SanDisk’s Yokkaichi plants and that a possible shortage of silicon wafer supply in the second half of 2Q, DRAMeXchange estimates the bit output of Yokkaichi plants will decrease up to 10 percent in 2Q, which will likely cause up to 4 percent decrease in global NAND Flash bit output in 2Q.
b) As for the supply of upstream silicon wafer in 2Q, the shutdown of Shin-Etsu Chemical’s Shirakawa plant will cause significant harm, because its capacity accounts for about 20 percent of global silicon wafer capacity. Due to equipment examination and electrical brownouts, there is still no definite date for its production to resume.
As for SUMCO’s Yonezawa plant and MEMC’s Utsunomiya plant, although they are temporary shut down due to electrical brownouts, but their capacities are comparatively smaller, so the effects they cause to silicon wafer supply in 2Q are limited. According to the current inventory levels of NAND Flash suppliers and their internal allocation and diversified procurement strategy of silicon wafers, it is expected there will be no effects on NAND Flash productions before the end of May.
c) If the short supply of silicon wafer remains unchanged in 2Q, manufacturers will rearrange the silicon wafer reallocation in respect to different products. However, manufacturers are still observing the future development of supply and demand in NAND Flash market in 2Q.
d) Mitsubishi Gas Chemical and Hitachi Chemical, the main suppliers of BT resin used in semiconductor products, plan to resume part of their production lines in affected areas at the end of March. Therefore, DRAMeXchange expects the shortage effects on BT resin supply to be eased in the beginning of May.
With regard to NAND Flash demand:
a) In 2Q, the retail memory card and UFD market will still be affected by the slow season effect.
b) After the Japan earthquake, some plants, located in the same afflicted area, that supply components to the NAND Flash end-products, like Tablet PC, Smartphone and PC, were shut down due to electricity brownouts, raw material shortage and equipment maintenance. According to downstream manufacturers’ inventory level and the slow sales of end-products in 2Q, it is expected that NAND Flash alone will not disrupt their production plans before mid-May. In addition, downstream manufacturers have started to search and test feasible alternatives in response to a possible component shortage in late 2Q.
c) Due to the fact that the demand for end-products in Japanese market is expected to decrease after the earthquake and that the shipments of end-products will be compromised by other component shortages and the delayed launch of new products from some vendors, sales of NAND Flash end-products will likely decrease in 2Q and 3Q.
Source: DRAMeXchange, Taiwan.On the bright side, the transport facilities in affected areas have been gradually restored, and experts from several countries have been working on ways to resolve Fukushima Daiichi nuclear power plant crisis. It seems that some problems in affected areas are on their way to recovery shortly.
In addition, Japan is planning to restart part of back-up thermo power plants and coming up with electricity supply plans for this summer peak-period, in hope of reducing the impact caused by electricity brownouts on domestic production in the mid-term.
In general, DRAMeXchange expects the demand and supply in NAND Flash market will both decrease slightly in 2Q. Due to the fact that there has already been a considerable surge of NAND Flash contract price in March in response to the supply uncertainty the contract price is expected to remain steady in April with all the above-mentioned demand and supply factors considered. However, as the supply of electricity gradually comes back to normal in mid-2Q, NAND Flash contract price will likely dip down due to the slow season effect of 2Q.
Copper interconnect explosion continued into 2010
Dr. Robert Castellano, The Information Network
NEW TRIPOLI, USA: I stated in an e-mail to you on April 15, 2010 that according to our report 300mm/Copper/Low-K Convergence:Timing, Trends, Issues, Market Analysis , the long awaited transition to copper interconnects for memory devices skyrocketed in 2009, and will impact nearly every sector of the semiconductor equipment market into 2011.
I also noted that “While the overall semiconductor equipment market decreased more than 40 percent in 2009, equipment directly tied to the copper interconnect part of semiconductor manufacturing decreased only 8.7.”
Now as part of research in updating the report for 2011, I’ve discovered that the explosion continued in 2010 and the copper market grew 152 percent compared to 105 percent for the rest of the semiconductor equipment space.
In 2009 and in 2010, the impact of this transition on processing equipment was most obvious in equipment used with traditional aluminum interconnects. For example, the high-density plasma CVD sector (HDPCVD), which is used for depositing undoped (USG) and doped (PSG and FSG) films, saw revenues drop 72 percent in 2009. In 2010, HDPCVD grew only 19.4 percent!
The integration of copper into memory devices presents a different set of challenges than the long-established logic processes. DRAM and Flash, which comprise the majority of the memory applications, exhibit high aspect ratios, small CD sizes, and critical sensitivity to line resistance.
In 2009, we saw the implementation of copper into memory devices. In 2010, growth in logic was more pronounced than memory. The key here is that in a logic device there are 10-12 layers of copper interconnects versus only 1 layer for memory. So, 2010 was an exceptional year for copper because it combined the robust growth of logic as well as the continued transition to copper for memory.
NEW TRIPOLI, USA: I stated in an e-mail to you on April 15, 2010 that according to our report 300mm/Copper/Low-K Convergence:Timing, Trends, Issues, Market Analysis , the long awaited transition to copper interconnects for memory devices skyrocketed in 2009, and will impact nearly every sector of the semiconductor equipment market into 2011.
I also noted that “While the overall semiconductor equipment market decreased more than 40 percent in 2009, equipment directly tied to the copper interconnect part of semiconductor manufacturing decreased only 8.7.”
Now as part of research in updating the report for 2011, I’ve discovered that the explosion continued in 2010 and the copper market grew 152 percent compared to 105 percent for the rest of the semiconductor equipment space.
In 2009 and in 2010, the impact of this transition on processing equipment was most obvious in equipment used with traditional aluminum interconnects. For example, the high-density plasma CVD sector (HDPCVD), which is used for depositing undoped (USG) and doped (PSG and FSG) films, saw revenues drop 72 percent in 2009. In 2010, HDPCVD grew only 19.4 percent!
The integration of copper into memory devices presents a different set of challenges than the long-established logic processes. DRAM and Flash, which comprise the majority of the memory applications, exhibit high aspect ratios, small CD sizes, and critical sensitivity to line resistance.
In 2009, we saw the implementation of copper into memory devices. In 2010, growth in logic was more pronounced than memory. The key here is that in a logic device there are 10-12 layers of copper interconnects versus only 1 layer for memory. So, 2010 was an exceptional year for copper because it combined the robust growth of logic as well as the continued transition to copper for memory.
Renesas Electronics to sell US semicon wafer fab facility to TELEFUNKEN
TOKYO, JAPAN & HEILBRONN, GERMANY: Renesas Electronics Corp. and TELEFUNKEN Semiconductors GmbH & Co. KG, an automotive-qualified, mixed-signal, high-voltage (HV) power management and SOI-based manufacturer, announced that they have signed an agreement under which Renesas Electronics America Inc. will sell its semiconductor wafer fabrication facility in Roseville, California, to TELEFUNKEN Semiconductors International LLC, a company that includes TELEFUNKEN Semiconductors GmbH.
The sale price is approximately 53 million U.S. dollars, and the closing for the sale is planned for May 2, 2011. Wafra Capital Partners L.P. and Somerset Capital Group Ltd. helped TELEFUNKEN finance and facilitate the transaction, and ATREG Inc. advised Renesas Electronics throughout the transaction.
As part of the strategies decided through its 100-Day Project announced on July 29, 2010, Renesas Electronics has been considering and implementing various measures to improve manufacturing efficiency by promoting larger wafers, finer process node, and production concentration. In line with these measures, the company decided to sell Renesas Electronics America’s facility in Roseville, California, to TELEFUNKEN Semiconductors International, which has been searching for a new manufacturing facility to expand its semiconductor business.
TELEFUNKEN Semiconductors International intends to utilize the 200-millimeter (mm), eight-inch line at the Roseville factory to manufacture its own analog/mixed-signal, HV products and the products for its strategic foundry partners. TELEFUNKEN Semiconductors International also will enter into a supply agreement with Renesas Electronics for manufacturing services at the Roseville factory. Under this agreement, TELEFUNKEN Semiconductors International will focus on Renesas Electronics’ current customers without interruption for the same high-quality level of production and service at the Roseville facility.
Renesas Electronics remains fully committed to meeting customers’ requirements through its Quality Assurance Center in Roseville to continue support of customers in the North American and European markets.
The sale price is approximately 53 million U.S. dollars, and the closing for the sale is planned for May 2, 2011. Wafra Capital Partners L.P. and Somerset Capital Group Ltd. helped TELEFUNKEN finance and facilitate the transaction, and ATREG Inc. advised Renesas Electronics throughout the transaction.
As part of the strategies decided through its 100-Day Project announced on July 29, 2010, Renesas Electronics has been considering and implementing various measures to improve manufacturing efficiency by promoting larger wafers, finer process node, and production concentration. In line with these measures, the company decided to sell Renesas Electronics America’s facility in Roseville, California, to TELEFUNKEN Semiconductors International, which has been searching for a new manufacturing facility to expand its semiconductor business.
TELEFUNKEN Semiconductors International intends to utilize the 200-millimeter (mm), eight-inch line at the Roseville factory to manufacture its own analog/mixed-signal, HV products and the products for its strategic foundry partners. TELEFUNKEN Semiconductors International also will enter into a supply agreement with Renesas Electronics for manufacturing services at the Roseville factory. Under this agreement, TELEFUNKEN Semiconductors International will focus on Renesas Electronics’ current customers without interruption for the same high-quality level of production and service at the Roseville facility.
Renesas Electronics remains fully committed to meeting customers’ requirements through its Quality Assurance Center in Roseville to continue support of customers in the North American and European markets.
Chinese MCU market to expand by two thirds by 2015
EL SEGUNDO, USA: Owing to a strong industrial sector and rising sales of consumer electronics devices, China’s microcontroller (MCU) market is expected to reach $4.7 billion in revenue by 2015, up more than two-thirds from $2.8 billion in 2010, according to new IHS iSuppli research.
“Government plans designed to stimulate growth in the electronics business helped the China MCU market post robust growth last year, up 40 percent from $1.9 billion in 2009,” said Alex Liu, analyst for China electronics research at IHS.
“Those initiatives, along with a strong recovery in spending from consumers and in the industrial sector, will help to expand the China MCU market to $4.7 billion by 2015. Other forms of support from Beijing include a $600 billion investment in the country’s infrastructure and emerging technologies, subsidies for home appliances and automobiles and stimulus programs for green technology.”
Together, the government’s moves helped mitigate the global economic downturn of late 2008 and 2009 in the China MCU space, which experienced a 12 percent decline during the period. While better than the worldwide decline for MCUs of 23 percent, the decrease in China came as a blow to its once-growing market.
Prospects are upbeat once again, however, and MCUs are back on a path of solid expansion in the world’s most populous country.
The figure presents the IHS iSuppli forecast of China’s MCU market.
Source: IHS iSuppli, USA.
Industrial strength
The largest market for MCUs in China is the industrial sector. In 2010, MCU revenue in this segment amounted to $783 million, which came from greater requirements of industry equipment for MCUs, particularly in information management, data processing and communication.
Consumer electronics also surged to become the second largest segment for MCUs in China, finding their way into products such as home appliances, televisions, video game consoles and audio systems. As a result, the consumer electronics market for MCUs will rise at a 10 percent compound annual growth rate (CAGR) during the next five years.
Automotive makes gains
While the industrial and consumer segments formed the largest markets, the fastest-growing segment for China MCU consumption in 2010 came from automotive, with revenue rising 82 percent from 2009. In 2010, China’s auto market became the world’s largest region for vehicles, and the country emerged as an important base for producing automotive electronic devices, with 20 percent market share worldwide.
With a number of automotive electronics vendors establishing joint ventures and design centers in China, MCU revenue for automotive electronics will achieve a 16.5 percent CAGR from 2011 to 2015.
Higher-bit MCUs obtaining traction
The largest market in the foreseeable future for the China MCU market will be the 8-bit devices that are used in the consumer, data processing and industrial segments.
However, 8-bit MCUs gradually will lose share in various markets to higher-bit MCUs with their better performance and lower costs. Furthermore, frequency conversion technology has been growing in sectors such as green energy and home appliances, which will benefit sales of higher-bit MCUs in the coming years.
Source: IHS iSuppli, USA.
“Government plans designed to stimulate growth in the electronics business helped the China MCU market post robust growth last year, up 40 percent from $1.9 billion in 2009,” said Alex Liu, analyst for China electronics research at IHS.
“Those initiatives, along with a strong recovery in spending from consumers and in the industrial sector, will help to expand the China MCU market to $4.7 billion by 2015. Other forms of support from Beijing include a $600 billion investment in the country’s infrastructure and emerging technologies, subsidies for home appliances and automobiles and stimulus programs for green technology.”
Together, the government’s moves helped mitigate the global economic downturn of late 2008 and 2009 in the China MCU space, which experienced a 12 percent decline during the period. While better than the worldwide decline for MCUs of 23 percent, the decrease in China came as a blow to its once-growing market.
Prospects are upbeat once again, however, and MCUs are back on a path of solid expansion in the world’s most populous country.
The figure presents the IHS iSuppli forecast of China’s MCU market.
Source: IHS iSuppli, USA.Industrial strength
The largest market for MCUs in China is the industrial sector. In 2010, MCU revenue in this segment amounted to $783 million, which came from greater requirements of industry equipment for MCUs, particularly in information management, data processing and communication.
Consumer electronics also surged to become the second largest segment for MCUs in China, finding their way into products such as home appliances, televisions, video game consoles and audio systems. As a result, the consumer electronics market for MCUs will rise at a 10 percent compound annual growth rate (CAGR) during the next five years.
Automotive makes gains
While the industrial and consumer segments formed the largest markets, the fastest-growing segment for China MCU consumption in 2010 came from automotive, with revenue rising 82 percent from 2009. In 2010, China’s auto market became the world’s largest region for vehicles, and the country emerged as an important base for producing automotive electronic devices, with 20 percent market share worldwide.
With a number of automotive electronics vendors establishing joint ventures and design centers in China, MCU revenue for automotive electronics will achieve a 16.5 percent CAGR from 2011 to 2015.
Higher-bit MCUs obtaining traction
The largest market in the foreseeable future for the China MCU market will be the 8-bit devices that are used in the consumer, data processing and industrial segments.
However, 8-bit MCUs gradually will lose share in various markets to higher-bit MCUs with their better performance and lower costs. Furthermore, frequency conversion technology has been growing in sectors such as green energy and home appliances, which will benefit sales of higher-bit MCUs in the coming years.
Source: IHS iSuppli, USA.
Lattice's low cost breakout boards accelerate PLD design and hardware evaluation
HILLSBORO, USA: Lattice Semiconductor Corp. announced the immediate availability of three new low-cost I/O Breakout Boards: the MachXO 2280 Breakout Board, the ispMACH 4256ZE Breakout Board and the Power Manager II POWR1014A Breakout Board.
Lattice Breakout Board Evaluation Kits offer a convenient way for users to accelerate hardware evaluation and prototyping by providing easy access by hand to densely spaced PLD I/Os and pre-wired power and programming connections. For common end applications like I/O expansion and bridging, PLDs offer high I/O density at a low cost. This has made PLDs the preferred solution instead of discrete logic ICs or an application processor with more I/Os.
Breakout Boards provide a convenient way to access the fine-pitch pins or balls of a PLD package. For example, the center-to-center spacing of the package balls of the 256-ball BGA package of the MachXO 2280 Breakout Board is only 1.00 mm BSC (Basic Spacing between Centers).
Electrical traces of the Breakout Board connect each I/O to header landings that have 2.54 mm (100 mil / 0.1 inch) centered holes. By adding test probes, jumper wires or pin headers to the header landings, engineers can easily evaluate the MachXO sysI/O Buffer, ispMACH 4000ZE I/O cells, or POWR1014A voltage monitors, high-voltage FET drivers, and open drain outputs.
Each Breakout Board is 3" x 3" and features a USB B-mini connector for power and programming, an LED array and a prototype area. All Lattice Breakout Boards provide an easy to use platform for evaluating and designing with the MachXO 2280 PLD, ispMACH 4256ZE CPLD or the ispPAC®-POWR1014A Power Manager II. Along with the board and USB programming cable, each kit includes a pre-loaded hardware test program. Using Lattice design tools that are provided free of charge, the user can reprogram the on-board PLD device to evaluate custom designs.
"We're pleased to offer this new family of Lattice Breakout Boards, as designers have told us this is a key method to make their design process more convenient," said Gordon Hands, director of Marketing for Low Density and Mixed-Signal Solutions.
"These boards significantly reduce the effort and cost required to adopt and evaluate PLD and mixed signal devices. In fact, users can verify correct board operation in minutes and then connect Breakout Boards directly to their prototyping platforms and test equipment. Designers will also appreciate access to the schematic and PCB CAD artwork files available from the Lattice website.
"For this evaluation kit project," said Hands, "Lattice took advantage of the turnkey services of Lattice LEADER Design Services Partner Axelsys of Fremont, California. Axelsys provided us with a quick time-to-market using their full turnkey product solution with PLD design, PCB schematic and layout design, PCB fabrication and assembly, and kit packaging."
Lattice Breakout Board Evaluation Kits offer a convenient way for users to accelerate hardware evaluation and prototyping by providing easy access by hand to densely spaced PLD I/Os and pre-wired power and programming connections. For common end applications like I/O expansion and bridging, PLDs offer high I/O density at a low cost. This has made PLDs the preferred solution instead of discrete logic ICs or an application processor with more I/Os.
Breakout Boards provide a convenient way to access the fine-pitch pins or balls of a PLD package. For example, the center-to-center spacing of the package balls of the 256-ball BGA package of the MachXO 2280 Breakout Board is only 1.00 mm BSC (Basic Spacing between Centers).
Electrical traces of the Breakout Board connect each I/O to header landings that have 2.54 mm (100 mil / 0.1 inch) centered holes. By adding test probes, jumper wires or pin headers to the header landings, engineers can easily evaluate the MachXO sysI/O Buffer, ispMACH 4000ZE I/O cells, or POWR1014A voltage monitors, high-voltage FET drivers, and open drain outputs.
Each Breakout Board is 3" x 3" and features a USB B-mini connector for power and programming, an LED array and a prototype area. All Lattice Breakout Boards provide an easy to use platform for evaluating and designing with the MachXO 2280 PLD, ispMACH 4256ZE CPLD or the ispPAC®-POWR1014A Power Manager II. Along with the board and USB programming cable, each kit includes a pre-loaded hardware test program. Using Lattice design tools that are provided free of charge, the user can reprogram the on-board PLD device to evaluate custom designs.
"We're pleased to offer this new family of Lattice Breakout Boards, as designers have told us this is a key method to make their design process more convenient," said Gordon Hands, director of Marketing for Low Density and Mixed-Signal Solutions.
"These boards significantly reduce the effort and cost required to adopt and evaluate PLD and mixed signal devices. In fact, users can verify correct board operation in minutes and then connect Breakout Boards directly to their prototyping platforms and test equipment. Designers will also appreciate access to the schematic and PCB CAD artwork files available from the Lattice website.
"For this evaluation kit project," said Hands, "Lattice took advantage of the turnkey services of Lattice LEADER Design Services Partner Axelsys of Fremont, California. Axelsys provided us with a quick time-to-market using their full turnkey product solution with PLD design, PCB schematic and layout design, PCB fabrication and assembly, and kit packaging."
TI's Japan factories on track for full recovery
DALLAS, USA: Just over two weeks after a major earthquake in Japan, Texas Instruments Inc. (TI) reports that recovery at its manufacturing sites in Miho and Aizu is progressing well and is on schedule to return to full production.
The site in Miho, about 40 miles northeast of Tokyo, achieved a significant milestone this past Sunday as repairs were completed on the infrastructure systems that deliver water, gases, chemicals and air, and recertified the cleanroom. Additionally, more than 90 percent of the equipment has been electrically checked out.
TI now estimates that initial production lines at Miho will resume in mid-April, and full production will resume in mid-July. This translates to full shipment capability in September. In the first few days after the earthquake, TI had identified alternate manufacturing sites for about 60 percent of Miho's work in process, and has since increased that to more than 80 percent. Alternate sites include TI factories in Dallas and Richardson, Texas, and Freising, Germany.
TI's fab in Aizu, about 150 miles north of Tokyo, has resumed initial production and is on track for full production by mid-April or earlier. Production recovery schedules at both Miho and Aizu assume a stable source of electrical power.
The state of supply for raw materials remains dynamic, particularly for the components used in rigid substrates and for 300-millimeter wafers.
Operations of some existing suppliers are just beginning to recover, and TI is working closely with them to define and avoid potential supply chain disruptions. We also are working in parallel to ensure an independent supply of raw materials. While information is improving each day, TI believes the full scope of supply challenges is still unknown and will remain cautious until sources fully return to normal.
As previously stated on March 14, TI expects some loss of revenue in the first quarter and more lost revenue in the second quarter. Multiple factors may affect revenue loss, including TI's ability to move production to other factories, existing inventory from which to meet customers' needs, the level of demand from customers taking delivery of products in Japan, availability of raw materials, and the ability to incrementally increase production each month at Miho.
TI expects to describe the financial impact in detail at the time of its first-quarter earnings report on April 18.
The site in Miho, about 40 miles northeast of Tokyo, achieved a significant milestone this past Sunday as repairs were completed on the infrastructure systems that deliver water, gases, chemicals and air, and recertified the cleanroom. Additionally, more than 90 percent of the equipment has been electrically checked out.
TI now estimates that initial production lines at Miho will resume in mid-April, and full production will resume in mid-July. This translates to full shipment capability in September. In the first few days after the earthquake, TI had identified alternate manufacturing sites for about 60 percent of Miho's work in process, and has since increased that to more than 80 percent. Alternate sites include TI factories in Dallas and Richardson, Texas, and Freising, Germany.
TI's fab in Aizu, about 150 miles north of Tokyo, has resumed initial production and is on track for full production by mid-April or earlier. Production recovery schedules at both Miho and Aizu assume a stable source of electrical power.
The state of supply for raw materials remains dynamic, particularly for the components used in rigid substrates and for 300-millimeter wafers.
Operations of some existing suppliers are just beginning to recover, and TI is working closely with them to define and avoid potential supply chain disruptions. We also are working in parallel to ensure an independent supply of raw materials. While information is improving each day, TI believes the full scope of supply challenges is still unknown and will remain cautious until sources fully return to normal.
As previously stated on March 14, TI expects some loss of revenue in the first quarter and more lost revenue in the second quarter. Multiple factors may affect revenue loss, including TI's ability to move production to other factories, existing inventory from which to meet customers' needs, the level of demand from customers taking delivery of products in Japan, availability of raw materials, and the ability to incrementally increase production each month at Miho.
TI expects to describe the financial impact in detail at the time of its first-quarter earnings report on April 18.
ASSET’s JTAG-based embedded debugger diagnoses Intel x86 systems anywhere, anytime
RICHARDSON, USA: A new embedded debugger from ASSET InterTech, the leading supplier of tools for embedded instrumentation, is the first in-system JTAG-based debugger for Intel x86 platforms.
Based on ASSET’s ScanWorks platform for embedded instruments, the debugger implements hardware-based run control in system firmware. Once the debugger has been installed, systems can be debugged remotely from anywhere and at anytime with no external JTAG emulator hardware.
Referred to as the ScanWorks embedded diagnostics solution, the debugger firmware operates out of an x86-based circuit board’s service processor, which is sometimes called the Baseboard Management Controller (BMC) and may be implemented in a field programmable gate array (FPGA) on the board.
The ScanWorks embedded diagnostics solution is able to access the Intel x86 processor through its debug port to diagnose faults and failures in the system. Some of the typical debugger functions provided by ScanWorks embedded diagnostics include reading and writing to all x86 registers, to memory, and to I/O interfaces; setting and retrieving breakpoints; and single-stepping through code.
Because ScanWorks embedded diagnostics is deployed as intellectual property (IP) within working systems, it can perform powerful debugging routines in the lab or in the field, anywhere, anytime, and on an unlimited number of systems where it has been embedded. This functionality is invaluable for troubleshooting problems with the system’s device drivers, BIOS (Basic Input/Output System), operating system kernel, and catastrophic or intermittent hardware or software failures that might cause system crashes or hangs.
“Being able to debug the root cause of intermittent system failures in the field is a critical capability for high-availability systems,” said Alan Sguigna, vice president of sales and marketing for ASSET. “ScanWorks embedded diagnostics is able to identify the causes of problems that often seem impossible to debug, such as the dreaded ‘blue screen’ system crash or a kernel panic.”
One of the early adopters of ScanWorks embedded diagnostics was Cray Inc., which is integrating it into next-generation, high-availability supercomputers to ensure a high level of system reliability.
“ASSET’s ScanWorks platform provides a rich set of functionality for embedded diagnostics,” said Peg Williams, senior vice president of research and development at Cray. “ScanWorks-based solutions will enable Cray’s next-generation product development to maintain a focus on quality and reliability, while continuing to push the envelope in scalability. This is a real differentiator for Cray’s next-generation supercomputers and we believe it will give us a competitive advantage in the marketplace.”
Based on ASSET’s ScanWorks platform for embedded instruments, the debugger implements hardware-based run control in system firmware. Once the debugger has been installed, systems can be debugged remotely from anywhere and at anytime with no external JTAG emulator hardware.
Referred to as the ScanWorks embedded diagnostics solution, the debugger firmware operates out of an x86-based circuit board’s service processor, which is sometimes called the Baseboard Management Controller (BMC) and may be implemented in a field programmable gate array (FPGA) on the board.
The ScanWorks embedded diagnostics solution is able to access the Intel x86 processor through its debug port to diagnose faults and failures in the system. Some of the typical debugger functions provided by ScanWorks embedded diagnostics include reading and writing to all x86 registers, to memory, and to I/O interfaces; setting and retrieving breakpoints; and single-stepping through code.
Because ScanWorks embedded diagnostics is deployed as intellectual property (IP) within working systems, it can perform powerful debugging routines in the lab or in the field, anywhere, anytime, and on an unlimited number of systems where it has been embedded. This functionality is invaluable for troubleshooting problems with the system’s device drivers, BIOS (Basic Input/Output System), operating system kernel, and catastrophic or intermittent hardware or software failures that might cause system crashes or hangs.
“Being able to debug the root cause of intermittent system failures in the field is a critical capability for high-availability systems,” said Alan Sguigna, vice president of sales and marketing for ASSET. “ScanWorks embedded diagnostics is able to identify the causes of problems that often seem impossible to debug, such as the dreaded ‘blue screen’ system crash or a kernel panic.”
One of the early adopters of ScanWorks embedded diagnostics was Cray Inc., which is integrating it into next-generation, high-availability supercomputers to ensure a high level of system reliability.
“ASSET’s ScanWorks platform provides a rich set of functionality for embedded diagnostics,” said Peg Williams, senior vice president of research and development at Cray. “ScanWorks-based solutions will enable Cray’s next-generation product development to maintain a focus on quality and reliability, while continuing to push the envelope in scalability. This is a real differentiator for Cray’s next-generation supercomputers and we believe it will give us a competitive advantage in the marketplace.”
Wednesday, March 30, 2011
Alternative technologies vie for share of fast-growing mobile DRAM market
EL SEGUNDO, USA: Mobile dynamic access random memory (DRAM) in its current form soon may prove inadequate for the data intensive needs of smart phones and tablets in handling applications, but emerging options await in the wings as possible replacements in mobile platforms, according to new IHS iSuppli research.
Low-power, double data rate 2 (LPDDR2) is just now becoming the predominant technology in the mobile DRAM space, projected to take 40 percent market share by the second quarter this year, up from 31 percent in the first quarter. The majority of the mobile DRAM market continues to be held by the older LPDDR1 technology—although not for long.
By the fourth quarter this year, the tables will have turned, with LLPDDR2 finally gaining ascendance for the first time and controlling 58 percent of the market, as shown in the figure.
Source: IHS iSuppli, USA.
“Once a sleepy backwater of the DRAM market, mobile DRAM now is getting considerably more engineering and development attention from important players like Samsung Electronics Co., Hynix Semiconductor Inc., Elpida Memory Inc. and Micron Technology,” said Mike Howard, principal analyst for DRAM and memory at IHS.
“Unlike standard DRAM, the mobile counterpart for memory uses reduced power, generates a smaller amount of heat and takes up less space—attributes especially suitable for smart phones and other small electronic devices, with their need for greater computing power but possessing limited real estate. Mobile DRAM also is used in digital still cameras, portable media players, portable gaming products and tablets.”
A major challenge to mobile DRAM is its performance for future devices. While LPDDR2 is adequate now for phones and tablets, power consumption and bandwidth remain areas of concern.
For instance, operating at 1.2V, LPDDR2 offers as much as 50 percent power savings per data transfer compared to LPDDR1. However, if the devices of tomorrow perform 10 times as many data transfers—well within conceivable attainment soon—LPDDR2 would come up woefully short.
LPDDR2’s transfer rate of 8.5 gigabytes (GB) per second is also phenomenal compared to 1066 megahertz (MHz) for LPDDR1, but the LPDDR2 rate might not be enough for devices making their debut in the very near future. Feedback from smart phone makers has pointed to the need for rates of 12.8GB per second, which would necessitate LPDDR2 increasing its clock rate to 800MHz. This does not appear feasible, IHS believes.
What’s next in the pipeline?
With the performance thresholds of LPDDR2 likely to be reached and exhausted soon, several mobile DRAM technologies are vying for attention as alternatives. The competing technologies are shown in the attached table.
The current front runners are mobile XDR, offered by Rambus Inc.; and Serial Port Memory Technology (SPMT), developed by the SPMT Consortium and designed to be a royalty-free memory interface.
Other competitive mobile DRAM technologies include Wide I/O, which promises to connect DRAM cores at the silicon level but is not necessarily a mobile technology; LPDDR3, whose specifications remain undefined; and DDR4, a form of standard DRAM not likely to appear until 2013.
Source: IHS iSuppli, USA.
Low-power, double data rate 2 (LPDDR2) is just now becoming the predominant technology in the mobile DRAM space, projected to take 40 percent market share by the second quarter this year, up from 31 percent in the first quarter. The majority of the mobile DRAM market continues to be held by the older LPDDR1 technology—although not for long.
By the fourth quarter this year, the tables will have turned, with LLPDDR2 finally gaining ascendance for the first time and controlling 58 percent of the market, as shown in the figure.
Source: IHS iSuppli, USA.“Once a sleepy backwater of the DRAM market, mobile DRAM now is getting considerably more engineering and development attention from important players like Samsung Electronics Co., Hynix Semiconductor Inc., Elpida Memory Inc. and Micron Technology,” said Mike Howard, principal analyst for DRAM and memory at IHS.
“Unlike standard DRAM, the mobile counterpart for memory uses reduced power, generates a smaller amount of heat and takes up less space—attributes especially suitable for smart phones and other small electronic devices, with their need for greater computing power but possessing limited real estate. Mobile DRAM also is used in digital still cameras, portable media players, portable gaming products and tablets.”
A major challenge to mobile DRAM is its performance for future devices. While LPDDR2 is adequate now for phones and tablets, power consumption and bandwidth remain areas of concern.
For instance, operating at 1.2V, LPDDR2 offers as much as 50 percent power savings per data transfer compared to LPDDR1. However, if the devices of tomorrow perform 10 times as many data transfers—well within conceivable attainment soon—LPDDR2 would come up woefully short.
LPDDR2’s transfer rate of 8.5 gigabytes (GB) per second is also phenomenal compared to 1066 megahertz (MHz) for LPDDR1, but the LPDDR2 rate might not be enough for devices making their debut in the very near future. Feedback from smart phone makers has pointed to the need for rates of 12.8GB per second, which would necessitate LPDDR2 increasing its clock rate to 800MHz. This does not appear feasible, IHS believes.
What’s next in the pipeline?
With the performance thresholds of LPDDR2 likely to be reached and exhausted soon, several mobile DRAM technologies are vying for attention as alternatives. The competing technologies are shown in the attached table.
The current front runners are mobile XDR, offered by Rambus Inc.; and Serial Port Memory Technology (SPMT), developed by the SPMT Consortium and designed to be a royalty-free memory interface.
Other competitive mobile DRAM technologies include Wide I/O, which promises to connect DRAM cores at the silicon level but is not necessarily a mobile technology; LPDDR3, whose specifications remain undefined; and DDR4, a form of standard DRAM not likely to appear until 2013.
Source: IHS iSuppli, USA.
Median pricing for 200mm production CMOS wafers increases at same rate as 300mm wafers QoQ
SAN JOSE, USA: The Global Semiconductor Alliance (GSA) has announced the results of its quarterly Wafer Fabrication & Back-End Pricing Survey, analyzing prices paid per wafer and mask set and for outsourced assembly services by fabless semiconductor companies and integrated device manufacturers (IDMs).
The results of the Q1 2011 Wafer Fabrication & Back-End Pricing Survey include:
* Median pricing for both 200mm and 300mm production CMOS wafers increased by about 5 poercent quarter-over-quarter (QoQ).
* After decreasing for two consecutive quarters, survey participants reported a sequential increase in the median mask set cost for 200mm CMOS wafers. Participants indicated that the median cost increased 21 percent QoQ and 20 percent YoY.
* The median cost for QFN packages with <=64 leads increased 3 percent QoQ.
* 90 percent of survey participants are getting the capacity they need, with the “Yes” percentage increasing by 13 percentage points QoQ.
The survey results provide detailed insight into wafer and mask costs using factors such as development stage, process geometry, number of metal layers, number of poly layers and epitaxial/non-epitaxial processes. Subscribers can also search assembly costs by such factors as package family, leads, units per week and substrate cost.
These results are published in GSA’s quarterly Wafer Fabrication & Back-End Pricing Report which includes a written analysis of the survey results, a downloadable MS Access database of all aggregated results, and interactive online results showing rolling average and median prices for four consecutive quarters by varying factors.
The results of the Q1 2011 Wafer Fabrication & Back-End Pricing Survey include:
* Median pricing for both 200mm and 300mm production CMOS wafers increased by about 5 poercent quarter-over-quarter (QoQ).
* After decreasing for two consecutive quarters, survey participants reported a sequential increase in the median mask set cost for 200mm CMOS wafers. Participants indicated that the median cost increased 21 percent QoQ and 20 percent YoY.
* The median cost for QFN packages with <=64 leads increased 3 percent QoQ.
* 90 percent of survey participants are getting the capacity they need, with the “Yes” percentage increasing by 13 percentage points QoQ.
The survey results provide detailed insight into wafer and mask costs using factors such as development stage, process geometry, number of metal layers, number of poly layers and epitaxial/non-epitaxial processes. Subscribers can also search assembly costs by such factors as package family, leads, units per week and substrate cost.
These results are published in GSA’s quarterly Wafer Fabrication & Back-End Pricing Report which includes a written analysis of the survey results, a downloadable MS Access database of all aggregated results, and interactive online results showing rolling average and median prices for four consecutive quarters by varying factors.
Synopsys announces availability of DesignWare PHY and embedded memory IP for TSMC advanced 28-nm technologies
MOUNTAIN VIEW, USA: Synopsys Inc. announced that it has worked with TSMC to develop a broad portfolio of DesignWare interface PHY IP including SuperSpeed USB 3.0, USB 2.0, HDMI, PCI Express, DDR and SATA as well as embedded memories for TSMC's 28-nanometer (nm) process technology. The collaboration enables designers to incorporate more functionality into their advanced system-on-chips (SoCs), while meeting low power and small silicon area requirements.
As a result of this collaboration, Synopsys has achieved USB logo certification for the DesignWare USB 2.0 picoPHY IP in TSMC's 28-nm process, demonstrating a robust design architecture that can withstand rigorous process, voltage and temperature variations.
In addition, the DesignWare IP portfolio of SiWare Embedded Memory SRAMs has also achieved positive silicon results for TSMC's 28-nm process. The longstanding cooperation between the two companies has resulted in the development of DesignWare PHY IP from 180-nm to 28-nm process technologies, allowing design teams to integrate key industry standard interfaces into their designs with less risk and improved time-to-market.
"TSMC's close relationship with Synopsys through the years has provided mutual customers access to a broad portfolio of high-quality IP solutions for a wide range of TSMC processes," said Suk Lee, director of Design Infrastructure Marketing Division, at TSMC. "Our collaboration with Synopsys on the development of DesignWare PHY and Embedded Memory IP for TSMC's advanced 28-nm process is a natural extension of our successful track record, and further demonstrates our shared commitment to delivering to designers widely-used SoC functionality for their high-performance, low power mobile designs."
"Synopsys' collaboration with TSMC has helped designers cope with the challenges of incorporating advanced interfaces into their SoCs," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "By providing a broad portfolio of IP that has been silicon-proven to be robust in process, voltage and temperature variations for TSMC processes, we can continue to help customers reduce integration risk and speed their creation of differentiated SoCs."
The DesignWare PHY IP for the TSMC 28-nm process is scheduled to be available in Q2 of 2011. The DesignWare IP portfolio of SiWare Embedded Memories for the TSMC 28-nm process is available now.
As a result of this collaboration, Synopsys has achieved USB logo certification for the DesignWare USB 2.0 picoPHY IP in TSMC's 28-nm process, demonstrating a robust design architecture that can withstand rigorous process, voltage and temperature variations.
In addition, the DesignWare IP portfolio of SiWare Embedded Memory SRAMs has also achieved positive silicon results for TSMC's 28-nm process. The longstanding cooperation between the two companies has resulted in the development of DesignWare PHY IP from 180-nm to 28-nm process technologies, allowing design teams to integrate key industry standard interfaces into their designs with less risk and improved time-to-market.
"TSMC's close relationship with Synopsys through the years has provided mutual customers access to a broad portfolio of high-quality IP solutions for a wide range of TSMC processes," said Suk Lee, director of Design Infrastructure Marketing Division, at TSMC. "Our collaboration with Synopsys on the development of DesignWare PHY and Embedded Memory IP for TSMC's advanced 28-nm process is a natural extension of our successful track record, and further demonstrates our shared commitment to delivering to designers widely-used SoC functionality for their high-performance, low power mobile designs."
"Synopsys' collaboration with TSMC has helped designers cope with the challenges of incorporating advanced interfaces into their SoCs," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "By providing a broad portfolio of IP that has been silicon-proven to be robust in process, voltage and temperature variations for TSMC processes, we can continue to help customers reduce integration risk and speed their creation of differentiated SoCs."
The DesignWare PHY IP for the TSMC 28-nm process is scheduled to be available in Q2 of 2011. The DesignWare IP portfolio of SiWare Embedded Memories for the TSMC 28-nm process is available now.
ZILOG releases 16 Bit MINI-Z module and 8 solid state relay design board
MILPITAS, USA & BIEL, SWITZERLAND: Zilog, a wholly owned subsidiary of IXYS Corp. and a trusted supplier of application specific, embedded micro controller (MCU) system-on-chip (SoC) solutions for industrial, power management and consumer applications, today introduced its new Z16MiniZ28 Module.
The Z16MiniZ28 Module is a Dual Inline Pin “stamp” module designed for the customer in mind, to quickly develop prototypes, proofs of concept and products for power management. The Mini-Z Module, which features the 16-bit ZNEO CPU-based Z16F2810 MCU, is designed to be pin-compatible with the Parallax BS2 Series of stamp modules and with Basic Micro’s Basic ATOM Pro 28-M module. This compatibility in the module’s design allows engineers to utilize differing vendors’ base boards which they may already possess in their development arsenal.
Complementing the Z16MiniZ28 Module is Zilog’s new Solid State Relay (SSR) Design Board with 8 independent SSRs. This combination with the Mini-Z product family provides engineers a platform for developing prototypes and products ranging from power grid management, motor controls and HVAC controls to multi-power load control systems. Designed to capitalize on the advanced functionality of the Z16MiniZ28 Module, the Design Board exposes all of the Module’s pins to add external functionality for even more creative power system projects.
The Design Board is compatible with other vendors’ modules, such as the Basic Micro’s ATOM Pro 28-M module and Parallax BS2 Series of Basic STAMP programming boards. Engineers can start with what they already have and add the Mini-Z Module later, when they need its extra features. The Design Board uses a USB-to-serial converter so that there is no longer any need to find a converter or a serial port. The Board is designed to be operated by either a 9V battery or an external power supply.
The Z16MiniZ28 Module is a Dual Inline Pin “stamp” module designed for the customer in mind, to quickly develop prototypes, proofs of concept and products for power management. The Mini-Z Module, which features the 16-bit ZNEO CPU-based Z16F2810 MCU, is designed to be pin-compatible with the Parallax BS2 Series of stamp modules and with Basic Micro’s Basic ATOM Pro 28-M module. This compatibility in the module’s design allows engineers to utilize differing vendors’ base boards which they may already possess in their development arsenal.
Complementing the Z16MiniZ28 Module is Zilog’s new Solid State Relay (SSR) Design Board with 8 independent SSRs. This combination with the Mini-Z product family provides engineers a platform for developing prototypes and products ranging from power grid management, motor controls and HVAC controls to multi-power load control systems. Designed to capitalize on the advanced functionality of the Z16MiniZ28 Module, the Design Board exposes all of the Module’s pins to add external functionality for even more creative power system projects.
The Design Board is compatible with other vendors’ modules, such as the Basic Micro’s ATOM Pro 28-M module and Parallax BS2 Series of Basic STAMP programming boards. Engineers can start with what they already have and add the Mini-Z Module later, when they need its extra features. The Design Board uses a USB-to-serial converter so that there is no longer any need to find a converter or a serial port. The Board is designed to be operated by either a 9V battery or an external power supply.
ST named again among ‘350 Most Admired Companies’
INDIA: STMicroelectronics announced that it was recognized as one of the ‘350 Most Admired Companies’ for the second consecutive year, according to FORTUNE Magazine’s 2011 ‘World’s Most Admired Companies’ survey results.
Within these 350 companies in the overall ranking, STMicroelectronics is one of only eight companies in the semiconductor industry to earn a place in this year’s FORTUNE annual listing, which ranks the top overall most-admired companies and provides industry-specific and regional lists.
Ranked as the sixth most admired company in the semiconductor industry, ST was the second highest-rated company based outside the United States and the highest-rated Europe-based chip maker in the sector.
“ST has long been committed to acting as a responsible corporation that has always emphasized innovation, creating an outstanding broad product portfolio,” said Didier Lamouche, COO of STMicroelectronics. “We are proud and delighted to have been recognized by our partners, suppliers and other stakeholders who contributed to the survey, to be among FORTUNE’s Most Admired Companies. This is definitely a tribute to all ST’s employees and managers who have worked so passionately over the years to make ST the leader it is today.”
All semiconductor companies in the industry-specific ranking were rated based on nine factors, including quality of products or services, quality of management, global competitiveness, and soundness of financial position, to name a few.
STMicroelectronics placed seventh-or-better in six of the nine reputation-attribute categories – including the industry’s fourth highest-rating for social responsibility. Furthermore, it was the highest-rated European semiconductor player in eight of the nine categories.
“Sustainable business and socially responsible practices are especially important to STMicroelectronics, therefore to receive high marks from our peers in that category is extremely rewarding to all of us,” said Lamouche. “It’s a sign that our long-standing initiatives and our beliefs in exemplary corporate citizenship are being recognized – and this is stimulating us to strive for more across all areas.”
Within these 350 companies in the overall ranking, STMicroelectronics is one of only eight companies in the semiconductor industry to earn a place in this year’s FORTUNE annual listing, which ranks the top overall most-admired companies and provides industry-specific and regional lists.
Ranked as the sixth most admired company in the semiconductor industry, ST was the second highest-rated company based outside the United States and the highest-rated Europe-based chip maker in the sector.
“ST has long been committed to acting as a responsible corporation that has always emphasized innovation, creating an outstanding broad product portfolio,” said Didier Lamouche, COO of STMicroelectronics. “We are proud and delighted to have been recognized by our partners, suppliers and other stakeholders who contributed to the survey, to be among FORTUNE’s Most Admired Companies. This is definitely a tribute to all ST’s employees and managers who have worked so passionately over the years to make ST the leader it is today.”
All semiconductor companies in the industry-specific ranking were rated based on nine factors, including quality of products or services, quality of management, global competitiveness, and soundness of financial position, to name a few.
STMicroelectronics placed seventh-or-better in six of the nine reputation-attribute categories – including the industry’s fourth highest-rating for social responsibility. Furthermore, it was the highest-rated European semiconductor player in eight of the nine categories.
“Sustainable business and socially responsible practices are especially important to STMicroelectronics, therefore to receive high marks from our peers in that category is extremely rewarding to all of us,” said Lamouche. “It’s a sign that our long-standing initiatives and our beliefs in exemplary corporate citizenship are being recognized – and this is stimulating us to strive for more across all areas.”
Semtech easy-to-use proximity capacitive touch sensor platform optimized for TV apps
CAMARILLO, USA: Semtech Corp., a leading supplier of analog and mixed-signal semiconductors, announced a new platform of easy-to-use capacitive sensing ICs optimized for the next-generation of energy-efficient, touch button television applications.
The 8-channel SX8660/61 touch sensor platform features integrated LED drivers and an extended, 10cm range of proximity sensing. It is designed to easily replace legacy mechanical button controllers with an analog output interface (AOI) that supports the use of a buzzer for audible feedback making the platform fully compatible with a wide range of television designs.
The capacitive analog interface on the SX8660/61 ICs is designed with a highly accurate analog-to-digital converter (ADC) that provides superior sensitivity to work with thick overlay materials (up to 5mm) for extremely robust ESD immunity and to support a long, 10cm range of proximity detection. With current consumption as low as 70µA at operation, these ICs help designers meet the latest energy-efficiency eco-regulations for televisions.
The SX8660/61 platform also integrates eight, 256-step LED drivers with individual intensity (linear or logarithmic) fading control that is optimized for human vision. This allows design of buttons that automatically fade on when touched and fade off when released, with interval speed and initial and final light intensity levels set by the designer. Special single and continuous breathing modes are also available to enhance visual feedback to the user.
The SX8660/61 platform further simplifies capacitive touch control design and reduces time-to-market with integrated, multi-time programmable firmware that enables users to customize various parameters such as scan time, slave address, channel gain and sensitivity thresholds in their applications, without the need for new firmware development. Additionally, dedicated capacitive sense inputs eliminate the need for external resistors and capacitors, reducing design footprint, bill of materials (BOM) and complexity.
“Unlike competitive alternatives, the SX8660/61 family integrates all the functional blocks necessary for touch sensing and proximity sensing in a tiny footprint that requires zero external components. This simplifies the PCB design and reduces the overall solution BOM cost,” said Sam Massih, Director, Consumer Analog Products for Semtech. “The integrated, advanced features of the SX8660/61 platform, coupled with their low power consumption and AOI makes these ICs ideal for a wide range of energy-efficient TV applications.”
The SX8661 offers a preconfigured quick-start mode for applications requiring proximity sensing and seven buttons, with one AOI and seven LED drivers with PWM fading. The SX8660 is preconfigured with a quick-start mode for applications with eight buttons, two AOIs, one buzzer output and five LED drivers with PWM fading. The GPIOs can also be individually configured for specific application requirements. Both devices feature a smart automatic offset compensation function that eliminates false triggers due to environmental factors such as temperature, humidity and dust. They are offered in a tiny, 4mm x 4mm 28-QFN package and are guaranteed to operate over an extended (-40°C to +85°C) temperature range.
Features of the SX8660/61 platform
* Capacitive touch sensor platform includes eight independent, 256-step LED drivers with auto-lightening mode and individual intensity and fading control.
* Optimized for TV applications with up to two analog output interfaces (AOI-A, AOI-B).
* Proximity sensing up to 10cm (SX8661).
* High-resolution capacitive sensing (able to sense thru overlay materials up to 5mm thick).
* Ultra-low power optimized for energy-efficient applications: 200µA (typ) in active mode; 70µA (typ) in doze mode and 8µA (typ) in sleep mode.
* Automatic offset compensation eliminates false triggers due to environmental factors.
* Zero external components required for sensor input.
* Multi-time, in-field programmable firmware parameters for ultimate flexibility
The eight-channel SX8660 (order code: SX8660I06AULTRT) and SX8661 (order code: SX8661I07AULTRT) are available in production quantities and are priced at $0.98 and $1.37 respectively in 3,000-piece lots. Semtech offers comprehensive design assistance, including field- and factory-based support.
The 8-channel SX8660/61 touch sensor platform features integrated LED drivers and an extended, 10cm range of proximity sensing. It is designed to easily replace legacy mechanical button controllers with an analog output interface (AOI) that supports the use of a buzzer for audible feedback making the platform fully compatible with a wide range of television designs.
The capacitive analog interface on the SX8660/61 ICs is designed with a highly accurate analog-to-digital converter (ADC) that provides superior sensitivity to work with thick overlay materials (up to 5mm) for extremely robust ESD immunity and to support a long, 10cm range of proximity detection. With current consumption as low as 70µA at operation, these ICs help designers meet the latest energy-efficiency eco-regulations for televisions.
The SX8660/61 platform also integrates eight, 256-step LED drivers with individual intensity (linear or logarithmic) fading control that is optimized for human vision. This allows design of buttons that automatically fade on when touched and fade off when released, with interval speed and initial and final light intensity levels set by the designer. Special single and continuous breathing modes are also available to enhance visual feedback to the user.
The SX8660/61 platform further simplifies capacitive touch control design and reduces time-to-market with integrated, multi-time programmable firmware that enables users to customize various parameters such as scan time, slave address, channel gain and sensitivity thresholds in their applications, without the need for new firmware development. Additionally, dedicated capacitive sense inputs eliminate the need for external resistors and capacitors, reducing design footprint, bill of materials (BOM) and complexity.
“Unlike competitive alternatives, the SX8660/61 family integrates all the functional blocks necessary for touch sensing and proximity sensing in a tiny footprint that requires zero external components. This simplifies the PCB design and reduces the overall solution BOM cost,” said Sam Massih, Director, Consumer Analog Products for Semtech. “The integrated, advanced features of the SX8660/61 platform, coupled with their low power consumption and AOI makes these ICs ideal for a wide range of energy-efficient TV applications.”
The SX8661 offers a preconfigured quick-start mode for applications requiring proximity sensing and seven buttons, with one AOI and seven LED drivers with PWM fading. The SX8660 is preconfigured with a quick-start mode for applications with eight buttons, two AOIs, one buzzer output and five LED drivers with PWM fading. The GPIOs can also be individually configured for specific application requirements. Both devices feature a smart automatic offset compensation function that eliminates false triggers due to environmental factors such as temperature, humidity and dust. They are offered in a tiny, 4mm x 4mm 28-QFN package and are guaranteed to operate over an extended (-40°C to +85°C) temperature range.
Features of the SX8660/61 platform
* Capacitive touch sensor platform includes eight independent, 256-step LED drivers with auto-lightening mode and individual intensity and fading control.
* Optimized for TV applications with up to two analog output interfaces (AOI-A, AOI-B).
* Proximity sensing up to 10cm (SX8661).
* High-resolution capacitive sensing (able to sense thru overlay materials up to 5mm thick).
* Ultra-low power optimized for energy-efficient applications: 200µA (typ) in active mode; 70µA (typ) in doze mode and 8µA (typ) in sleep mode.
* Automatic offset compensation eliminates false triggers due to environmental factors.
* Zero external components required for sensor input.
* Multi-time, in-field programmable firmware parameters for ultimate flexibility
The eight-channel SX8660 (order code: SX8660I06AULTRT) and SX8661 (order code: SX8661I07AULTRT) are available in production quantities and are priced at $0.98 and $1.37 respectively in 3,000-piece lots. Semtech offers comprehensive design assistance, including field- and factory-based support.
Mentor Graphics outlines strategy for 3D-IC design, verification and testing
Design Automation Conference 2011, WILSONVILLE, USA: Mentor Graphics Corp. described its strategy for meeting the EDA requirements of designing, verifying, manufacturing and testing integrated circuit products using multi-die vertical stacking technology, popularly referred to as “3D-IC.” It also announced its 3D-IC testing solution employing multiple components of the Tessent® design-for-test product line for integrated multi-die hierarchical scan and built-in self-test (BIST) methodologies.
“3D-IC is generating a huge amount of interest and exploration because it offers an alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package,” said Walden C. Rhines, CEO and chairman of Mentor Graphics. “We’re validating the use of our products for successful 3D-IC development with our leading customers who are actively working on products employing multiple die stacking approaches, including the use of interposers, or so-called ‘2.5D,’ and full 3D with through silicon vias (TSVs). Regardless of which approach a customer selects, customers will have a Mentor solution available to them.”
“Today, we’re describing our 3D-IC test solution, which addresses both 2.5 and full 3D test requirements,” said Joseph Sawicki, vice president and general manager of the design-to-silicon division at Mentor Graphics. “At the upcoming Design Automation Conference we will talk more about our multi-die design rule checking, layout versus schematic, and extraction solutions for 3D-IC, which will address the impact of TSVs on physical verification. And, in the coming months we will describe solutions for interposer and package routing as well as product roadmaps to meet the future needs of the market.”
Hierarchical test for 3D-IC
The Tessent solution for 3D-IC test provides a combination of capabilities that work together to deliver the highest test quality while reducing development time and manufacturing test costs. The combination of the Tessent TestKompress and Tessent LogicBIST logic test products create both highly compressed deterministic scan patterns, and on-chip generated random patterns that together ensure very high coverage while minimizing test time.
This is critical since low defect rates at the “known good die” stage are critical to achieving acceptable package yield in 3D-IC production. Low test time becomes even more important for 3D because die stacking may require additional test stages for partial assemblies.
Another key requirement of 3D-IC is the ability to fully test the assembled multi-die structure, which presents challenges in test access and throughput. Successful testing depends on the ability to combine logic built-in self-test (LBIST), memory BIST, analog test and boundary scan test in an integrated fashion, and to distribute test commands and patterns across multiple die in a hierarchical manner.
The Mentor Tessent TestKompress, Tessent LogicBIST, Tessent MemoryBIST, Tessent BoundaryScan, Tessent PLLTest and Tessent SerdesTest products work together to provide a seamless infrastructure for testing 3D structures including processor cores, logic, memory and high-speed I/O. A key advantage of the Tessent solution is the ability to reuse die-level ATPG and BIST tests at the package level. The Tessent insertion technology enables the creation of a hierarchical DFT architecture that is based on the IEEE 1149.1 standard with 3D-related enhancements such as TSV-based “test elevators.”
This test distribution and control architecture enables die-level patterns to be routed through multiple die after packaging. Scan patterns can target TSV interconnects by accessing scan chains on multiple die. In addition, die-targeted ATPG patterns can be retargeted to the package level with automatic pattern re-timing, allowing engineers to reuse patterns and reduce test development time.
The Tessent MemoryBIST product provides at-speed testing of stacked memory die with support for all popular DRAM protocols, and allows memory parameters (address size, waveforms) and test algorithms to be programmed post-silicon. This allows memory BIST controllers in a logic die to handle a variety of memory die stacked on top for different product variations. The product also supports at-speed testing of memory buses, which covers both bond wires and TSV interconnects. A shared-bus capability enables test of multiple memory die on the same interconnect.
“3D-IC is generating a huge amount of interest and exploration because it offers an alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package,” said Walden C. Rhines, CEO and chairman of Mentor Graphics. “We’re validating the use of our products for successful 3D-IC development with our leading customers who are actively working on products employing multiple die stacking approaches, including the use of interposers, or so-called ‘2.5D,’ and full 3D with through silicon vias (TSVs). Regardless of which approach a customer selects, customers will have a Mentor solution available to them.”
“Today, we’re describing our 3D-IC test solution, which addresses both 2.5 and full 3D test requirements,” said Joseph Sawicki, vice president and general manager of the design-to-silicon division at Mentor Graphics. “At the upcoming Design Automation Conference we will talk more about our multi-die design rule checking, layout versus schematic, and extraction solutions for 3D-IC, which will address the impact of TSVs on physical verification. And, in the coming months we will describe solutions for interposer and package routing as well as product roadmaps to meet the future needs of the market.”
Hierarchical test for 3D-IC
The Tessent solution for 3D-IC test provides a combination of capabilities that work together to deliver the highest test quality while reducing development time and manufacturing test costs. The combination of the Tessent TestKompress and Tessent LogicBIST logic test products create both highly compressed deterministic scan patterns, and on-chip generated random patterns that together ensure very high coverage while minimizing test time.
This is critical since low defect rates at the “known good die” stage are critical to achieving acceptable package yield in 3D-IC production. Low test time becomes even more important for 3D because die stacking may require additional test stages for partial assemblies.
Another key requirement of 3D-IC is the ability to fully test the assembled multi-die structure, which presents challenges in test access and throughput. Successful testing depends on the ability to combine logic built-in self-test (LBIST), memory BIST, analog test and boundary scan test in an integrated fashion, and to distribute test commands and patterns across multiple die in a hierarchical manner.
The Mentor Tessent TestKompress, Tessent LogicBIST, Tessent MemoryBIST, Tessent BoundaryScan, Tessent PLLTest and Tessent SerdesTest products work together to provide a seamless infrastructure for testing 3D structures including processor cores, logic, memory and high-speed I/O. A key advantage of the Tessent solution is the ability to reuse die-level ATPG and BIST tests at the package level. The Tessent insertion technology enables the creation of a hierarchical DFT architecture that is based on the IEEE 1149.1 standard with 3D-related enhancements such as TSV-based “test elevators.”
This test distribution and control architecture enables die-level patterns to be routed through multiple die after packaging. Scan patterns can target TSV interconnects by accessing scan chains on multiple die. In addition, die-targeted ATPG patterns can be retargeted to the package level with automatic pattern re-timing, allowing engineers to reuse patterns and reduce test development time.
The Tessent MemoryBIST product provides at-speed testing of stacked memory die with support for all popular DRAM protocols, and allows memory parameters (address size, waveforms) and test algorithms to be programmed post-silicon. This allows memory BIST controllers in a logic die to handle a variety of memory die stacked on top for different product variations. The product also supports at-speed testing of memory buses, which covers both bond wires and TSV interconnects. A shared-bus capability enables test of multiple memory die on the same interconnect.
Magma's Excalibur-Litho efficiently integrates real-time data from semiconductor manufacturing floor
BANGALORE, INDIA: Magma Design Automation Inc., a provider of chip design software, has announced Excalibur-Litho, a complete fab analysis framework that supports the development and monitoring of advanced lithography solutions.
Excalibur-Litho is the first system to efficiently integrate design and real-time data from the semiconductor manufacturing floor, including defectivity, metrology and tool history, enabling an unmatched level of data analysis, monitoring and process control. Excalibur-Litho optimizes yield ramps with built-in solutions for litho qualification through the proprietary coupling of design-based binning, electrical cross mapping, and fab-wide data correlation. This enables unprecedented defect isolation and root cause analysis.
“Excalibur-Litho is based on a proven fab analysis framework that provides comprehensive examination of inline lithography-based defects,” said Ankush Oberai, general manager and vice president of Magma’s Fab Analysis Business Unit. “By leveraging a proven infrastructure that has access to both design and fab data, Excalibur-Litho turns data into knowledge, accelerating lithography-based process improvement.”
Magma and Applied Materials Inc. announced on Feb. 28 a collaborative effort to integrate Magma’s CAD-based navigation and yield analysis software, Materials’ advanced inspection tools, such as the Applied UVision 4 system.
“This unique combination of design and manufacturing tools has accelerated lithography qualification and enabled quicker yield ramp at multiple customers for the development and production of advanced technology nodes,” said Erez Paran, manager, Integrated Solutions for Applied Materials’ Process Diagnostics and Control business unit, which includes Excalibur-Litho, with Applied Excalibur-Litho:
From data to knowledge
Excalibur-Litho collects and organizes data from the manufacturing process, including defectivity, metrology, and electrical tools and manufacturing execution system (MES) data. Wafer information is stacked and easily cross-mapped to any one of the layout, schematic or netlist design representations for easy analysis.
Excalibur-Litho is built on a revolutionary open-architecture database developed by Magma that enables safe and secured CAD access and easy fab integration. This open architecture also ensures interoperability with most inspection tools and yield analysis databases.
Excalibur-Litho is the first system to efficiently integrate design and real-time data from the semiconductor manufacturing floor, including defectivity, metrology and tool history, enabling an unmatched level of data analysis, monitoring and process control. Excalibur-Litho optimizes yield ramps with built-in solutions for litho qualification through the proprietary coupling of design-based binning, electrical cross mapping, and fab-wide data correlation. This enables unprecedented defect isolation and root cause analysis.
“Excalibur-Litho is based on a proven fab analysis framework that provides comprehensive examination of inline lithography-based defects,” said Ankush Oberai, general manager and vice president of Magma’s Fab Analysis Business Unit. “By leveraging a proven infrastructure that has access to both design and fab data, Excalibur-Litho turns data into knowledge, accelerating lithography-based process improvement.”
Magma and Applied Materials Inc. announced on Feb. 28 a collaborative effort to integrate Magma’s CAD-based navigation and yield analysis software, Materials’ advanced inspection tools, such as the Applied UVision 4 system.
“This unique combination of design and manufacturing tools has accelerated lithography qualification and enabled quicker yield ramp at multiple customers for the development and production of advanced technology nodes,” said Erez Paran, manager, Integrated Solutions for Applied Materials’ Process Diagnostics and Control business unit, which includes Excalibur-Litho, with Applied Excalibur-Litho:
From data to knowledge
Excalibur-Litho collects and organizes data from the manufacturing process, including defectivity, metrology, and electrical tools and manufacturing execution system (MES) data. Wafer information is stacked and easily cross-mapped to any one of the layout, schematic or netlist design representations for easy analysis.
Excalibur-Litho is built on a revolutionary open-architecture database developed by Magma that enables safe and secured CAD access and easy fab integration. This open architecture also ensures interoperability with most inspection tools and yield analysis databases.
austriamicrosystems releases 0.18µm High-Voltage CMOS process for volume production
UNTERPREMSTAETTEN, AUSTRIA: austriamicrosystems announced the conditional release for volume production of its advanced 0.18µm High-Voltage CMOS process technology "H18” which will be manufactured in IBM’s 200mm Burlington wafer facility. Jointly developed with IBM, the 0.18µm High-Voltage CMOS process is the 6th generation of continuously improved High-Voltage CMOS technologies developed at austriamicrosystems.
Featuring a new level of RF and HV integration capability on a single IC, the new 0.18µm High-Voltage CMOS process offers the highest integration density, up to 118k gates/mm², enabling SoC applications (System-on-Chip) as well as best-in-class power-on resistance (Rdson) which directly results in a silicon area reduction. The integration capabilities of H18 enable design houses and IDMs to create new applications in areas such as smart sensors, sensor interface devices, smart meters, industrial and building controls and LED lighting control. H18 is uniquely positioned to create the next generation of smarter interconnected devices.
Only a few mask level adders are required on top of the fully compatible CMOS base process to implement high-voltage capabilities, making the H18 process one of the most cost competitive 0.18µm High-Voltage CMOS technologies in the market. The process allows the integration of 1.8V, 5V, 20V and 50V devices on a single chip without any process modifications. Process features such as Schottky barrier diode, high-resistive and precision poly, single- and dual metal-insulator-metal (MIM) capacitors, varactors and up to 7 metal layers including thick last metal complete the state-of-the art High-Voltage CMOS process.
“We are very pleased to have jointly developed an industry-benchmark 0.18µm High-Voltage CMOS process with IBM where austriamicrosystems enabled the technology with its leading high-voltage expertise. The process technology is finding tremendous interest in the market for allowing modular SoC designs integrating analog high-voltage blocks with RF CMOS, extended digital functions and micro-controllers,” states Thomas Riener, senior VP and GM of austriamicrosystems' Full Service Foundry business unit. “The H18 technology is now ramping in a broad range of smart green applications such as power management and LED driver applications.”
“The combination of austriamicrosystems’ leadership in high voltage and IBM’s high density RF CMOS heritage has created unique value with the H18 process”, said Regina Darmoni, Director of Specialty Foundry at IBM Microelectronics. “H18 represents a new paradigm of semiconductor integration, enabling smarter and more cost-effective “endpoint” devices as part of the “Internet of Things”. Photovoltaics, Smart Sensors, Smart Meters and LED drivers are just some of the Smarter Planet applications which will benefit. We look forward to our continued collaboration with austriamicrosystems in this expanding market.”
Featuring a new level of RF and HV integration capability on a single IC, the new 0.18µm High-Voltage CMOS process offers the highest integration density, up to 118k gates/mm², enabling SoC applications (System-on-Chip) as well as best-in-class power-on resistance (Rdson) which directly results in a silicon area reduction. The integration capabilities of H18 enable design houses and IDMs to create new applications in areas such as smart sensors, sensor interface devices, smart meters, industrial and building controls and LED lighting control. H18 is uniquely positioned to create the next generation of smarter interconnected devices.
Only a few mask level adders are required on top of the fully compatible CMOS base process to implement high-voltage capabilities, making the H18 process one of the most cost competitive 0.18µm High-Voltage CMOS technologies in the market. The process allows the integration of 1.8V, 5V, 20V and 50V devices on a single chip without any process modifications. Process features such as Schottky barrier diode, high-resistive and precision poly, single- and dual metal-insulator-metal (MIM) capacitors, varactors and up to 7 metal layers including thick last metal complete the state-of-the art High-Voltage CMOS process.
“We are very pleased to have jointly developed an industry-benchmark 0.18µm High-Voltage CMOS process with IBM where austriamicrosystems enabled the technology with its leading high-voltage expertise. The process technology is finding tremendous interest in the market for allowing modular SoC designs integrating analog high-voltage blocks with RF CMOS, extended digital functions and micro-controllers,” states Thomas Riener, senior VP and GM of austriamicrosystems' Full Service Foundry business unit. “The H18 technology is now ramping in a broad range of smart green applications such as power management and LED driver applications.”
“The combination of austriamicrosystems’ leadership in high voltage and IBM’s high density RF CMOS heritage has created unique value with the H18 process”, said Regina Darmoni, Director of Specialty Foundry at IBM Microelectronics. “H18 represents a new paradigm of semiconductor integration, enabling smarter and more cost-effective “endpoint” devices as part of the “Internet of Things”. Photovoltaics, Smart Sensors, Smart Meters and LED drivers are just some of the Smarter Planet applications which will benefit. We look forward to our continued collaboration with austriamicrosystems in this expanding market.”
Average DRAM density in tablets to rise by 147 percent in 2011
EL SEGUNDO, USA: The amount of dynamic random access memory (DRAM) in media tablets will jump 147 percent in 2011 to an average of 676 megabytes (MB), according to new IHS iSuppli research.
“With tablets handling more data-intensive applications such as video, the average DRAM content in these platforms during 2011 will be about two-and-a-half times more than last year’s 274MB,” said Mike Howard, principal analyst for DRAM & memory at IHS. “The rapid expansion will continue next year, when average DRAM in tablets reaches approximately 1.3 gigabytes (GB). In 2015, tablets will have DRAM content similar to that of today’s laptops, reaching 3.7GB.”
Tablet DRAM density will expand at a compound annual growth rate (CAGR) of 68 percent from 2010 to 2015.
Despite the substantial increase this year of DRAM content in tablets, growth could have been even greater if Apple Inc.’s recently released iPad 2 turned out to have the full 1GB of DRAM—similar to the iPad’s competitors, which prior assumptions seemed to indicate—instead of just 512MB. In comparison, the Xoom by Motorola, the TouchPad by Hewlett-Packard and the BlackBerry Playbook by Research In Motion—tablet devices competing with the iPad—each has 1GB of DRAM.
Apple’s choice to include only 512MB of DRAM isn’t really surprising, however, given that the company is attempting to focus on the overall tablet experience rather than its product specifications, IHS believes. Just the same, Apple’s dominance of the tablet market at present—taken in consideration with the 512MB in its iPad devices—means that the overall increase in DRAM content this year was much less than if Apple had used 1GB.
Meanwhile, speculation abounds that the next version of the iPad might feature a Retina display similar to Apple’s iPhone 4 and iPod Touch. If this turns out to be true, DRAM content surely will jump to 1GB, Howard predicts, which then would alter the forecast and result in even greater DRAM content growth in tablet devices. Future releases of the iOS operating system by Apple might also unleash iPad functionality that could require more DRAM.
DRAM growth in tablets is mirrored by a similar increase of DRAM content this year in smart phones, projected to grow 62 percent; and in tablets, expected to climb 33 percent. Around the 2012 to 2013 time frame, tablets will become a significant DRAM category rivaling smart phones, IHS iSuppli research indicates. While both tablets and smart phones use less DRAM content per device than PCs, their combined shipments in 2011 will outnumber those of PCs, making them categories well worth watching in the DRAM arena.
Source: IHS iSuppli, USA.
“With tablets handling more data-intensive applications such as video, the average DRAM content in these platforms during 2011 will be about two-and-a-half times more than last year’s 274MB,” said Mike Howard, principal analyst for DRAM & memory at IHS. “The rapid expansion will continue next year, when average DRAM in tablets reaches approximately 1.3 gigabytes (GB). In 2015, tablets will have DRAM content similar to that of today’s laptops, reaching 3.7GB.”
Tablet DRAM density will expand at a compound annual growth rate (CAGR) of 68 percent from 2010 to 2015.
Despite the substantial increase this year of DRAM content in tablets, growth could have been even greater if Apple Inc.’s recently released iPad 2 turned out to have the full 1GB of DRAM—similar to the iPad’s competitors, which prior assumptions seemed to indicate—instead of just 512MB. In comparison, the Xoom by Motorola, the TouchPad by Hewlett-Packard and the BlackBerry Playbook by Research In Motion—tablet devices competing with the iPad—each has 1GB of DRAM.
Apple’s choice to include only 512MB of DRAM isn’t really surprising, however, given that the company is attempting to focus on the overall tablet experience rather than its product specifications, IHS believes. Just the same, Apple’s dominance of the tablet market at present—taken in consideration with the 512MB in its iPad devices—means that the overall increase in DRAM content this year was much less than if Apple had used 1GB.
Meanwhile, speculation abounds that the next version of the iPad might feature a Retina display similar to Apple’s iPhone 4 and iPod Touch. If this turns out to be true, DRAM content surely will jump to 1GB, Howard predicts, which then would alter the forecast and result in even greater DRAM content growth in tablet devices. Future releases of the iOS operating system by Apple might also unleash iPad functionality that could require more DRAM.
DRAM growth in tablets is mirrored by a similar increase of DRAM content this year in smart phones, projected to grow 62 percent; and in tablets, expected to climb 33 percent. Around the 2012 to 2013 time frame, tablets will become a significant DRAM category rivaling smart phones, IHS iSuppli research indicates. While both tablets and smart phones use less DRAM content per device than PCs, their combined shipments in 2011 will outnumber those of PCs, making them categories well worth watching in the DRAM arena.
Source: IHS iSuppli, USA.
SEMI reports 2010 global semiconductor materials sales of $43.55 billion
SINGAPORE: The global semiconductor materials market increased 25 percent in 2010 compared to 2009 as the semiconductor industry shipped record units. Record device shipments are primarily responsible for the record revenues experienced by the materials industry, surpassing the previous high of $42.67 billion set in 2007. An outstanding growth rate for the ROW region, including Singapore, Malaysia, Philippines and other areas of SEA, was 21 percent from 2009 to 2010.
Semiconductor materials market revenues totaled $43.55 billion globally in 2010. Total wafer fabrication materials and packaging materials were $22.93 billion and $20.63 billion, respectively. Comparable revenues for these segments in 2009 were $17.75 billion for wafer fabrication materials and $17.09 billion for packaging materials. Significant increases in silicon and advanced packaging substrates revenues contributed to the year-over-year growth of the total semiconductor materials market.
Japan remains the largest consumer of semiconductor materials with $9.20 billion in total sales, though the materials market in Taiwan reached $9.11 billion due to its large foundry and advanced packaging base. All regional markets experienced double-digit growth. Rising gold metal prices propelled revenues in regions with strong packaging bases. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets).
Source: SEMI, USA.
Semiconductor materials market revenues totaled $43.55 billion globally in 2010. Total wafer fabrication materials and packaging materials were $22.93 billion and $20.63 billion, respectively. Comparable revenues for these segments in 2009 were $17.75 billion for wafer fabrication materials and $17.09 billion for packaging materials. Significant increases in silicon and advanced packaging substrates revenues contributed to the year-over-year growth of the total semiconductor materials market.
Japan remains the largest consumer of semiconductor materials with $9.20 billion in total sales, though the materials market in Taiwan reached $9.11 billion due to its large foundry and advanced packaging base. All regional markets experienced double-digit growth. Rising gold metal prices propelled revenues in regions with strong packaging bases. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets).
Source: SEMI, USA.
Mentor Graphics announces intention to offer convertible subordinated debentures
WILSONVILLE, USA: Mentor Graphics Corp. announced its intention to commence a private placement, subject to market conditions, of $220 million in aggregate principal amount of the company’s Convertible Subordinated Debentures due 2031 to be issued in reliance on Rule 144A under the Securities Act of 1933, as amended. The interest rate, conversion rate and offering price are to be determined by negotiations between the company and the initial purchasers of the debentures.
The company expects to grant the initial purchasers a 13-day option to purchase up to an additional $33 million aggregate principal amount of convertible subordinated debentures to cover overallotments, if any.
The company intends to use the net proceeds from the private placement to repurchase up to $25.0 million of its outstanding common stock, to repay the outstanding amounts owing under its $18.5 million aggregate principal amount term loan due 2013 and, along with available cash on hand, to retire, through repurchases or redemption, the outstanding principal and interest on its 6.25 percent Convertible Subordinated Debentures due 2026. If the overallotment option is exercised, the company intends to use any remaining net proceeds for general corporate purposes, including capital expenditures and working capital.
This announcement is neither an offer to sell nor a solicitation to buy any of these securities and shall not constitute an offer, solicitation or sale in any jurisdiction in which such offer, solicitation or sale is unlawful.
The debentures and any common stock issuable upon conversion of the debentures have not been registered under the Securities Act of 1933, as amended, or under any state securities laws and may not be offered or sold in the United States absent registration or an applicable exemption from registration requirements.
The company expects to grant the initial purchasers a 13-day option to purchase up to an additional $33 million aggregate principal amount of convertible subordinated debentures to cover overallotments, if any.
The company intends to use the net proceeds from the private placement to repurchase up to $25.0 million of its outstanding common stock, to repay the outstanding amounts owing under its $18.5 million aggregate principal amount term loan due 2013 and, along with available cash on hand, to retire, through repurchases or redemption, the outstanding principal and interest on its 6.25 percent Convertible Subordinated Debentures due 2026. If the overallotment option is exercised, the company intends to use any remaining net proceeds for general corporate purposes, including capital expenditures and working capital.
This announcement is neither an offer to sell nor a solicitation to buy any of these securities and shall not constitute an offer, solicitation or sale in any jurisdiction in which such offer, solicitation or sale is unlawful.
The debentures and any common stock issuable upon conversion of the debentures have not been registered under the Securities Act of 1933, as amended, or under any state securities laws and may not be offered or sold in the United States absent registration or an applicable exemption from registration requirements.
ISSI announces family of 512Mb DDR DRAMs
SAN JOSE, USA: Integrated Silicon Solution Inc., a leader in advanced memory solutions, today introduced a family of 512Mb DDR SDRAMs with speeds up to 200Mhz, targeted for automotive, communications, and industrial applications. The introduction of this product family now, using advanced technology, enables ISSI to provide the long term product support required by these targeted applications.
These devices have an operating voltage of 2.5V, and are available in 64Mx8, 32Mx16, and 16Mx32 configurations. Temperature ranges available are 0 to 70C, -40 to 85C, and -40 to 105C. The 64Mx8 (IS43R86400D) and 32Mx16 (IS43R16320D) are available in both a 66-pin TSOP-II and in 60-ball BGA packages. A 16Mx32 (IS43R32160D) will be available in a 144-ball BGA package.
512Mb DDR SDRAMs are used in a variety of applications including automotive telematics, medical imaging and analysis, switches and routers, set-top boxes, and modems. ISSI is making this product available now.
Pat Lasserre, ISSI director of strategic marketing, said: "512Mb DDR SDRAMs have been widely adopted in communication applications such as enterprise switches, core and edge routers, PON, DSLAMs, and base stations. Long-term product support, oftentimes up to 10 years or beyond, is required for those applications. Additionally, since some of those products are in outdoor environments, industrial temperature is also a requirement."
"The 512Mb DDR offers a new dimension to our long-term support for our automotive customers that use processors with this interface. Our camera, navigation and infotainment automotive customers appreciate that this product is available from ISSI in leaded BGA and with an operating range up to 105C," added Lyn Zastrow, ISSI vice president of the Automotive Business Unit.
In addition to the 512Mb DDR SDRAM product family, ISSI offers SDR, DDR, mobile SDR/DDR, and DDR2 SDRAM product families in a variety of densities, organizations, and temperature ranges as well as a complete line of SRAMs targeted for automotive, networking, telecom, industrial and consumer applications.
These devices have an operating voltage of 2.5V, and are available in 64Mx8, 32Mx16, and 16Mx32 configurations. Temperature ranges available are 0 to 70C, -40 to 85C, and -40 to 105C. The 64Mx8 (IS43R86400D) and 32Mx16 (IS43R16320D) are available in both a 66-pin TSOP-II and in 60-ball BGA packages. A 16Mx32 (IS43R32160D) will be available in a 144-ball BGA package.
512Mb DDR SDRAMs are used in a variety of applications including automotive telematics, medical imaging and analysis, switches and routers, set-top boxes, and modems. ISSI is making this product available now.
Pat Lasserre, ISSI director of strategic marketing, said: "512Mb DDR SDRAMs have been widely adopted in communication applications such as enterprise switches, core and edge routers, PON, DSLAMs, and base stations. Long-term product support, oftentimes up to 10 years or beyond, is required for those applications. Additionally, since some of those products are in outdoor environments, industrial temperature is also a requirement."
"The 512Mb DDR offers a new dimension to our long-term support for our automotive customers that use processors with this interface. Our camera, navigation and infotainment automotive customers appreciate that this product is available from ISSI in leaded BGA and with an operating range up to 105C," added Lyn Zastrow, ISSI vice president of the Automotive Business Unit.
In addition to the 512Mb DDR SDRAM product family, ISSI offers SDR, DDR, mobile SDR/DDR, and DDR2 SDRAM product families in a variety of densities, organizations, and temperature ranges as well as a complete line of SRAMs targeted for automotive, networking, telecom, industrial and consumer applications.
Cadence releases industry’s first wide I/O memory controller IP solution
SAN JOSE, USA: Cadence Design Systems Inc. announced that it is first to market with a licensable, wide I/O memory controller core, along with an integration environment, that brings PC-like performance to mobile applications like smartphones and tablets.
Enabling up to four times the performance of conventional memory interfaces, the Cadence wide I/O interface not only meets the performance metrics of the proposed specification, but includes unique optimizations such as traffic reordering and several low-power features that lead to better overall system operation. Complemented by memory models, verification IP (VIP) and a sophisticated 3D IC design methodology, the wide I/O IP lowers the risk and overall cost of SoC design.
“We understand that customers not only need robust IP, but also require sophisticated technologies and methodologies for successful integration into a design,” said Vishal Kapoor, VP of marketing for the SoC Realization Group at Cadence.
“The Denali acquisition has given us access to over a decade of experience in advanced memory and storage controller IP. When combined with our exceptional 3D IC technologies and services, we give mobile designers a holistic, proven approach to the development of differentiated SoCs that meet the unique space, performance and power requirements of mobile systems.” According to Cadence, the IP is already in use by a high-profile customer on two separate projects.
Wide I/O, a memory interface standard in review at JEDEC, defines a 512-bit wide interface to dramatically increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8 gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions.
The wide I/O interface allows a large array of low-cost and low-power connections between an application processor and the DRAM stacked on top of it. The result is a system that can achieve higher bandwidth with less power while also meeting the goals of reduced PCB area and component height. As a result, it is critical that designers also have access to advanced 3D IC assembly and design methodologies.
Differentiated features optimize power and performance at system-level
Designed to enable maximum system-level performance, the wide I/O memory controller includes advanced algorithms to ensure highly efficient data transfer and to intelligently schedule transactions, delivering unprecedented sustained and peak performance for mobile applications. The IP has the capability of reordering traffic by monitoring system transactions and delineating between low priority and system critical tasks. These unique capabilities enable the IP to maximize bandwidth and minimize latency on critical transactions.
The Cadence wide I/O interface also goes beyond the proposed low-power metrics of the standard, offering additional power-saving features such as “traffic sensing,” which automatically adjusts the power consumption based on the type of traffic. The IP has been designed to support operation at multiple frequencies, and allows designers to implement advanced power-control techniques, such as dynamic voltage and frequency scaling (DVFS), to reduce power even further. A flexible and configurable design allows the memory controller IP to be custom-fit for each SoC, further reducing time-to-market and risk.
Applying EDA360 Vision to wide I/O and 3D IC design
Because the majority of wide I/O designs will require stacking of memory on top of logic, designers will need a sophisticated, comprehensive 3D IC platform for realizing their SoCs. The Cadence 3D IC platform includes advanced capabilities, such as support for through-silicon vias (TSVs), to enable the use of vertical electrical connections for significantly reduced board space, cost and power.
A 3D IC approach also requires expertise in all aspects of design, from digital and analog circuitry to packaging and PCB design layout. Offering digital, mixed-signal and analog end-to-end flows, as well as advanced PCB layout expertise, Cadence offers the holistic approach required to successfully integrate the wide I/O interface onto an SoC.
The wide I/O IP and integration platform are an important step toward achieving the EDA360 vision outlined by Cadence last year. The vision states that semiconductor companies can no longer just provide component IP, but must deliver solutions that ensure smooth integration of that IP into SoCs. The solution enables customers to move toward a key tenet of the vision, called SoC Realization, which seeks to ease IP integration and enable customers to realize SoCs with reduced risk and cost.
The Cadence wide I/O memory controller and supporting VIP are available now.
Enabling up to four times the performance of conventional memory interfaces, the Cadence wide I/O interface not only meets the performance metrics of the proposed specification, but includes unique optimizations such as traffic reordering and several low-power features that lead to better overall system operation. Complemented by memory models, verification IP (VIP) and a sophisticated 3D IC design methodology, the wide I/O IP lowers the risk and overall cost of SoC design.
“We understand that customers not only need robust IP, but also require sophisticated technologies and methodologies for successful integration into a design,” said Vishal Kapoor, VP of marketing for the SoC Realization Group at Cadence.
“The Denali acquisition has given us access to over a decade of experience in advanced memory and storage controller IP. When combined with our exceptional 3D IC technologies and services, we give mobile designers a holistic, proven approach to the development of differentiated SoCs that meet the unique space, performance and power requirements of mobile systems.” According to Cadence, the IP is already in use by a high-profile customer on two separate projects.
Wide I/O, a memory interface standard in review at JEDEC, defines a 512-bit wide interface to dramatically increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8 gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions.
The wide I/O interface allows a large array of low-cost and low-power connections between an application processor and the DRAM stacked on top of it. The result is a system that can achieve higher bandwidth with less power while also meeting the goals of reduced PCB area and component height. As a result, it is critical that designers also have access to advanced 3D IC assembly and design methodologies.
Differentiated features optimize power and performance at system-level
Designed to enable maximum system-level performance, the wide I/O memory controller includes advanced algorithms to ensure highly efficient data transfer and to intelligently schedule transactions, delivering unprecedented sustained and peak performance for mobile applications. The IP has the capability of reordering traffic by monitoring system transactions and delineating between low priority and system critical tasks. These unique capabilities enable the IP to maximize bandwidth and minimize latency on critical transactions.
The Cadence wide I/O interface also goes beyond the proposed low-power metrics of the standard, offering additional power-saving features such as “traffic sensing,” which automatically adjusts the power consumption based on the type of traffic. The IP has been designed to support operation at multiple frequencies, and allows designers to implement advanced power-control techniques, such as dynamic voltage and frequency scaling (DVFS), to reduce power even further. A flexible and configurable design allows the memory controller IP to be custom-fit for each SoC, further reducing time-to-market and risk.
Applying EDA360 Vision to wide I/O and 3D IC design
Because the majority of wide I/O designs will require stacking of memory on top of logic, designers will need a sophisticated, comprehensive 3D IC platform for realizing their SoCs. The Cadence 3D IC platform includes advanced capabilities, such as support for through-silicon vias (TSVs), to enable the use of vertical electrical connections for significantly reduced board space, cost and power.
A 3D IC approach also requires expertise in all aspects of design, from digital and analog circuitry to packaging and PCB design layout. Offering digital, mixed-signal and analog end-to-end flows, as well as advanced PCB layout expertise, Cadence offers the holistic approach required to successfully integrate the wide I/O interface onto an SoC.
The wide I/O IP and integration platform are an important step toward achieving the EDA360 vision outlined by Cadence last year. The vision states that semiconductor companies can no longer just provide component IP, but must deliver solutions that ensure smooth integration of that IP into SoCs. The solution enables customers to move toward a key tenet of the vision, called SoC Realization, which seeks to ease IP integration and enable customers to realize SoCs with reduced risk and cost.
The Cadence wide I/O memory controller and supporting VIP are available now.
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