Novelics expands memory IP offering to 40nm

LAGUNA HILLS, USA: Novelics Corp., a leading provider of semiconductor embedded memory IP, today announced the expansion of its portfolio with the addition of coolSRAM-6T embedded memory IP and MemQuest compiler which are enhanced with Novelics 3G optimizations. This IP is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs.

This IP enables ASSP and ASIC designers to achieve higher performance and more power-efficient system-on-chips (SoCs).

3rd generation (3G) optimizations for coolSRAM-6T memory IP in 40nm technology
Content and feature-rich products require faster, more power-efficient SoCs with increasingly large amounts of on-chip memory. Novelics MemQuest compiler environment enables architectural analysis for access time, active power, leakage, and area. coolSRAM-6T IP includes an embedded grid-style power mesh.

The power supply lines are available for user tapping, which are located on Metal 4 for best power integrity and simplest IR-drop analysis. This arrangement can support up to a 512 bit-wide bus to achieve great bandwidth and g up to 2 Mbits of block size.

For small geometries such as 40nm, leakage power constitutes a large portion of power consumption. SOC designers are forced to make a tradeoff between speed and design leakage. Therefore coolSRAM-6T offers options to use standard Vt (SVT) transistors or High Vt (HVT) transistors to achieve the best tradeoffs between speed and leakage.

For further reduction of leakage, Novelics’ advanced source biasing technique is offered. This is complemented with advanced power gating techniques. Three easy to use power modes are offered: These are (1) a low leakage active mode when an operation is performed, (2) a lower leakage standby mode where data is retained but no operations can be performed, and (3) a sleep mode where leakage is minimized and data is destroyed.

Novelics has also applied innovative techniques to minimize memory latency and maximize speed by application of high speed / low power decode logic, and implementation of ultra fast output circuit paths. High speed designers can continuously benefit from Novelics’ edged-based clocking scheme to achieve the best speed with no restriction on clock duty cycle.

Other application specific options such as row and column redundancy, ECC, MUX for BIST and DFT scan are also offered to achieve optimum yield.

“Embedded memory typically represents 30-60 percent of the transistors on a SOC chip and is growing, and therefore plays a crucial role in a designer’s ability to differentiate their designs with the shortest design cycle,” said Farzad Zarrinfar, president and CEO at Novelics.

“Novelics is expanding its portfolio beyond existing 180nm-55nm offering with our coolSRAM-6T in leading 40nm process technologies with optimum active power consumption, leakage, speed, area, and block resolution. This will enable customers to differentiate themselves in markets such as wireless communication, video, portable multimedia, smart grid, storage, image processing, and connected home entertainment.”