Freescale, Nepes in licensing agreement to manufacture redistributed chip fan-out package technology

AUSTIN, USA: Freescale Semiconductor has signed a licensing agreement with Nepes Corporation, a leading Korean semiconductor parts and materials specialist, who will manufacture Freescale’s redistributed chip packaging (RCP) technology in a lower cost 300mm format.

Nepes installed the 300mm equipment set and manufacturing process capable of multiple layer single-die and multi-die system-in-package solutions at its facility in Singapore (Nepes Pte) earlier this year. The technology start-up at Nepes is in progress with a volume ramp forecast for the first quarter of 2011.

Freescale and Nepes are also collaborating in a joint development effort to further enhance the capabilities of the RCP technology. Development activities are expected to continue at both Freescale’s US RCP development facility in Tempe, Arizona and at Nepes’ facility in Singapore.

"Working with an outstanding company such as Nepes is a huge step toward introducing the RCP fan-out technology to the market,” said Ken Hansen, senior fellow, vice president and chief technology officer at Freescale. “Our joint development collaboration will also allow us to offer our customers compelling solutions for single die, 2D and 3D systems-in-package targeted at a broad range of industries and applications.”

“We are glad to work with Freescale, one of the leading companies in the semiconductor industry,” said Esdy Baek, senior vice president and chief of the global business center at Nepes.

“Through licensing and the ongoing joint development of RCP, Nepes Corporation will be able to provide leading edge packaging solutions to the market. With RCP technology support from both South Korea and Singapore, Nepes is in a strong position to support our customers and the market.”

Freescale, which developed and introduced the now widely deployed ball grid array (BGA) packaging technology, announced the RCP technology in 2006. RCP integrates semiconductor packaging as a functional part of the die and system solution.

It addresses some of the significant limitations associated with previous generations of packaging technologies by eliminating higher cost wire bonds, package substrates and flip chip bumps. In addition, RCP does not utilize blind vias or require thinned die to achieve thin profiles. These advancements simplify assembly, lower costs and provide compatibility with advanced wafer manufacturing processes utilizing low-k interlayer dielectrics.

The RCP fan-out package provides solutions for both highly sensitive analog devices and digital platforms. The technology is compatible with both small and larger package sizes. RCP accommodates single and multiple routing layers to optimize package size, performance, die size range of I/O and cost.