Mentor Graphics Veloce delivers 400X acceleration for OVM driven verification

WILSONVILLE, USA: Mentor Graphics Corp. announced that the Veloce emulation platform fully supports the Open Verification Methodology (OVM).

The primary advantage to companies using both the OVM and the Veloce platform is the ability to use a single transaction-based testbench for both simulation and emulation—two technologies that are critical to the functional verification of large, complex system-on-chip (SoCs) designs.

Mentor pioneered transaction-based acceleration in 2001 to maximize user throughput on hardware emulators. The fundamental structure of the then popular time-based testbenches limited emulation acceleration to a mere 10X over logic simulation. The TestBench XPress™ tool, the culmination of over 100 staff-years of development, speeds transaction-based testbenches up to 400X.

Testbench development consumes up to 80 percent of the SoC verification effort, making testbench reuse a mandatory practice. With the TestBench XPress tool, engineers can accelerate their OVM simulation testbenches on the Veloce emulator without modification and speed execution by two orders of magnitude, transforming a five hour video frame simulation into a 30 second run on the Veloce platform.

“The widespread adoption of OVM validates our direction over the past decade that an untimed, transaction-based testbench is the most effective path to functional verification,” said Eric Selosse, vice president and general manager of the Mentor Graphics Emulation Division. “With the entire EDA industry now promoting transaction-based methodology, the Veloce platform, combined with the TestBench Xpress tool, is uniquely positioned to accelerate the verification process.”

The Veloce and TestBench XPress tools consistently outperform other emulators on OVM-based customer evaluations, including those claiming higher raw emulation speed. The Veloce emulator high-performance implementation of the Accellera standard SCE-MI 2.0 (Standard Co-Emulation Model Interface) and extended synthesizable RTL subset accelerates more of the testbench in emulation hardware, including interface elements critical to high-bandwidth communication.

Testbenches adhering to OVM guidelines are accelerated on the Veloce platform without modification, delivering effortless testbench reuse between simulation and emulation.