Mentor Graphics Calibre InRoute delivers true manufacturing signoff during physical design closure

WILSONVILLE, USA: Mentor Graphics Corp. has announced the new Calibre InRoute design and verification platform, which now enables designers to natively invoke Calibre tools within the Olympus-SoC place and route system to achieve true manufacturing closure during physical design.

The Calibre InRoute product automatically detects and fixes DRC violations and performs design for manufacturing (DFM) enhancements while optimizing for area, timing, power and signal integrity. The full power of the Olympus-SoC and Calibre platforms together improve design quality, eliminate late-stage surprises, and significantly reduce time to closure.

“We have used Calibre InRoute on a production 55nm SOC. InRoute has successfully corrected the DRC violations caused by several complex IPs, whose ‘abstract’ views did not fully match the underlying layout, as well as several detailed routing DRC violations,” said Philippe Magarshack, STMicroelectronics Technology R&D Group Vice President and Central CAD and Design Solutions General Manager.

“Besides catching manufacturability issues early in the design flow, InRoute allows us to automatically find and repair violations without leaving the Olympus cockpit. This saves engineering time and ensures that no new violations will be created by the fixes. We will take advantage of these unique InRoute capabilities in upcoming 55nm, 40nm and 32nm ST designs.”

“Calibre InRoute with Olympus-SoC is a breakthrough product because it allows our customers to design to tighter margins, realizing higher performance and lower power, while eliminating design-driven manufacturing issues, all without extending time-to-market,” said Joseph Sawicki, Vice President and General Manager for the Design-to-Silicon division at Mentor Graphics. “Calibre InRoute has the potential to be a game changer for design teams already pressed by tight tapeout delivery dates.”

The manufacturing closure problem
Designers are experiencing growing manufacturing closure problems in advanced ICs, such as mismatches between SVRF-based design rules and inaccurate or outdated place and route models; timing and power degradation due to litho, fill and thickness variability; long runtimes due to multiple iterations and huge ASCII file transfers; and lengthy manual repair methodologies.

These issues lead to surprises late in the design cycle and delay time-to-market. Existing solutions that simply provide error annotation followed by manual repairs don’t really solve the problem because they are slow, require layout engineers to have deep manufacturing knowledge, and are non-convergent because manual fixes to one problem often create new violations.

The Calibre InRoute solution
The innovative Calibre InRoute Open Router architecture allows the Olympus-SoC system to natively invoke Calibre SVRF-based DRC and DFM analysis in the inner loop of the router.

The Calibre InRoute platform provides interactive, incremental analysis, on-demand GDSII model abstraction, and automated repair techniques targeted at specific DRC and DFM violations. The InRoute platform also performs MCMM-based analysis and optimization during yield improvement modifications to automatically minimize the impact on timing and power.

The InRoute architecture is also extremely scalable—besides the full breadth of DRC, LVS, LFD, CMP thickness variation, CAA and other DFM capabilities in the current Calibre platform, InRoute enables new Calibre rules and features to become immediately available inside the Olympus-SoC design environment as they are added. This ensures the increasing effectiveness of the InRoute platform as DRC and DFM rules get more numerous and complex.