Analog Devices releases new version of popular PLL synthesizer software for RF designs

NORWOOD, USA: Analog Devices Inc. (ADI) has announced the ADIsimPLL Version 3.3, a new generation of its successful phase-locked loop (PLL) circuit design and evaluation tool.

ADIsimPLL Version 3.3 assists users in evaluating, designing, and troubleshooting RF systems exploiting Analog Devices’ family of PLL synthesizers and is available from ADI’s web site free of charge.

Fully compatible with prior releases, ADIsimPLL Version 3.3 builds upon the success of previous versions of the software tool by adding support for 16 new devices, increased phase noise modeling accuracy and Fractional-N spur level estimation, along with enhancements to the tool’s New Design Wizard, Time Simulation Engine and Time Domain Simulator features. These innovative features further remove time-consuming iterations from the design process, ultimately speeding the design to market.

The new devices included in ADIsimPLL Version 3.3 are the recently announced ADF4150HV and ADF4158 synthesizers; ADF5000, ADF5001 and ADF5002 RF prescalers; highly integrated ADRF670x quadrature modulators with integrated Fractional-N PLL; ADRF660x mixers with integrated Fractional-N PLL and VCO; ADRF6750 quadrature modulator and ADRF6655 mixer.

To support these new highly integrated solutions, the ability to derive additional frequency outputs by dividing the VCO signal has been incorporated into the ADIsimPLL design tool. There have also been significant improvements and enhancements to the tool’s simulation and evaluation capabilities.

The phase noise simulation algorithms have been improved by the addition of the 1/f phase noise contribution from the digital dividers and the phase detector, resulting in highly accurate phase noise predictions from close to the carrier all the way to the broadband noise floor.

To assist in estimating the level of Fractional-N spurs, a new estimate of the worst case magnitude of the first three Fractional-N spurs is now calculated and displayed on the phase noise plots, which allows the user to evaluate different loop filter topologies and design parameters in order to manage the effect of these spurious signals.

Furthermore, a variety of enhancements to the design tool have been made including those to the Time Domain Simulator to model the various modulation options available; and to the New Design Wizard so that the user can select from the range of options to generate the desired frequency. In addition, an output page for the secondary output is provided allowing different configuration options to be selected when the phase noise is displayed, and the Time Simulation Engine has been enhanced to accurately model the effect of the anti-backlash pulse.