SAN JOSE, USA: Cadence Design Systems Inc. announced that it has increased the tool support in TSMC’s 65-nanometer Integrated Signoff Flow by introducing RTL Compiler, EDI System, QRC Extraction and Encounter Timing System for Signal Integrity into it.
By following fully validated, scripted and documented procedures within TSMC’s Integrated Signoff Flow, mutual customers can now establish an end-to-end RTL-to-GDSII flow with predictable, shorter time-to-volume for their 65-nanometer designs.
Global Unichip, a member of TSMC's Open Innovation Platform eco-system, partnered with TSMC and Cadence in the beta test of Integrated Signoff Flow. "Starting from 2008, we have successfully taped out over 20 65-nanometer projects annually using Cadence-based flow," said CC Hsieh, vice president of Design Service at Global Unichip.
"The collaboration with TSMC and Cadence in Integrated Signoff Flow is a great opportunity to further enhance our design flow efficiency and a critical step to bring more success to our customers."
“To be successful in implementing their low-power, high-performance SOC designs, our mutual customers need a proven best-in-class methodology that allows them to get their design ready for high volume production,” said ST Juang, senior director of design infrastructure marketing at TSMC.
“In line with this, we have worked closely with Cadence to expand EDA tool support in TSMC Integrated Signoff Flow by integrating their implementation and RC extraction capabilities into our flow.”
“Cadence and TSMC have been working closely to ensure that designers achieve their design goals as fast as possible when using our solutions,” said Dr. Chi-Ping Hsu, senior vice president of Implementation R&D.
“By qualifying EDI System and RTL Compiler, our customers can now get the best of both worlds: large-scale, high- performance physical synthesis and design closure capabilities in EDI System and RTL compiler, backed by the world-class manufacturing that results from using TSMC’s Integrated Signoff Flow.”