Avago first to demo 25Gbps SerDes performance in 40nm CMOS

SAN JOSE, USA & SINGAPORE: Avago Technologies, a leading supplier of analog interface components for communications, industrial, and consumer applications, has demonstrated serial 25Gbps SerDes performance in 40nm CMOS technology. This milestone is the latest achievement in Avago’s history of breakthrough ASIC IP performance.

Key differentiators of Avago’s SerDes cores are its unique decision feedback equalization (DFE), which results in lower overall power usage, as well as best-in-class data latency, noise immunity, jitter, and crosstalk performance. Further, due to Avago’s modular, multi-rate architecture, its SerDes cores are highly integratable, and channel counts in the hundreds are common.

Offering designers great flexibility, Avago’s broad SerDes portfolio is ideal for optical, copper, and backplane applications. Supported standards include PCI Express, Fibre Channel, XAUI, CEI-11G, 10GBASE-KR, and SFI.

“With the demonstration of 25Gbps performance, Avago’s legacy of IP leadership continues,” said Frank Ostojic, vice president and general manager of Avago’s ASIC Products Division. “Our early achievement of this milestone reflects Avago’s ongoing commitment to providing SerDes IP that enables our customers to address the demand for ever-increasing bandwidth.”

With over 95 million SerDes channels shipped, Avago has established a history of delivering reliable, high-performance ASICs. Three decades of design experience, state-of-the art hierarchical design methodology, and an IP portfolio covering multiple standards, form the foundation for success in supplying complex ASICs for networking, computing, and storage applications.