Shalom Bresticker receives Accellera’s 2010 Technical Excellence Award

NAPA, USA: Accellera, the electronics industry organization focused on EDA and Intellectual Property (IP) standards, announced that Shalom Bresticker, Senior CAD Engineer, Intel, is the 2010 recipient of its 7th annual Technical Excellence Award.

The Award recognizes Bresticker’s volunteer contributions to Accellera’s SystemVerilog, Open Verification Library (OVL) and Verilog Analog/Mixed Signal (AMS) standards.

Accellera’s chair, Shrenik Mehta, presented Accellera’s Technical Excellence Award at 3pm on Wednesday, February 24, 2010, during the organization’s Design and Verification Conference and Exhibition (DVCon) at the Doubletree hotel in San Jose, California before the Panel, What Keeps You Up at Night?

“Shalom Bresticker’s achievements are important for the industry because they provide clarity and improve the quality of existing and future Verilog-related design and verification language standards,” said Shrenik Mehta, Accellera’s chair. “Because of Shalom’s expertise, contributions and understanding of the language and its place in the electronic design and verification ecosystem, we have better quality standards.”

Mehta continued: “Shalom has a long standing devotion to the development of a quality specification for the Verilog and SystemVerilog languages. He has scrutinized the standards at every step in the process for completeness and accuracy. Tool developers and users of the language for design and verification have better standards because of his constant attention, and devotion to producing quality standards. He is someone whom many should look to emulate.”

"It is an honor to be recognized by Accellera for my work on the Verilog standard and its related language standards,” added Shalom Bresticker.