Xilinx picks 28nm high–performance, low-power process to accelerate platforms for driving the programmable imperative

INDIA: Xilinx Inc. announced the foundation for a next-generation of Xilinx programmable platforms that will give system designers FPGAs that consume half the power at twice the capacity than previously possible for addressing the Programmable Imperative.

Xilinx is maximizing the value of the 28nm technology node by choosing a high-performance, low-power process technology, a common scalable architecture across product ranges, and tool innovations so customers will have FPGAs that deliver the ASIC-class capabilities they need to meet their cost and power budgets, while improving their productivity through easy design migration and IP reuse.

Today, numerous trends – the exorbitant cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials, and the need for both hardware and software programmability, all in the face of rough economic times and reduced staffing – are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs. Xilinx calls the convergence of these trends the Programmable Imperative.

At the same time, power management and the impact it has on system costs and performance is a paramount concern to today’s electrical system designers and manufacturers. The need to reduce power consumption and manage thermal dissipation, while also keeping ahead on price and performance-driven capabilities, is essential as competitive pressure increases.

“At the 28nm node, static power is a very significant portion of the total power dissipation of a device and in some cases is the dominate factor.  To achieve maximal power efficiency, the choice of process technology is paramount because the key to enabling greater useable system performance and capabilities is controlling power consumption,” said Victor Peng, Senior Vice President, Programmable Platforms Development as Xilinx.

“We chose the high-k metal gate high-performance, low-power process at TSMC and Samsung for next-generation FPGAs to significantly minimize static power consumption so we wouldn’t lose the performance and functional advantages we get at 28nm.”

Compared to the standard high-performance process, the high-performance, low-power process delivers FPGAs that are 50 percent lower in static power. The lower static power enables Xilinx to provide customers with the lowest-power FPGAs in their class, and contributes to a 50 percent reduction in total power compared to previous generation devices.

Meanwhile, next-generation development tools reduce dynamic power as much as 20 percent through innovative clock management. Enhancements made to Xilinx’s industry-leading partial reconfiguration technology will enable designers to further drive down power consumption and lower system costs by 33 percent.

To address system performance bottlenecks caused at the interconnect level, Xilinx will provide the industry’s highest performance interfaces to support customers who need high-bandwidth chip-to-chip, board-to-board, and box-to-box connections. This is of critical importance as customers increasingly look to FPGAs to become a major, if not central, component of their systems, and helps define how the next generation of FPGAs will enable customers to build their systems when ASIC and ASSP options are unavailable.

Preserving IP and design investment
Tool enhancements deliver productivity gains in alignment with a unified ASMBL architecture that reduces the need to modify a design to accommodate moving between the range of high-performance and low-cost devices, and ease design migration as Spartan-6 and Virtex-6 FPGA customers transition to the development of their next generation products over time.

Unifying the architecture enables Xilinx to fulfill its vision for ‘socketable IP’ that will allow customers to preserve their IP investments and more easily offer product portfolios that address a broad range of end market requirements. Socketable IP and unification also enables a larger, more responsive ecosystem through reduced IP development cost, all in support of the Xilinx strategy of accelerating innovation and reducing development costs through Targeted Design Platforms.

Xilinx’s collaboration efforts with ARM on the next generation AMBA AXI specification with extensions for FPGA implementation, announced in October 2009, will further drive IP development and re-use by providing software and hardware designers with a proven, broadly adopted standard for interconnecting IP blocks and building embedded systems.

Accelerating platforms to address the programmable imperative
As ASICs and ASSPs become viable for only the highest volume applications, Xilinx’s keen focus on delivering significantly lower-levels of total power consumption is essential for unlocking the full, usable, potential FPGAs can provide systems in support of a variety of applications.

Portable medical equipment, for example, call for low price, small form factor, and low static power to enable battery-powered operation, while reduced thermal dissipation enables higher performance in high-performance computing, electronic warfare and radar systems for the aerospace and defense markets.

The new silicon devices and development tools will form the Base Platform for the next generation of Targeted Design Platforms from Xilinx and 3rd parties, and will include ‘Ultra-High End FPGAs’ that can only be made possible by Xilinx’s process, architectural and tool innovations.

Ultra-high-end FPGAs integrate high serial I/O bandwidth, logic density greater than twice that of what is currently in a high-end FPGA, and high-bandwidth interfaces to next generation memory technology. This enables telecommunications system developers to replace a single large ASIC or an ASSP chip set for applications such as:

High-end Tera-bit switch fabric in telecom systems: Ultra-high-end class FPGAs will enable single-chip implementations of 1Tbps full-duplex switches by integrating the world’s highest serial I/O bandwidth, logic density 2x what’s available in today’s FPGAs, and high-bandwidth interfaces to next generation memory technology replacing a single large ASIC or an ASSP chip set.

400G OTN (optical transport network) line cards: A single ultra-high-end class FPGA can implement the required bandwidth to support multiple 40G or 100G single chip implementations to replace multiple ASSPs on a line card

Built on high-K metal gate, high-performance, low-power 28nm processes at TSMC and Samsung Electronics’ Foundry, initial devices will be available in Q4 of calendar year 2010 with initial tools support available in the ISE Design Suite in June.