Silicon Frontline improves performance and capacity of flagship EDA products

LOS GATOS, USA: Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company in the post-layout verification market, announced that new versions of its flagship post-layout verification products, F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices, are shipping now.

F3D improves its performance by up to 10x when compared to the previous version. F3D and R3D also accommodate larger designs than the previous versions announced in May 2009.

According to Dermott Lynch, VP Marketing at Silicon Frontline, “To address our customers’ post-layout verification needs as their technology options change, we are focused on improving our software products’ performance and our products’ capacity to handle full-chip designs.”

F3D is chosen for providing nanometer and Analog Mixed Signal (A/MS) design accuracy and R3D for its ability to improve the reliability and efficiency of semiconductor power devices.

F3D and R3D incorporate patent-pending 3D technology to deliver a Guaranteed Accurate solution for full-chip, post-layout verification. They work in industry standard flows allowing simpler adoption and quicker closure, with guaranteed accuracy, of the post-layout verification loop.

What’s new: Capacity and performance
The latest version of Silicon Frontline’s 3D Field Solver technology accomplishes full-chip extraction with Field Solver accuracy and improves its performance and capacity. Typical examples of F3D running with Guaranteed Accuracy are a 65nm SOC run in under two hours (in the previous version this took 10 hours); MOMCaps run in under 1 minute (in the previous version this took 3 minutes and can take over 7 hours with most commercial Field Solvers).

A tiling feature allows design size for F3D and R3D to be unlimited. Designs can be automatically partitioned into blocks of up to 4-million transistors and each block can be run using one CPU or multiple CPUs can run a number of design blocks in parallel. In the previous version the block size was limited to a maximum of 1-million transistors.

These results are not possible with commercial tools available today.

The newest version of F3D and R3D are available now.