IEEE completes revised IEEE 1800 standard to make semiconductor chip design and verification more efficient

PISCATAWAY, USA: IEEE, the world's leading professional association for the advancement of technology, announced completion of IEEE 1800-2009, a revision to an existing IEEE standard.

The new IEEE 1800 defines a single, comprehensive standard language that is designed to help boost the productivity of electronic system design and verification engineers and make possible broader and improved Electronic Design Automation (EDA) tools to more quickly bring complex system-on-chip (SOC) devices to market.

“IEEE 1800 has been so successful because of the sustained attention of such a broad representation of the EDA, semiconductor and system-design communities throughout the standard’s lifecycle,” said Karen Pieper, chair of the IEEE P1800 SystemVerilog Working Group. “We encourage all stakeholders to continue to engage and build consensus through the IEEE to advance the ongoing innovations that our industry will require.”

An open meeting of the IEEE P1800 SystemVerilog Working Group will take place Feb. 26 in San Jose, Calif., in conjunction with DVCon 2010. Input gathered at this meeting will be used to establish the scope of the next revision of the IEEE 1800 standard. For more information on attending or participating remotely, please visit http://www.eda.org/sv-ieee1800/.

Continued increases in logic functionality, verification complexity and power issues resulting in a larger number of lines of Register Transfer Level (RTL) code characterize contemporary SOC designs. These trends also make multi-discipline verification significantly more complex.

In addition to expanding the original IEEE 1800 SystemVerilog standard to meet these challenges and address the language’s increased usage, the newly revised standard ensures backward compatibility with the legacy IEEE 1364-2005 Verilog standard to improve ease of use.

IEEE 1800 is a comprehensive standard that mergers into it the underlying IEEE 1364 Verilog language. IEEE 1800 also includes errata fixes and resolutions, general enhancements, and significant improvements and extensions to the SystemVerilog Assertion (SVA) language.

“IEEE 1800 has become the dominant global design and verification language standard to allow higher-capacity chips to be produced with greater efficiency,” said Dennis Brophy, chair of the IEEE-SA Corporate Advisory Group. “Broad corporate participation in the development of the standard under the corporate program has ensured IEEE 1800 addresses the pressing design and verification challenges of industry.”