UMC and Synopsys to develop DesignWare IP for 28nm technology

HSINCHU, TAIWAN & MOUNTAIN VIEW, USA: United Microelectronics Corp. (UMC), a leading global semiconductor foundry, and Synopsys Inc., announced an expanded collaboration to develop DesignWare IP for UMC's 28-nanometer (nm) HLP Poly SiON process.

Extending its previous successes in UMC's 40-nm and 55-nm processes, Synopsys plans to implement its proven DesignWare Embedded Memories and Logic Libraries in UMC's 28HLP Poly SiON process technology. This collaboration will enable designers to create high-speed, low-power system-on-chips (SoCs) with less risk and improved time-to-market. The longstanding relationship between the two companies extends the availability of high-quality DesignWare IP for a wide range of UMC processes from 180-nm to 28-nm.

While preserving the cost-competitiveness of conventional Poly SiON gate stack and using proprietary process techniques, UMC's 28HLP process technology delivers exceptional performance-to-cost ratio with vastly improved performance and power consumption over other 28-nm Poly SiON industry offerings. This enhanced 28-nm Poly-SiON process provides a natural migration path from 40-nm, enabling easy design adoption and fast time-to-market.

"UMC and Synopsys' close collaboration has spanned many years and technology generations," said S. C. Chien, UMC vice president of Customer Engineering & IP Development Design Support Divisions. "Extending our relationship with Synopsys, a leading and trusted IP provider, into the 28-nm process shows our mutual commitment to helping customers develop their increasingly complex SoC designs. We look forward to bringing these next-generation products to market with our customers."

Synopsys' broad portfolios of embedded memories and standard cell libraries are optimized for speed, power and area, and have been silicon proven in more than one billion chips. The DesignWare Embedded Memories and Logic Libraries include advanced power management features such as light-sleep, deep-sleep and shut-down, as well as a Power Optimization Kit to help extend battery life in mobile applications. In addition, Synopsys' integrated STAR Memory System test and repair solution enables designers to achieve higher test quality and yield for their embedded memories while lowering overall chip area.

"Synopsys' collaboration with UMC, a leading foundry provider, will help our mutual customers differentiate their SoC designs with IP that is proven in UMC's robust 28-nm process technology," said John Koeter, vice president of marketing for IP & systems at Synopsys. "Our extensive track record of delivering high-quality IP in advanced nodes gives designers confidence that they can integrate DesignWare IP into their SoCs with less risk and achieve a predictable path to first-pass silicon success."

The DesignWare Embedded Memories and Logic Libraries supporting UMC's 28HLP process are scheduled to be available in Q2 2012. The 28HLP DesignWare Embedded Memories and Logic Libraries will be available at no cost to qualified licensees as part of Synopsys' Foundry Sponsored IP program.

UMC's 28-nm Poly SiON technology is currently in pilot production and available for customer design-in now.