ARM VSTREAM accelerates functional SoC validation on RTL simulators

CAMBRIDGE, UK: ARM has extended the functionality of the VSTREAM Virtual Debug Interface to enable the connection of the ARM Development Studio 5 (DS-5) and RVD debuggers to ARM Cortex processors running in RTL simulation.

Together, VSTREAM and DS-5 enable earlier and more efficient functional validation and software development for ARM processor-based SoCs on either RTL simulation or hardware-assisted validation platforms.

In the very early stages of the design cycle, VSTREAM may be used to:
* Verify the correct implementation of the debug and trace fabric of the SoC, including any CoreSight components, by running high-level test patterns and connecting an actual debugger.
* Easily validate the connection of the processor to the memory system and memory-mapped peripherals, by opening memory views in the debugger.
* Create and debug boot code and functional test software to prove the integration of SoC components. From the debugger it is possible to stop the processor, view and change the value of processor registers and system memory, and single-step through code.
* Post-process PTM or ETM instruction trace after a simulation run in order to get a history of instructions executed by the processor in a non-intrusive way.

DS-5, together with VSTREAM and the ARM DSTREAM™ target connection unit, provide a common software development environment throughout the complete design cycle: from models and RTL simulators, through hardware emulators and FPGAs, to ASICs and ASSPs.

All current ARM Cortex processors are supported by VSTREAM. Furthermore, it enables the simultaneous connection of multiple debuggers to a target, an essential function in bringing up multicore devices, such as those based on the Cortex-A5, Cortex- and Cortex-A15 MPCore processors.

VSTREAM is available now for usage with Cadence Incisive, Synopsys VCS and Mentor ModelSim and Questa simulators. The hardware emulators supported are Cadence Palladium, Eve Zebu and Mentor Veloce.