MOUNTAIN VIEW, USA: Nimbic (formerly Physware) announced the open beta launch of nCloud, the world’s first scalable and secure cloud computing platform for electronic design automation (EDA). Effective immediately, nWave, the leading 3D full-wave EM solver for signal and power integrity (formerly PhysWAVE), and nApex, the leading 3D accelerated parasitic extractor (formerly PhysAPEX), are available on nCloud.
“With our pay-for-use, peak-usage cloud computing model, customers can now expect to see results hundreds of times faster than what they have been used to, without having to over-spend on upfront volume licenses that typically sit idle for extended periods during the year,” said Dr. Raul Camposano, CEO of Nimbic. “nCloud has all the ingredients to ignite a new phase in electronic design, where solutions to even the most complex system designs can be delivered cost-effectively in near real time.”
nCloud offers multiple advantages:
* On-demand provisioning of computing resources in minutes, with virtually unlimited scalability;
* A highly secure compute platform;
* Resources to exploit parallelism at the tool and at the design-methodology level;
* An easy-to-use design environment with pre-installed and ready-to-run design tools;
* Reduced need for on-premises hardware IT infrastructure;
* Reduced need for upfront purchase of EDA licenses;
* A cost-effective pay-for-use and pay-as-you-go software-as-a-service (SaaS) model.
“The cost-effective way of scaling performance with nCloud is very appealing to us,” said Tomoaki Isozaki, chief professional, system package engineering department, Renesas Electronics. “As a customer of Nimbic, we have continually been impressed with the accuracy, speed and capacity of their enterprise solution. We look forward to even greater efficiencies with the solutions on the cloud. We are excited to be working with Nimbic as an early nCloud adopter.”
“As an innovator in the programmable logic market looking to deploy our Stylus 3PLD design tools on the cloud, and as a satisfied enterprise customer of nWave and nApex, we share in the excitement of Nimbic’s launch of the solutions in the cloud,” said Prasun Raha, senior director, analog and system engineering, at Tabula Inc. “Better productivity with less upfront EDA tool investment and the ability to scale on demand and pay for use when we are in peak design mode is particularly attractive to us. We are excited to be a beta participant in nCloud.”
For many customers, security in the cloud remains a real concern. To address this issue, Nimbic built its architecture with security across multiple layers, including security of data in transit, security of data at rest and security through the use of isolation techniques.
Tuesday, May 31, 2011
ATREG acts as exclusive financial advisor to Renesas in recent closed sale of 200mm US manufacturing fab to TELEFUNKEN
SEATTLE, USA: ATREG Inc. (Advanced Technology Resource Group), a Seattle-based global advisory firm to the semiconductor industry, announced that it acted as exclusive financial advisor to Renesas Electronics America Inc. in the recently announced sale of its 200mm semiconductor fab to TELEFUNKEN Semiconductors International LLC for an estimated $53 million.
Wafra Capital Partners L.P. and Somerset Capital Group Ltd. helped TELEFUNKEN finance the transaction. TELEFUNKEN will use the Roseville, Calif. facility to manufacture its own analog / mixed-signal high-voltage products as well as products for strategic foundry partners. The buyer has also entered into a supply agreement with Renesas Electronics for manufacturing services at the Roseville factory, and kept the site’s entire workforce.
Renesas Electronics had been considering and implementing various measures to improve manufacturing efficiency by promoting larger wafers, finer process node, and production concentration. In line with these measures, the company decided to sell its Roseville, Calif. facility to TELEFUNKEN Semiconductors International, which had been searching for a new manufacturing facility to expand its semiconductor business.
“We were on an aggressive timeline for completing this transaction by the end of our fiscal year,” explains Yutaka Emoto, executive manager, corporate structure planning department, corporate planning division at Renesas Electronics Corporation based in Tokyo, Japan. “ATREG provided us with the expert financial advice, the key industry relationships, and the market knowledge we needed in order to move quickly and achieve a successful sale.”
“We are very pleased to see an international company making a significant investment in manufacturing in America,” comments Barnett Silver, senior vice president and principal at ATREG. “We are currently witnessing increasing investment in what are perceived as higher-cost regions where semiconductor companies can rely on higher available capacity, more affordable assets, strong IP protection, a highly trained workforce, and wage stability. The Renesas transaction is a perfect example of that unfolding trend.”
Wafra Capital Partners L.P. and Somerset Capital Group Ltd. helped TELEFUNKEN finance the transaction. TELEFUNKEN will use the Roseville, Calif. facility to manufacture its own analog / mixed-signal high-voltage products as well as products for strategic foundry partners. The buyer has also entered into a supply agreement with Renesas Electronics for manufacturing services at the Roseville factory, and kept the site’s entire workforce.
Renesas Electronics had been considering and implementing various measures to improve manufacturing efficiency by promoting larger wafers, finer process node, and production concentration. In line with these measures, the company decided to sell its Roseville, Calif. facility to TELEFUNKEN Semiconductors International, which had been searching for a new manufacturing facility to expand its semiconductor business.
“We were on an aggressive timeline for completing this transaction by the end of our fiscal year,” explains Yutaka Emoto, executive manager, corporate structure planning department, corporate planning division at Renesas Electronics Corporation based in Tokyo, Japan. “ATREG provided us with the expert financial advice, the key industry relationships, and the market knowledge we needed in order to move quickly and achieve a successful sale.”
“We are very pleased to see an international company making a significant investment in manufacturing in America,” comments Barnett Silver, senior vice president and principal at ATREG. “We are currently witnessing increasing investment in what are perceived as higher-cost regions where semiconductor companies can rely on higher available capacity, more affordable assets, strong IP protection, a highly trained workforce, and wage stability. The Renesas transaction is a perfect example of that unfolding trend.”
Micron and Intellectual Ventures sign IP license agreement
BOISE & BELLEVUE, USA: Micron Technology Inc. and Intellectual Ventures (IV) have entered into an intellectual property license agreement.
The agreement provides Micron with access to IV's patent portfolio of more than 30,000 IP assets. In addition, the companies have the option to buy patents from each other. Micron can acquire patents from IV to help defend against companies that may assert patents against them, and IV has the opportunity to acquire patents from Micron to expand and supplement its growing portfolio of IP assets.
"Building on Micron's extensive patent portfolio, this transaction provides Micron strategic access to IV's substantial patent portfolio to help drive future innovation and continued expansion of our award-winning products and leading-edge technologies in addition to opportunities to advance our intellectual property strategies," said Rod Lewis, Micron's vice president of legal affairs and general counsel.
"Micron is an innovative industry-leading company and has pioneered various thoughtful and strategic intellectual property transactions," said Joe Chernesky, vice president and general manager, global licensing sales at Intellectual Ventures. "Our collaborative agreement with Micron further validates the strength of our patent portfolio and the value we bring to technology companies through efficient access to intellectual property."
Intellectual Ventures engages with companies of all sizes to meet their current business needs and provide strategic guidance on forward-thinking intellectual property. IV combines scale and expertise to structure sophisticated deals designed to help companies strengthen their market position by reducing their current risk and providing access to the invention rights they need to stay competitive. Collaborating with Intellectual Ventures helps Micron protect its core business so it can focus on innovation.
The agreement provides Micron with access to IV's patent portfolio of more than 30,000 IP assets. In addition, the companies have the option to buy patents from each other. Micron can acquire patents from IV to help defend against companies that may assert patents against them, and IV has the opportunity to acquire patents from Micron to expand and supplement its growing portfolio of IP assets.
"Building on Micron's extensive patent portfolio, this transaction provides Micron strategic access to IV's substantial patent portfolio to help drive future innovation and continued expansion of our award-winning products and leading-edge technologies in addition to opportunities to advance our intellectual property strategies," said Rod Lewis, Micron's vice president of legal affairs and general counsel.
"Micron is an innovative industry-leading company and has pioneered various thoughtful and strategic intellectual property transactions," said Joe Chernesky, vice president and general manager, global licensing sales at Intellectual Ventures. "Our collaborative agreement with Micron further validates the strength of our patent portfolio and the value we bring to technology companies through efficient access to intellectual property."
Intellectual Ventures engages with companies of all sizes to meet their current business needs and provide strategic guidance on forward-thinking intellectual property. IV combines scale and expertise to structure sophisticated deals designed to help companies strengthen their market position by reducing their current risk and providing access to the invention rights they need to stay competitive. Collaborating with Intellectual Ventures helps Micron protect its core business so it can focus on innovation.
License and settlement agreement with Elpida relating to Qimonda's patent portfolio
MUNICH, GERMANY: Dr. Michael Jaffé, the insolvency administrator over the estate of Qimonda AG, reached a settlement and license agreement with the Japanese memory chip manufacturer Elpida Memory Inc., Tokyo.
Insolvency proceedings over the estate of Qimonda AG were opened on April 1, 2009 at the Munich District Court and Dr. Michael Jaffé was appointed insolvency administrator. Qimonda AG markets one of the largest semiconductor IP portfolios in the world including some 4,500 patent families.
The settlement and license agreement allows Elpida to use Qimonda's patents world wide. Elpida will withdraw from litigation pending in the US between Qimonda's administrator and several semiconductor and information-technology manufacturers.
This settlement is the first resolution of claims brought by licensees of Qimonda AG's patent portfolio. After a US Bankruptcy Court recognized Qimonda AG's German insolvency proceedings as a foreign main proceeding under Chapter 15 of the US Bankruptcy Code, a group of licensees, including Elpida, Samsung Electronics Co. Ltd., Intel Corp., Infineon Technologies AG, Micron Technology Inc., Hynix Semiconductor Inc., IBM Corp. and Nanya Technology Corp., asserted that the US Bankruptcy Court should order that licenses shall continue with respect to Qimonda's US patents under US law, despite the insolvency administrator's election of non-performance under German law. That proceeding - from which Elpida will now withdraw as an objector - is still pending.
The terms and conditions of the license and the settlement amount are confidential.
Insolvency proceedings over the estate of Qimonda AG were opened on April 1, 2009 at the Munich District Court and Dr. Michael Jaffé was appointed insolvency administrator. Qimonda AG markets one of the largest semiconductor IP portfolios in the world including some 4,500 patent families.
The settlement and license agreement allows Elpida to use Qimonda's patents world wide. Elpida will withdraw from litigation pending in the US between Qimonda's administrator and several semiconductor and information-technology manufacturers.
This settlement is the first resolution of claims brought by licensees of Qimonda AG's patent portfolio. After a US Bankruptcy Court recognized Qimonda AG's German insolvency proceedings as a foreign main proceeding under Chapter 15 of the US Bankruptcy Code, a group of licensees, including Elpida, Samsung Electronics Co. Ltd., Intel Corp., Infineon Technologies AG, Micron Technology Inc., Hynix Semiconductor Inc., IBM Corp. and Nanya Technology Corp., asserted that the US Bankruptcy Court should order that licenses shall continue with respect to Qimonda's US patents under US law, despite the insolvency administrator's election of non-performance under German law. That proceeding - from which Elpida will now withdraw as an objector - is still pending.
The terms and conditions of the license and the settlement amount are confidential.
Microsemi completes acquisition of AML Communications
IRVINE, USA: Microsemi Corp. announced that its acquisition of AML Communications Inc. closed on Friday, May 27, 2011.
"We are pleased to move forward with AML's contribution to the Microsemi family," stated James J. Peterson, Microsemi president and CEO. "RF components are increasingly important in today's defense programs and Unmanned Aerial Vehicle (UAV) systems and this acquisition brings scale and complementary technology to Microsemi's fast-growing RF component and subsystems product offering. As we execute on the integration of AML, we expect to deliver ever more advanced RF solutions to our customers, increase our sellable available market, and drive shareholder returns."
The financial contribution from AML for Microsemi's fiscal third quarter is uncertain at this time but will be immaterial to results. As a reminder, in its fiscal second quarter earnings conference call, the company forecast sequential revenue growth on the order of 3-5 percent, excluding the effect of any pending acquisition.
"We are pleased to move forward with AML's contribution to the Microsemi family," stated James J. Peterson, Microsemi president and CEO. "RF components are increasingly important in today's defense programs and Unmanned Aerial Vehicle (UAV) systems and this acquisition brings scale and complementary technology to Microsemi's fast-growing RF component and subsystems product offering. As we execute on the integration of AML, we expect to deliver ever more advanced RF solutions to our customers, increase our sellable available market, and drive shareholder returns."
The financial contribution from AML for Microsemi's fiscal third quarter is uncertain at this time but will be immaterial to results. As a reminder, in its fiscal second quarter earnings conference call, the company forecast sequential revenue growth on the order of 3-5 percent, excluding the effect of any pending acquisition.
Atrenta announces new book on RTL design
SAN JOSE, USA: Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced the availability of a comprehensive text book on RTL design.
The text book “Principles of VLSI RTL Design, A Practical Guide”, authored by Sanjay Churiwala and Sapan Garg is being published by Springer Science+Business Media. The book is based on the author’s experiences, while working at Atrenta’s Noida, India R&D center.
“Through our years of work at Atrenta, we had seen a lot of designs and design methodologies. We developed a good understanding of what best practices looked like,” said Sanjay Churiwala. “It was gratifying to be able to put all those ideas down on paper so others can benefit from our experiences.”
The book targets RTL designers and provides rich information on design practices and how they affect downstream implementation tasks. Topics discussed in the text include: reliable RTL construction, clock domain crossings and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling and routing congestion.
“The decisions made by RTL designers can have a profound impact on the schedule and ultimate quality of the chip,” said Sapan Garg. “Through the use of many examples, we highlight how the RTL designer can heavily influence the outcome of any design project.”
The text book “Principles of VLSI RTL Design, A Practical Guide”, authored by Sanjay Churiwala and Sapan Garg is being published by Springer Science+Business Media. The book is based on the author’s experiences, while working at Atrenta’s Noida, India R&D center.
“Through our years of work at Atrenta, we had seen a lot of designs and design methodologies. We developed a good understanding of what best practices looked like,” said Sanjay Churiwala. “It was gratifying to be able to put all those ideas down on paper so others can benefit from our experiences.”
The book targets RTL designers and provides rich information on design practices and how they affect downstream implementation tasks. Topics discussed in the text include: reliable RTL construction, clock domain crossings and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling and routing congestion.
“The decisions made by RTL designers can have a profound impact on the schedule and ultimate quality of the chip,” said Sapan Garg. “Through the use of many examples, we highlight how the RTL designer can heavily influence the outcome of any design project.”
MIPS and SiS to drive Android into digital home
SUNNYVALE, USA & HSINCHU, TAIWAN: MIPS Technologies Inc. and Taiwan's Silicon Integrated Systems Corp. (SiS) announced their latest milestones in driving the Android platform into the digital home. The companies collaborated to deliver an optimized Android solution on SiS' new MIPS-Based integrated Internet TV platform, which is available now. SiS has also licensed the new superscalar multiprocessing MIPS32 1074Kf Coherent Processing System (CPS) for next generation designs.
"Android is fundamentally changing the embedded world, enabling the industry to move beyond fragmented, proprietary operating systems that use a number of different kernels, to a single framework for application development. SiS and MIPS share a vision of how the power of Android will transform the consumer entertainment experience in the digital home. We are excited to work with SiS and other members of the Android on MIPS ecosystem to help make this vision a reality," said Art Swift, vice president of marketing and business development, MIPS Technologies.
"We have collaborated closely with MIPS to deliver an ideal user experience through Android in our MIPS-Based internet TV solutions. With our highly competitive products, we are helping to expand the internet TV market segment beyond the high-end into the mainstream. With our next-generation chip based on the 1074K CPS, targeting 1GHz frequency, our goal is to enable more consumers to enjoy cloud entertainment in the digital era," said Michael Chen, president of SiS.
The new highly-integrated internet TV platform from SiS leverages dual core high-performance MIPS processors, and offers customized widgets and support for popular services including YouTube, Facebook, eBay, Flickr, weather and finance, as well as online film rental. It supports high-end graphics and enhanced video processing as well as Adobe Flash Player 10.1 for Flash and video streaming on TV. It also supports video on demand recording and Skype for internet communications. It is designed for seamless interoperability with other Android devices such as tablets and smartphones, which can be used for remote control and video sharing. The new internet TV platform is available now through SiS.
With its license of the MIPS32 1074K CPS, SiS will be able to leverage a new level of performance for its next-generation designs. The 1074K CPS was designed to bring multicore performance to the next generation of internet-connected multimedia products such as digital televisions, Blu-ray players and set-top boxes (STBs), as well as home/wireless networking products and tablet computers leveraging the popular Android operating system.
"Android is fundamentally changing the embedded world, enabling the industry to move beyond fragmented, proprietary operating systems that use a number of different kernels, to a single framework for application development. SiS and MIPS share a vision of how the power of Android will transform the consumer entertainment experience in the digital home. We are excited to work with SiS and other members of the Android on MIPS ecosystem to help make this vision a reality," said Art Swift, vice president of marketing and business development, MIPS Technologies.
"We have collaborated closely with MIPS to deliver an ideal user experience through Android in our MIPS-Based internet TV solutions. With our highly competitive products, we are helping to expand the internet TV market segment beyond the high-end into the mainstream. With our next-generation chip based on the 1074K CPS, targeting 1GHz frequency, our goal is to enable more consumers to enjoy cloud entertainment in the digital era," said Michael Chen, president of SiS.
The new highly-integrated internet TV platform from SiS leverages dual core high-performance MIPS processors, and offers customized widgets and support for popular services including YouTube, Facebook, eBay, Flickr, weather and finance, as well as online film rental. It supports high-end graphics and enhanced video processing as well as Adobe Flash Player 10.1 for Flash and video streaming on TV. It also supports video on demand recording and Skype for internet communications. It is designed for seamless interoperability with other Android devices such as tablets and smartphones, which can be used for remote control and video sharing. The new internet TV platform is available now through SiS.
With its license of the MIPS32 1074K CPS, SiS will be able to leverage a new level of performance for its next-generation designs. The 1074K CPS was designed to bring multicore performance to the next generation of internet-connected multimedia products such as digital televisions, Blu-ray players and set-top boxes (STBs), as well as home/wireless networking products and tablet computers leveraging the popular Android operating system.
IAR embedded workbench selected by ON Semiconductor for its Q32M210 precision mixed-signal MCU development kit
FOSTER CITY & PHOENIX, USA: IAR Systems and ON Semiconductor announced that IAR Systems integrated development environment has been chosen as the tool chain for ON Semiconductor’s new Q32M210 precision mixed-signal microcontroller for portable sensing applications. The KickStart edition of IAR Embedded Workbench for ARM was selected for its ability to provide an effective integrated development environment for building and debugging Q32M210 applications.
In addition to IAR Embedded Workbench, the ON Semiconductor development kit includes a hardware board and easy-to-use software with firmware libraries and sample code. The Q32M210 is the first in a new family of highly integrated devices that provide a unique combination of precision mixed-signal performance with exceptional power efficiency for precision measurement and monitoring applications.
“We are very pleased to be selected by ON Semiconductor as a technology partner for its latest technology,” said Nadim Shehayed, Americas General Manager for IAR Systems. “ON Semiconductor’s precision mixed-signal MCU is an excellent fit for a wide range of embedded designs and we’re able to provide high quality tools combined with second to none service and technical support.”
“The Q32M210 microcontroller represents a significant step forward in precision mixed-signal microcontrollers,” said Michel DeMey, senior director for ON Semiconductor’s conversion and control technologies product line. “In order for the device to achieve its true potential in terms of addressing applications, it is important to provide first-class development support. IAR Systems KickStart edition of IAR Embedded Workbench for ARM is a crucial part of the overall hardware and software support we offer our customers to help simplify and speed the development of their new designs.”
In addition to IAR Embedded Workbench, the ON Semiconductor development kit includes a hardware board and easy-to-use software with firmware libraries and sample code. The Q32M210 is the first in a new family of highly integrated devices that provide a unique combination of precision mixed-signal performance with exceptional power efficiency for precision measurement and monitoring applications.
“We are very pleased to be selected by ON Semiconductor as a technology partner for its latest technology,” said Nadim Shehayed, Americas General Manager for IAR Systems. “ON Semiconductor’s precision mixed-signal MCU is an excellent fit for a wide range of embedded designs and we’re able to provide high quality tools combined with second to none service and technical support.”
“The Q32M210 microcontroller represents a significant step forward in precision mixed-signal microcontrollers,” said Michel DeMey, senior director for ON Semiconductor’s conversion and control technologies product line. “In order for the device to achieve its true potential in terms of addressing applications, it is important to provide first-class development support. IAR Systems KickStart edition of IAR Embedded Workbench for ARM is a crucial part of the overall hardware and software support we offer our customers to help simplify and speed the development of their new designs.”
MIPS advances 'Apps on MIPS' development
SUNNYVALE, USA: MIPS Technologies Inc. announced the launch of a new MIPS Application Development (MAD) Program designed to promote rapid development of applications on the MIPS architecture.
The program offers technical support and services for performance testing and compatibility to verify that applications will run as designed on MIPS-Based devices. Through the program—the latest offering available through the new MIPS Developer Community—developers can quickly create applications that are fully compatible with MIPS-Based mobile devices to ensure an ideal user experience with their games and other applications.
The initial MAD Program is targeted for development of applications for MIPS-Based devices running the Android platform. A dedicated team of MIPS development engineers will provide compatibility and performance analysis, which will be fed back to the application developer. Full documentation and technical support are available through the MIPS Developer Community at developer.mips.com. In addition, developers can take advantage of a MAD Kit for Android application development. The MAD Kit offers a full toolchain comprised of the Android software development kit (SDK) and QEMU emulator, and includes a native development kit (NDK) (r5b Windows/Linux). A premium mobile hardware platform will also be available.
"An increasing number of MIPS licensees are developing smart connected products with Android, including several MIPS-Based Android tablets that are already in the market. Today, consumers already have access to thousands of apps on MIPS. We want to encourage developers to build more apps, and support these developers in testing the performance and compatibility of those apps. We anticipate that developers will optimize their apps across each of the major processor architectures to ensure an optimal user experience on all consumer devices," said Art Swift, vice president of marketing and business development, MIPS Technologies.
The program offers technical support and services for performance testing and compatibility to verify that applications will run as designed on MIPS-Based devices. Through the program—the latest offering available through the new MIPS Developer Community—developers can quickly create applications that are fully compatible with MIPS-Based mobile devices to ensure an ideal user experience with their games and other applications.
The initial MAD Program is targeted for development of applications for MIPS-Based devices running the Android platform. A dedicated team of MIPS development engineers will provide compatibility and performance analysis, which will be fed back to the application developer. Full documentation and technical support are available through the MIPS Developer Community at developer.mips.com. In addition, developers can take advantage of a MAD Kit for Android application development. The MAD Kit offers a full toolchain comprised of the Android software development kit (SDK) and QEMU emulator, and includes a native development kit (NDK) (r5b Windows/Linux). A premium mobile hardware platform will also be available.
"An increasing number of MIPS licensees are developing smart connected products with Android, including several MIPS-Based Android tablets that are already in the market. Today, consumers already have access to thousands of apps on MIPS. We want to encourage developers to build more apps, and support these developers in testing the performance and compatibility of those apps. We anticipate that developers will optimize their apps across each of the major processor architectures to ensure an optimal user experience on all consumer devices," said Art Swift, vice president of marketing and business development, MIPS Technologies.
Duolog and ARM provide accelerated IP integration
DAC 2011, DUBLIN, IRELAND: Duolog Technologies, the award-winning developer of IP and SoC integration products has combined its industry-proven integration platform, Socrates, with ARM’s CoreLink AMBA Designer to accelerate IP integration. Duolog and ARM will be co-presenting this solution during DAC 2011 in San Diego, from June 6th-8th.
“Duolog’s Socrates complements ARM’s system IP and CoreLink AMBA Designer particularly well,” commented Andy Nightingale, Product Marketing Manager, Processor Division, ARM. “We are delighted to be able to demonstrate the results of this exciting combination at DAC. I believe that our customers will reap the benefits of this partnership as we continue to collaborate with Duolog and deliver joint solutions.”
ARM provides a wide range of high-performance configurable system IP; including, memory controllers, interface IP and interconnect fabric that are used to by system architects and designers to develop energy-efficient SoCs for advanced digital devices ranging from smartphones and tablets to set-top boxes and DTVs. Socrates ensures fast and consistent IP integration and system assembly which leads to fewer bugs and reduced verification times, resulting in faster time-to-integration. Socrates and AMBA Designer work together by using IP-XACT to enable a fully interoperable flow.
“We’re delighted to bring this great collaboration to the industry,” says Mike Smith, Product Manager, Duolog Technologies. “With Socrates we can instantiate configured ARM IP and provide input to AMBA Designer for interconnect creation, which is then automatically integrated into the system. Socrates immediately generates fully coherent processor views of the entire system as well as the complete connectivity netlist. The integration process is reduced from months to minutes.”
“Duolog’s Socrates complements ARM’s system IP and CoreLink AMBA Designer particularly well,” commented Andy Nightingale, Product Marketing Manager, Processor Division, ARM. “We are delighted to be able to demonstrate the results of this exciting combination at DAC. I believe that our customers will reap the benefits of this partnership as we continue to collaborate with Duolog and deliver joint solutions.”
ARM provides a wide range of high-performance configurable system IP; including, memory controllers, interface IP and interconnect fabric that are used to by system architects and designers to develop energy-efficient SoCs for advanced digital devices ranging from smartphones and tablets to set-top boxes and DTVs. Socrates ensures fast and consistent IP integration and system assembly which leads to fewer bugs and reduced verification times, resulting in faster time-to-integration. Socrates and AMBA Designer work together by using IP-XACT to enable a fully interoperable flow.
“We’re delighted to bring this great collaboration to the industry,” says Mike Smith, Product Manager, Duolog Technologies. “With Socrates we can instantiate configured ARM IP and provide input to AMBA Designer for interconnect creation, which is then automatically integrated into the system. Socrates immediately generates fully coherent processor views of the entire system as well as the complete connectivity netlist. The integration process is reduced from months to minutes.”
MIPS and Ingenic to bring Android 'Honeycomb' to new 1GHz MIPS-Based mobile SoC
SUNNYVALE, USA: MIPS Technologies Inc. and Ingenic Semiconductor, a leading China-based CPU provider for mobile multimedia applications, are collaborating to bring Android 3.0, also known as 'Honeycomb', to Ingenic's new JZ4770 mobile applications processor, which leverages a MIPS-Based XBurst CPU running at 1GHz. Honeycomb is the newest version of the Android operating system designed specifically for tablets and other large format products. MIPS and Ingenic will work together on porting Honeycomb to the Ingenic chip for tablets.
The new JZ4770 SoC is one of the first MIPS-Based systems-on-chips (SoCs) targeted for mobile devices that delivers 1GHz frequency, increasingly a requirement for tablets and other devices that incorporate rich multimedia and numerous high-performance applications and functionality.
The JZ4770 is the latest in a series of low-power platforms from Ingenic to leverage the MIPS32 architecture for mobile products. Previously released platforms are used in products such as the Cruz tablets from Velocity Micro, and will also be used in the first smartphone from TCL Corporation, a global leader and technology innovator in consumer electronics, mobile communications and home appliances.
Ingenic's JZ4770 SoC integrates a 1GHz CPU, 1080P VPU, OpenGL ES 2.0 3D GPU and numerous on-chip analog and application blocks such as audio CODEC and GPS. The MIPS32 compatible XBurst CPU core provides an alternative and ultra low-power application processor solution. At 1GHz, the JZ4770 SoC consumes ~250mW power.
The new chip from Ingenic will be available in the third quarter of 2011.
The new JZ4770 SoC is one of the first MIPS-Based systems-on-chips (SoCs) targeted for mobile devices that delivers 1GHz frequency, increasingly a requirement for tablets and other devices that incorporate rich multimedia and numerous high-performance applications and functionality.
The JZ4770 is the latest in a series of low-power platforms from Ingenic to leverage the MIPS32 architecture for mobile products. Previously released platforms are used in products such as the Cruz tablets from Velocity Micro, and will also be used in the first smartphone from TCL Corporation, a global leader and technology innovator in consumer electronics, mobile communications and home appliances.
Ingenic's JZ4770 SoC integrates a 1GHz CPU, 1080P VPU, OpenGL ES 2.0 3D GPU and numerous on-chip analog and application blocks such as audio CODEC and GPS. The MIPS32 compatible XBurst CPU core provides an alternative and ultra low-power application processor solution. At 1GHz, the JZ4770 SoC consumes ~250mW power.
The new chip from Ingenic will be available in the third quarter of 2011.
Industry leaders unite to form the Embedded Vision Alliance
OAKLAND, USA: More than 15 leading technology companies— including some of the largest semiconductor companies—have joined forces to speed the adoption of computer vision capabilities in electronic products.
The ability of machines to see and understand their environments—what we call "embedded vision"—promises to transform the electronics industry with products that are more intelligent and aware of their environments, and to create significant new markets for electronic equipment and components. A new consortium, called the Embedded Vision Alliance, will enable the proliferation of embedded vision technology by providing design engineers with information, practical know-how, and industry standards.
"Adding computer vision to embedded systems creates phenomenal new products, markets, and opportunities," according to Jeff Bier, president of BDTI. "Just look at the Microsoft Kinect, which added vision to the Xbox 360—it became the fastest-selling consumer electronics device in history, shipping more than 10 million units in 5 months. But that's just a small part of the story. From automobiles that prevent accidents to security cameras that prevent crimes, embedded vision will proliferate across a multitude of markets."
BDTI, Xilinx, and IMS Research initiated the Embedded Vision Alliance (EVA) and are being joined by Analog Devices, Apical, Avnet Electronics Marketing, CEVA, CogniVue, Freescale, National Instruments, NVIDIA, Texas Instruments, Tokyo Electron Device, MathWorks, Ximea, and XMOS as founding members. These companies share the belief that incorporating vision capabilities into future products will bring dramatic benefits to users and provide high-growth opportunities in consumer, medical, automotive, entertainment, industrial, and retail markets.
"The momentum behind embedded vision applications is growing at an astounding rate and industry collaboration is needed to enable the technology's smooth adoption in new markets," said Vin Ratford, senior vice president of worldwide marketing and business development at Xilinx. "Xilinx is excited to be a founding member of the new Embedded Vision Alliance and looks forward to a long, successful partnership with the Alliance members. Through this collaboration—and by delivering the right combination of performance, price points and flexibility to intelligently manage and act upon vast amounts of real-time image data within the parameters of industry standards—our programmable platforms are poised to open up a new world for systems development."
As a first step, the Embedded Vision Alliance is launching a website at www.embedded-vision.com. The site will serve as a source of practical information that will help design engineers incorporate vision capabilities in new systems. The EVA's future plans include newsletters, educational webinars, industry reports, technology standards, and other related activities. Everyone is free to access the information on the website, which is maintained through member and industry contributions. Membership information is also available at the site.
Ian Weightman, president of market research firm IMS Research, said: "IMS Research is proud to be one of the founding members of the Embedded Vision Alliance. The EVA shares our vision of a future where embedded computer vision positively impacts many aspects of our daily lives. With hundreds of companies now developing embedded vision components, products and applications, the EVA can become the pivotal hub that not only educates companies on the potential of embedded vision, but also enables the industry to share ideas and best practices. This will be essential for the technology to reach its true potential, and we look forward to supporting the Embedded Vision Alliance in its objectives."
The ability of machines to see and understand their environments—what we call "embedded vision"—promises to transform the electronics industry with products that are more intelligent and aware of their environments, and to create significant new markets for electronic equipment and components. A new consortium, called the Embedded Vision Alliance, will enable the proliferation of embedded vision technology by providing design engineers with information, practical know-how, and industry standards.
"Adding computer vision to embedded systems creates phenomenal new products, markets, and opportunities," according to Jeff Bier, president of BDTI. "Just look at the Microsoft Kinect, which added vision to the Xbox 360—it became the fastest-selling consumer electronics device in history, shipping more than 10 million units in 5 months. But that's just a small part of the story. From automobiles that prevent accidents to security cameras that prevent crimes, embedded vision will proliferate across a multitude of markets."
BDTI, Xilinx, and IMS Research initiated the Embedded Vision Alliance (EVA) and are being joined by Analog Devices, Apical, Avnet Electronics Marketing, CEVA, CogniVue, Freescale, National Instruments, NVIDIA, Texas Instruments, Tokyo Electron Device, MathWorks, Ximea, and XMOS as founding members. These companies share the belief that incorporating vision capabilities into future products will bring dramatic benefits to users and provide high-growth opportunities in consumer, medical, automotive, entertainment, industrial, and retail markets.
"The momentum behind embedded vision applications is growing at an astounding rate and industry collaboration is needed to enable the technology's smooth adoption in new markets," said Vin Ratford, senior vice president of worldwide marketing and business development at Xilinx. "Xilinx is excited to be a founding member of the new Embedded Vision Alliance and looks forward to a long, successful partnership with the Alliance members. Through this collaboration—and by delivering the right combination of performance, price points and flexibility to intelligently manage and act upon vast amounts of real-time image data within the parameters of industry standards—our programmable platforms are poised to open up a new world for systems development."
As a first step, the Embedded Vision Alliance is launching a website at www.embedded-vision.com. The site will serve as a source of practical information that will help design engineers incorporate vision capabilities in new systems. The EVA's future plans include newsletters, educational webinars, industry reports, technology standards, and other related activities. Everyone is free to access the information on the website, which is maintained through member and industry contributions. Membership information is also available at the site.
Ian Weightman, president of market research firm IMS Research, said: "IMS Research is proud to be one of the founding members of the Embedded Vision Alliance. The EVA shares our vision of a future where embedded computer vision positively impacts many aspects of our daily lives. With hundreds of companies now developing embedded vision components, products and applications, the EVA can become the pivotal hub that not only educates companies on the potential of embedded vision, but also enables the industry to share ideas and best practices. This will be essential for the technology to reach its true potential, and we look forward to supporting the Embedded Vision Alliance in its objectives."
New Texas Memory Systems patent enhances reliability and improves MTBF with RamSan-70
HOUSTON, USA: Texas Memory Systems Inc. (TMS) sets a new standard for Flash reliability with the introduction of its patented Variable Stripe RAID (VSR) error mitigation technology on the RamSan-70 PCIe Flash card. Failure of a plane (small subsection of a Flash chip) is the second most common kind of Flash failure after Flash block failures.
TMS VSR technology (U.S. Patent #7,856,528) addresses plane and chip failures by dynamically bypassing failed Flash, reducing maintenance requirements and extending operating lifecycles. VSR technology is available exclusively from TMS, the leader in enterprise solid state reliability.
Variable Stripe RAID (VSR) forms a core portion of the TMS SSD reliability technology suite developed through extensive Flash device testing in labs and the field. TMS lab facilities include a burn-in room used to stress test systems for one month prior to shipment. The intense testing process has provided a treasure trove of real-world reliability data for several generations of Flash media. Flash media naturally degrades after hundreds of thousands of write cycles.
TMS has seen three basic categories of Flash media failures: block failures, disabling a tiny part of a chip; plane failures, affecting a small part of a chip; and complete chip failures. Block failures are typically handled by error correcting code (ECC). VSR is an improved management approach for plane and chip failures.
Most enterprise SSDs use a simple type of error mitigation called RAID which groups Flash media into “stripes” containing equal numbers of chips. RAID technology can reconstruct data from a failed Flash chip. Typically, when a chip or part of a chip fails, the RAID algorithm uses a spare chip as a virtual replacement for the broken chip. But once the SSD is out of spare chips, it needs to be replaced. VSR technology allows the number of chips to vary among stripes, so bad chips can simply be bypassed using a smaller stripe size.
Additionally, VSR provides greater stripe size granularity, so a stripe could exclude a small part of a chip rather than having to exclude an entire chip if only part of it failed. With VSR technology, TMS Series-7 products like the RamSan-70 require less maintenance than average SSD designs.
According to Dan Scheel, president of Texas Memory Systems, “Variable Stripe RAID technology is another TMS innovation that maximizes return on SSD investments and minimizes maintenance downtime.”
To further understand the benefits of VSR, consider a hypothetical SSD made up of 25 individual Flash chips. If a plane failure occurs that disables an eighth of one chip, a traditional RAID system would remove a full 4 percent of the raw Flash capacity. TMS VSR technology bypasses the failure and only reduces the raw Flash capacity by 0.5 percent, an 8x improvement. TMS tests show that plane failures are the second most common kind of Flash device failures, so it is very important to be able to handle them without wasting working Flash.
TMS VSR technology (U.S. Patent #7,856,528) addresses plane and chip failures by dynamically bypassing failed Flash, reducing maintenance requirements and extending operating lifecycles. VSR technology is available exclusively from TMS, the leader in enterprise solid state reliability.
Variable Stripe RAID (VSR) forms a core portion of the TMS SSD reliability technology suite developed through extensive Flash device testing in labs and the field. TMS lab facilities include a burn-in room used to stress test systems for one month prior to shipment. The intense testing process has provided a treasure trove of real-world reliability data for several generations of Flash media. Flash media naturally degrades after hundreds of thousands of write cycles.
TMS has seen three basic categories of Flash media failures: block failures, disabling a tiny part of a chip; plane failures, affecting a small part of a chip; and complete chip failures. Block failures are typically handled by error correcting code (ECC). VSR is an improved management approach for plane and chip failures.
Most enterprise SSDs use a simple type of error mitigation called RAID which groups Flash media into “stripes” containing equal numbers of chips. RAID technology can reconstruct data from a failed Flash chip. Typically, when a chip or part of a chip fails, the RAID algorithm uses a spare chip as a virtual replacement for the broken chip. But once the SSD is out of spare chips, it needs to be replaced. VSR technology allows the number of chips to vary among stripes, so bad chips can simply be bypassed using a smaller stripe size.
Additionally, VSR provides greater stripe size granularity, so a stripe could exclude a small part of a chip rather than having to exclude an entire chip if only part of it failed. With VSR technology, TMS Series-7 products like the RamSan-70 require less maintenance than average SSD designs.
According to Dan Scheel, president of Texas Memory Systems, “Variable Stripe RAID technology is another TMS innovation that maximizes return on SSD investments and minimizes maintenance downtime.”
To further understand the benefits of VSR, consider a hypothetical SSD made up of 25 individual Flash chips. If a plane failure occurs that disables an eighth of one chip, a traditional RAID system would remove a full 4 percent of the raw Flash capacity. TMS VSR technology bypasses the failure and only reduces the raw Flash capacity by 0.5 percent, an 8x improvement. TMS tests show that plane failures are the second most common kind of Flash device failures, so it is very important to be able to handle them without wasting working Flash.
MIPS and Actions Semiconductor to bring Android 'Honeycomb' to new 1.3GHz chipset for tablets
SUNNYVALE, USA & ZHUHAI, CHINA: MIPS Technologies Inc. and Actions Semiconductor Co. Ltd, one of China's leading fabless semiconductor companies that provides solutions for portable consumer electronics, are collaborating to bring Android 3.0, also known as "Honeycomb," to a new 1.3GHz MIPS-Based chipset from Actions.
Honeycomb is the newest version of the Android operating system designed specifically for tablets and other large format products. After recently announcing that it is porting Honeycomb to the MIPS architecture, MIPS is now porting Honeycomb to MIPS-Based tablets, with support from Actions.
The new high-performance system-on-chip (SoC) from Actions leverages a superscalar MIPS32 74Kf core (with floating point unit) running at 1.3GHz. In addition to Android, the new chip incorporates an OpenGL ES 2.0 3D graphics processing unit, USB 2.0 OTG, HDMI 1.3, support for multi-format high definition 1080p video encoding and decoding, and other advanced functionality. Actions and MIPS will also work together to enable the platform with Adobe Flash Player 10.2 optimized for the MIPS architecture.
"With its new 1.3GHz chip specifically designed for tablets, Actions is a flag bearer for the MIPS architecture in the mobile market," said Art Swift, vice president of marketing and business development, MIPS Technologies. "This is one of the first times a MIPS licensee has achieved such high frequency with a MIPS-Based SoC targeted for mobile applications. As MIPS continues to make inroads into the mobile market, we are working closely with innovative licensees such as Actions to enable them to deliver fully optimized MIPS-Based solutions for their specific target applications."
"With the MIPS architecture, we are able to achieve extremely high performance with power efficiency that differentiates our solutions in the market. For more than 10 years, Actions has experienced success in the market with SoCs for portable consumer electronics. Our MIPS-Based chips are already shipping in portable media player products including our Series 23, 25, 27, game family G1000, tablet family ATM70, and a feature phone. Now we are pleased to collaborate with MIPS to deliver a chip specifically designed for tablets. Into this SoC we have integrated the most advanced technologies that will provide an ideal user experience," said Robert Wang, vice president of marketing, Actions Semiconductor.
Honeycomb is the newest version of the Android operating system designed specifically for tablets and other large format products. After recently announcing that it is porting Honeycomb to the MIPS architecture, MIPS is now porting Honeycomb to MIPS-Based tablets, with support from Actions.
The new high-performance system-on-chip (SoC) from Actions leverages a superscalar MIPS32 74Kf core (with floating point unit) running at 1.3GHz. In addition to Android, the new chip incorporates an OpenGL ES 2.0 3D graphics processing unit, USB 2.0 OTG, HDMI 1.3, support for multi-format high definition 1080p video encoding and decoding, and other advanced functionality. Actions and MIPS will also work together to enable the platform with Adobe Flash Player 10.2 optimized for the MIPS architecture.
"With its new 1.3GHz chip specifically designed for tablets, Actions is a flag bearer for the MIPS architecture in the mobile market," said Art Swift, vice president of marketing and business development, MIPS Technologies. "This is one of the first times a MIPS licensee has achieved such high frequency with a MIPS-Based SoC targeted for mobile applications. As MIPS continues to make inroads into the mobile market, we are working closely with innovative licensees such as Actions to enable them to deliver fully optimized MIPS-Based solutions for their specific target applications."
"With the MIPS architecture, we are able to achieve extremely high performance with power efficiency that differentiates our solutions in the market. For more than 10 years, Actions has experienced success in the market with SoCs for portable consumer electronics. Our MIPS-Based chips are already shipping in portable media player products including our Series 23, 25, 27, game family G1000, tablet family ATM70, and a feature phone. Now we are pleased to collaborate with MIPS to deliver a chip specifically designed for tablets. Into this SoC we have integrated the most advanced technologies that will provide an ideal user experience," said Robert Wang, vice president of marketing, Actions Semiconductor.
Magma's Titan and FineSim validated for TSMC's analog/mixed-signal Reference Flow 2.0 for 28-nm processes
SAN JOSE, USA: Magma Design Automation announced TSMC has validated the Titan Mixed-Signal Design Platform and FineSim SPICE and FineSim Pro circuit simulation products for inclusion in TSMC's Analog/Mixed-Signal (AMS) Reference Flow 2.0.
The TSMC AMS Reference Flow 2.0 targets its most advanced 28-nanometer (nm) process technology and includes a comprehensive design kit and new advanced custom design methodologies. Magma's Titan Mixed-Signal Design Platform and FineSim circuit simulator have been applied to support the enhanced flow. With Magma’s advanced technology and the TSMC AMS Reference Flow 2.0 flow, mutual customers can accelerate the design and manufacture of next-generation analog/mixed-signal IC designs.
Titan and FineSim provide a robust, integrated analog design and simulation platform that complies with the requirements of the TSMC AMS Reference Flow 2.0. Titan provides a Layout-Dependent-Effects (LDE)-aware flow that allows users to account for these effects during schematic design, and performs custom wire load emulation allowing users to include parasitic effects early in the circuit design and simulation flow. Titan also provides a parasitic wrapper that enables schematic engineering change order (ECO) emulation with parasitic and LDE parameters, allowing users to make schematic changes and factor in LPE and RC effects.
FineSim SPICE and FineSim Pro work with Titan to enable SPICE-level simulation and post-layout simulation with extracted parasitics. FineSim SPICE is a SPICE-level simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed-signal and analog designs. FineSim Pro is the industry's first fast SPICE circuit simulator that supports multi-CPU simulations.
“Customers always seek better ways to achieve superior results in advanced technologies,” said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. “By working with TSMC and providing advanced capabilities, faster throughput, higher levels of automation and allowing analog design reuse, Magma enables customers to develop highly differentiated products more cost effectively.”
"TSMC’s 28-nm process technology enables customers to improve timing, area and power on their designs, and achieving silicon success requires a complete design ecosystem that includes leading-edge analog and circuit simulation tools,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. "By collaborating with Magma to include Titan and FineSim for the AMS Reference Flow 2.0, we can provide our customers with a robust design ecosystem.”
Titan and FineSim are currently in production release. Customers may access the AMS Reference Flow 2.0 at the TSMC Online customer design portal.
The TSMC AMS Reference Flow 2.0 targets its most advanced 28-nanometer (nm) process technology and includes a comprehensive design kit and new advanced custom design methodologies. Magma's Titan Mixed-Signal Design Platform and FineSim circuit simulator have been applied to support the enhanced flow. With Magma’s advanced technology and the TSMC AMS Reference Flow 2.0 flow, mutual customers can accelerate the design and manufacture of next-generation analog/mixed-signal IC designs.
Titan and FineSim provide a robust, integrated analog design and simulation platform that complies with the requirements of the TSMC AMS Reference Flow 2.0. Titan provides a Layout-Dependent-Effects (LDE)-aware flow that allows users to account for these effects during schematic design, and performs custom wire load emulation allowing users to include parasitic effects early in the circuit design and simulation flow. Titan also provides a parasitic wrapper that enables schematic engineering change order (ECO) emulation with parasitic and LDE parameters, allowing users to make schematic changes and factor in LPE and RC effects.
FineSim SPICE and FineSim Pro work with Titan to enable SPICE-level simulation and post-layout simulation with extracted parasitics. FineSim SPICE is a SPICE-level simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed-signal and analog designs. FineSim Pro is the industry's first fast SPICE circuit simulator that supports multi-CPU simulations.
“Customers always seek better ways to achieve superior results in advanced technologies,” said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. “By working with TSMC and providing advanced capabilities, faster throughput, higher levels of automation and allowing analog design reuse, Magma enables customers to develop highly differentiated products more cost effectively.”
"TSMC’s 28-nm process technology enables customers to improve timing, area and power on their designs, and achieving silicon success requires a complete design ecosystem that includes leading-edge analog and circuit simulation tools,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. "By collaborating with Magma to include Titan and FineSim for the AMS Reference Flow 2.0, we can provide our customers with a robust design ecosystem.”
Titan and FineSim are currently in production release. Customers may access the AMS Reference Flow 2.0 at the TSMC Online customer design portal.
Magma's Talus IC implementation system supports TSMC 28-nm process technology through Reference Flow 12.0
SAN JOSE, USA: Magma Design Automation Inc. announced that Magma's Talus, Hydra, Tekton, QCP and Quartz DRC integrated circuit (IC) implementation and verification solutions have been qualified to support the TSMC Reference Flow 12.0. Through TSMC's Open Innovation Platform (OIP), Magma's product suite provides users with advanced features to address the challenges of 28-nanometer (nm) design.
"Magma and TSMC have already worked closely to support the design and manufacture of a number of 28-nm ICs for the industry’s highest volume fabless companies,” said Premal Buch, general manager of Magma's Design Implementation Business Unit. "With Talus, Hydra, Tekton, QCP and Quartz DRC, and Reference Flow 12.0, mutual customers can have a high level of confidence in their ability to successfully deliver differentiated ICs using Magma and TSMC solutions."
"Close collaboration with leading EDA vendors such as Magma is critical to delivering the 28-nm design ecosystem,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. “Our mutual customers’ silicon successes highlight the effectiveness of TSMC’s process technology and Talus, Hydra, Tekton and Quartz for ICs at 28 nm.”
28-nm design enablement
Magma's Talus RTL-to-GDSII IC Implementation system supports TSMC 28-nm design rules that have been enhanced in Reference Flow 12.0. Talus' support of Reference Flow 12.0 takes advantage of new power and performance features, providing customers with faster overall design closure and better performance and predictability. In addition, Magma's Quartz DRC and Quartz LVS physical verification tools support in-the-loop physical verification.
Improved performance
At 28 nm and below it becomes increasingly complicated to capture the number of potential variations at all process corners. With Reference Flow 12.0, greater performance is achieved using multiple advanced stage-based on-chip variation (OCV) optimization and analysis tables instead of a single OCV value. This analysis technique is available in Tekton, Magma's standalone static timing analysis tool, and is also supported by Talus Vortex through its MX timing engine. This technique can reduce traditional OCV pessimism and improve performance by removing some of the punitive pessimism associated with traditional OCV modeling.
Reference Flow 12.0 additionally provides significant user margin control through add-on OCV that allows further modeling of voltage and temperature variation and cell-based constraint uncertainty, both of which are supported fully by Talus Vortex and Tekton.
To ensure optimal dummy fill after GDSII stream-out, Reference Flow 12.0 provides for timing criticality information to be passed through to latter stages of the flow, a technique also fully supported by Talus Vortex.
New low-power features
TSMC supports both the Common Power Format (CPF) and Unified Power Format (UPF) in Reference Flow 12.0. Talus Power Pro, Magma's advanced low-power optimization technology, also supports both the CPF 1.1 and UPF 2.0 power intent standards. This provides customers with complete flexibility in defining power intent. Talus Power Pro's industry-leading multiple voltage domain (MVdd) infrastructure delivers the most comprehensive power support combined with the simplest use model.
In particular, its dynamic voltage and frequency scaling (DVFS) low-power technologies, bolstered by an industry-leading multi-mode, multi-corner framework, enables customers to deliver the maximum performance per watt. These capabilities, combined with Magma's Hydra hierarchical design planner, allow customers to design very large, low-power systems on a chip without sacrificing performance.
To support Reference Flow 12.0, Talus Vortex also delivers optimized cell placement to minimize power hotspots and delivers native electromigration-safe clock placement and network topologies throughout the flow. Talus Vortex with Talus Power Pro now supports post-route multi-mode, multi-corner-aware leakage power optimization through Magma’s Tekton timing analysis tool.
Magma support for TSMC Reference Flow 12.0
Reference Flow 12.0 is supported by Magma's full RTL-to-GDSII suite of tools, which includes:
• Talus Design – physically aware RTL synthesis
• Talus Vortex – advanced timing and DFM-aware physical implementation
• Talus Power Pro – low-power optimization
• Hydra – hierarchical design planning
• Talus qDRC – timing-aware metal fill
• Quartz DRC – design rule checking
• Tekton – static timing analysis
• QCP – sign-off-quality extraction.
"Magma and TSMC have already worked closely to support the design and manufacture of a number of 28-nm ICs for the industry’s highest volume fabless companies,” said Premal Buch, general manager of Magma's Design Implementation Business Unit. "With Talus, Hydra, Tekton, QCP and Quartz DRC, and Reference Flow 12.0, mutual customers can have a high level of confidence in their ability to successfully deliver differentiated ICs using Magma and TSMC solutions."
"Close collaboration with leading EDA vendors such as Magma is critical to delivering the 28-nm design ecosystem,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. “Our mutual customers’ silicon successes highlight the effectiveness of TSMC’s process technology and Talus, Hydra, Tekton and Quartz for ICs at 28 nm.”
28-nm design enablement
Magma's Talus RTL-to-GDSII IC Implementation system supports TSMC 28-nm design rules that have been enhanced in Reference Flow 12.0. Talus' support of Reference Flow 12.0 takes advantage of new power and performance features, providing customers with faster overall design closure and better performance and predictability. In addition, Magma's Quartz DRC and Quartz LVS physical verification tools support in-the-loop physical verification.
Improved performance
At 28 nm and below it becomes increasingly complicated to capture the number of potential variations at all process corners. With Reference Flow 12.0, greater performance is achieved using multiple advanced stage-based on-chip variation (OCV) optimization and analysis tables instead of a single OCV value. This analysis technique is available in Tekton, Magma's standalone static timing analysis tool, and is also supported by Talus Vortex through its MX timing engine. This technique can reduce traditional OCV pessimism and improve performance by removing some of the punitive pessimism associated with traditional OCV modeling.
Reference Flow 12.0 additionally provides significant user margin control through add-on OCV that allows further modeling of voltage and temperature variation and cell-based constraint uncertainty, both of which are supported fully by Talus Vortex and Tekton.
To ensure optimal dummy fill after GDSII stream-out, Reference Flow 12.0 provides for timing criticality information to be passed through to latter stages of the flow, a technique also fully supported by Talus Vortex.
New low-power features
TSMC supports both the Common Power Format (CPF) and Unified Power Format (UPF) in Reference Flow 12.0. Talus Power Pro, Magma's advanced low-power optimization technology, also supports both the CPF 1.1 and UPF 2.0 power intent standards. This provides customers with complete flexibility in defining power intent. Talus Power Pro's industry-leading multiple voltage domain (MVdd) infrastructure delivers the most comprehensive power support combined with the simplest use model.
In particular, its dynamic voltage and frequency scaling (DVFS) low-power technologies, bolstered by an industry-leading multi-mode, multi-corner framework, enables customers to deliver the maximum performance per watt. These capabilities, combined with Magma's Hydra hierarchical design planner, allow customers to design very large, low-power systems on a chip without sacrificing performance.
To support Reference Flow 12.0, Talus Vortex also delivers optimized cell placement to minimize power hotspots and delivers native electromigration-safe clock placement and network topologies throughout the flow. Talus Vortex with Talus Power Pro now supports post-route multi-mode, multi-corner-aware leakage power optimization through Magma’s Tekton timing analysis tool.
Magma support for TSMC Reference Flow 12.0
Reference Flow 12.0 is supported by Magma's full RTL-to-GDSII suite of tools, which includes:
• Talus Design – physically aware RTL synthesis
• Talus Vortex – advanced timing and DFM-aware physical implementation
• Talus Power Pro – low-power optimization
• Hydra – hierarchical design planning
• Talus qDRC – timing-aware metal fill
• Quartz DRC – design rule checking
• Tekton – static timing analysis
• QCP – sign-off-quality extraction.
Helic's EDA tools contribute to successful development of SHARP's RF-IC
SAN FRANCISCO, USA & OSAKA, JAPAN: Helic Inc., the technology leader in EDA solutions for RF and high-speed IC design and SHARP Corp., proudly announced that SHARP selected Helic's VeloceRF, VeloceRaptor/X and VeloceWired to be part of its RFIC design flow.
To meet the demands of RF and high-speed design in advanced silicon processes, VeloceRF features a unique component-synthesis engine that generates DRC and DFM-correct inductive devices according to designer specifications. VeloceRF brings a complete solution for achieving an optimal floor plan, enabling silicon area reduction by optimizing inductor sizes. The tool de-risks the design from electromagnetic effects, incorporating EM coupling parasitics in post-layout simulation.
VeloceRaptor/X is a breakthrough RLCK modeling tool with unparalleled capacity and speed suitable for integrated passives such as transmission lines, interconnects, digital high-speed lines, spiral inductive devices and MIM/MOM capacitors. VeloceWired completes the flow with the design and extraction of 3D structures like bondwires providing instantly the impact of package parasitics on RFIC performance.
Dr. Kunihiko Iizuka, Design Manager at Electronic Components and Devices Group at SHARP, commented on how Helic's EDA products were instrumental for the successful development of a silicon Low Noise Block-down converter (LNB) designed in a challenging CMOS process. "VeloceRF and VeloceRaptor/X(TM) helped us to optimize our floor plan and design with high speed and accuracy, while with VeloceWired(R) we managed to design an optimum input-matching network for our LNA block. The results lead to successful mass production of a silicon LNB with the first parts shipping to customers in April 2011."
"SHARP leverages their leadership in RF devices to foray the satellite market and we are very proud to contribute with our tools in this endeavor setting higher standards to address their design needs", said Yorgos Koutsoyannopoulos, CEO of Helic.
To meet the demands of RF and high-speed design in advanced silicon processes, VeloceRF features a unique component-synthesis engine that generates DRC and DFM-correct inductive devices according to designer specifications. VeloceRF brings a complete solution for achieving an optimal floor plan, enabling silicon area reduction by optimizing inductor sizes. The tool de-risks the design from electromagnetic effects, incorporating EM coupling parasitics in post-layout simulation.
VeloceRaptor/X is a breakthrough RLCK modeling tool with unparalleled capacity and speed suitable for integrated passives such as transmission lines, interconnects, digital high-speed lines, spiral inductive devices and MIM/MOM capacitors. VeloceWired completes the flow with the design and extraction of 3D structures like bondwires providing instantly the impact of package parasitics on RFIC performance.
Dr. Kunihiko Iizuka, Design Manager at Electronic Components and Devices Group at SHARP, commented on how Helic's EDA products were instrumental for the successful development of a silicon Low Noise Block-down converter (LNB) designed in a challenging CMOS process. "VeloceRF and VeloceRaptor/X(TM) helped us to optimize our floor plan and design with high speed and accuracy, while with VeloceWired(R) we managed to design an optimum input-matching network for our LNA block. The results lead to successful mass production of a silicon LNB with the first parts shipping to customers in April 2011."
"SHARP leverages their leadership in RF devices to foray the satellite market and we are very proud to contribute with our tools in this endeavor setting higher standards to address their design needs", said Yorgos Koutsoyannopoulos, CEO of Helic.
NetLogic announces production orders into LTE base stations for ground-breaking XLP multi-core processors
SANTA CLARA, USA: NetLogic Microsystems Inc. has received, and is now accepting orders for volume production for its best-in-class XLP316L multi-core, multi-threaded processors from customers developing next-generation LTE base stations. NetLogic Microsystems’ industry-leading XLP316L multi-core processor delivers unparalleled performance and sets a new standard for Tier One OEMs developing highly differentiated eNodeB solutions for LTE and LTE-Advanced.
The XLP316L multi-core processor integrates 16 high-performance NXCPUs and an innovative quad-issue, quad-threaded processor architecture with superscalar out-of-order execution capabilities to deliver the industry’s highest performance Layers 2-7 processing for mobile wireless infrastructure. In addition, the XLP316L processor offers a number of base station-specific features that make it ideally suited to LTE applications, such as an advanced floating point unit (FPU), Kasumi and SNOW3G security protocol acceleration and a low-latency Serial RapidIO (SRIO) interface.
“The receipt of orders for volume production from our leading customers for the XLP316L processor, just months after its announcement, is a testament to the compelling benefits of the product and to its success in addressing the critical requirements of advanced LTE networks,” said Chris O’Reilly, vice president of marketing for NetLogic Microsystems.
“Through outstanding execution, we have accelerated the delivery of this product to the market at a time when the deployment of LTE infrastructure is gaining momentum worldwide. With highly differentiated performance and feature sets, our XLP processor product family is having tremendous design win success throughout wireless infrastructure, including common platform base stations, service gateways and equipment targeted at the mobile packet core. Its state-of-the-art design is enabling our Tier One customers to keep pace with the increasingly rigorous demands of advanced wireless telecommunications.”
The industry migration from 3G WCDMA and HSPA+ mobile wireless technologies to 4G LTE and LTE-Advanced protocols requires at least a 10X increase in the performance of next-generation base stations to enable significantly greater bandwidth and faster download speeds.
The XLP316L multi-core processor is perfectly suited for this application, offering unparalleled performance of up to 20 Gigabits-per-second (Gbps) and 30 million packets-per-second (Mpps) for converged data plane and control plane processing, all within a low power profile, enabled in part by its development on the advanced 40 nanometer process technology. In addition, its NXCPUs are fully cache and memory coherent for software applications to seamlessly run in Symmetric Multi Processing (SMP) or Asymmetric Multi Processing (AMP) modes.
The XLP316L multi-core, multi-threaded processor features NetLogic Microsystems' high-speed, low-latency Enhanced Fast Messaging Network to enable efficient, high-bandwidth communication among the 16 NXCPUs and to support billions of in-flight messages and packet descriptors between all on-chip elements. The XLP316L processor also offers a unique tri-level cache architecture with more than 6 Megabytes of fully coherent on-chip cache, which deliver 40 Terabits per second (Tbps) of extremely high-speed on-chip memory bandwidth, as well as a 72-bit DDR3 interconnect that yields more than 100 Gbps of off-chip memory bandwidth.
To complement the 16 NXCPUs, the XLP316L processor offers fully-autonomous processing engines that provide independent and complete offload of certain network functions from the NXCPUs, including:
* 10 Gbps of encryption/decryption/authentication, including support for Kasumi and SNOW3G protocols that are required for mobile infrastructure;
* 10 Gbps Network Acceleration Engines for Ingress/Egress Packet Parsing and Management;
* Packet Ordering;
* TCP Segmentation Offload; and
* IEEE 1588 Hardware Time Stamping for Ethernet backhaul timing synchronization.
The XLP multi-core processor integrates a wide range of high-speed networking interfaces for base stations, including:
* Ultra low-latency Serial RapidIO (SRIO) Rev 2.1 with flexible support for 4x1 and 1x4 configurations, enabling connectivity to four DSP or ASIC chips;
* PCI-Express Gen2 (4x1 or 1x4 configuration);
* 8x Gigabit Ethernet (SGMII) channels;
* Dual XAUI ports;
* USB2.0; and
* XEN Hypervisor virtualization and serial I/O virtualization (SRIOV).
The XLP316L multi-core processor integrates 16 high-performance NXCPUs and an innovative quad-issue, quad-threaded processor architecture with superscalar out-of-order execution capabilities to deliver the industry’s highest performance Layers 2-7 processing for mobile wireless infrastructure. In addition, the XLP316L processor offers a number of base station-specific features that make it ideally suited to LTE applications, such as an advanced floating point unit (FPU), Kasumi and SNOW3G security protocol acceleration and a low-latency Serial RapidIO (SRIO) interface.
“The receipt of orders for volume production from our leading customers for the XLP316L processor, just months after its announcement, is a testament to the compelling benefits of the product and to its success in addressing the critical requirements of advanced LTE networks,” said Chris O’Reilly, vice president of marketing for NetLogic Microsystems.
“Through outstanding execution, we have accelerated the delivery of this product to the market at a time when the deployment of LTE infrastructure is gaining momentum worldwide. With highly differentiated performance and feature sets, our XLP processor product family is having tremendous design win success throughout wireless infrastructure, including common platform base stations, service gateways and equipment targeted at the mobile packet core. Its state-of-the-art design is enabling our Tier One customers to keep pace with the increasingly rigorous demands of advanced wireless telecommunications.”
The industry migration from 3G WCDMA and HSPA+ mobile wireless technologies to 4G LTE and LTE-Advanced protocols requires at least a 10X increase in the performance of next-generation base stations to enable significantly greater bandwidth and faster download speeds.
The XLP316L multi-core processor is perfectly suited for this application, offering unparalleled performance of up to 20 Gigabits-per-second (Gbps) and 30 million packets-per-second (Mpps) for converged data plane and control plane processing, all within a low power profile, enabled in part by its development on the advanced 40 nanometer process technology. In addition, its NXCPUs are fully cache and memory coherent for software applications to seamlessly run in Symmetric Multi Processing (SMP) or Asymmetric Multi Processing (AMP) modes.
The XLP316L multi-core, multi-threaded processor features NetLogic Microsystems' high-speed, low-latency Enhanced Fast Messaging Network to enable efficient, high-bandwidth communication among the 16 NXCPUs and to support billions of in-flight messages and packet descriptors between all on-chip elements. The XLP316L processor also offers a unique tri-level cache architecture with more than 6 Megabytes of fully coherent on-chip cache, which deliver 40 Terabits per second (Tbps) of extremely high-speed on-chip memory bandwidth, as well as a 72-bit DDR3 interconnect that yields more than 100 Gbps of off-chip memory bandwidth.
To complement the 16 NXCPUs, the XLP316L processor offers fully-autonomous processing engines that provide independent and complete offload of certain network functions from the NXCPUs, including:
* 10 Gbps of encryption/decryption/authentication, including support for Kasumi and SNOW3G protocols that are required for mobile infrastructure;
* 10 Gbps Network Acceleration Engines for Ingress/Egress Packet Parsing and Management;
* Packet Ordering;
* TCP Segmentation Offload; and
* IEEE 1588 Hardware Time Stamping for Ethernet backhaul timing synchronization.
The XLP multi-core processor integrates a wide range of high-speed networking interfaces for base stations, including:
* Ultra low-latency Serial RapidIO (SRIO) Rev 2.1 with flexible support for 4x1 and 1x4 configurations, enabling connectivity to four DSP or ASIC chips;
* PCI-Express Gen2 (4x1 or 1x4 configuration);
* 8x Gigabit Ethernet (SGMII) channels;
* Dual XAUI ports;
* USB2.0; and
* XEN Hypervisor virtualization and serial I/O virtualization (SRIOV).
Adoption ramps for AMD Fusion processor companion chips from Analogix
COMPUTEX TAIPEI 2011, SANTA CLARA, USA: Analogix Semiconductor Inc., a manufacturer and innovator of high-performance analog and mixed-signal devices for the digital media and communications markets, is driving high-volume production and low-power innovation for OEMs and ODMs with its DisplayPort translators for AMD Fusion APUs.
Announced last December, Analogix has already delivered more than 1 million DisplayPort converter chips to major PC ODMs and OEMs, offering the industry a conversion solution for embedded DisplayPort output to existing LVDS display standards. The products will be on display at Computex Taipei, May 31-June 4, 2011.
Driving integration solutions for AMD Accelerated Processing Unit based platforms ensures manufacturers have increased compatibility with available LCD display panels. With space-saving and power-reduction features built in, manufacturers are ultimately able to deliver smaller, thinner products with improved battery life.
“Building laptops that incorporate Analogix conversion devices gives PC makers flexibility in their LCD panel production,” says Dr. Kewei Yang, chairman and CEO of Analogix. “As a proven hardware and software solution that has been tested with the range of AMD Fusion processors, PC OEMs can now get their notebook products to market as fast as possible.”
The display translator devices (code-named “Travis”), jointly developed by AMD and Analogix, are designed to operate seamlessly with AMD Accelerated Processing Unit based platforms. AMD and Analogix have executed extensive validation plans on AMD reference platforms to provide customers a high confidence path for successful integration of a Travis device.
The ANX3110 chip boasts the unique features of integrated specialized circuitry for content protection, key panel control features such as panel dimming, and the implementation of special power saving modes that work in conjunction with the AMD chipset to reduce overall system power consumption.
Announced last December, Analogix has already delivered more than 1 million DisplayPort converter chips to major PC ODMs and OEMs, offering the industry a conversion solution for embedded DisplayPort output to existing LVDS display standards. The products will be on display at Computex Taipei, May 31-June 4, 2011.
Driving integration solutions for AMD Accelerated Processing Unit based platforms ensures manufacturers have increased compatibility with available LCD display panels. With space-saving and power-reduction features built in, manufacturers are ultimately able to deliver smaller, thinner products with improved battery life.
“Building laptops that incorporate Analogix conversion devices gives PC makers flexibility in their LCD panel production,” says Dr. Kewei Yang, chairman and CEO of Analogix. “As a proven hardware and software solution that has been tested with the range of AMD Fusion processors, PC OEMs can now get their notebook products to market as fast as possible.”
The display translator devices (code-named “Travis”), jointly developed by AMD and Analogix, are designed to operate seamlessly with AMD Accelerated Processing Unit based platforms. AMD and Analogix have executed extensive validation plans on AMD reference platforms to provide customers a high confidence path for successful integration of a Travis device.
The ANX3110 chip boasts the unique features of integrated specialized circuitry for content protection, key panel control features such as panel dimming, and the implementation of special power saving modes that work in conjunction with the AMD chipset to reduce overall system power consumption.
AMD launches Indian Universities’ first ever Faculty Development Program for OpenCL
BANGALORE, INDIA: AMD India recently launched the first Faculty Development Program for OpenCL available in India. The three-day workshop was organized in partnership with Coimbatore Institute of Technology (CIT), Coimbatore, India and was the first of its kind to be organized in the country.
This workshop was attended by faculty members from various Engineering and Technology universities and colleges including CIT, SSN, Bharathiar University, Bharathidasan University-Technology Park, Amrita University, Avinashilingam University, SRM University, Anna University (CEG) - Chennai, PSG College of Technology, The American College, Karpagam University, Lady Dock College, Sri Bhagawan Mahaveer Jain College of Engineering and RV College of Engineering.
The program is targeted towards the OpenCL (Open Computing Language) standard, which is a framework for writing programs that execute across heterogeneous platforms consisting of Central Processing Units (CPUs), Graphics Processing Units (GPUs) and other processors. Faculty members were trained in the subject using AMD’s University Kit, a set of materials that can be leveraged by any Indian university to assist them in teaching a semester course in OpenCL programming.
Included in the University Kit is a 13 lecture series, equipped with instructor and speaker notes, as well as code examples where necessary and can be downloaded from this link - OpenCL University Kit. The training methodology was interactive, using tools like case studies, live examples and free flowing discussions.
This effort underscores AMD’s commitment to the educational community, which currently includes a number of research initiatives, created to equip the next generation of software developers and programmers with the knowledge needed to lead the era of heterogeneous computing. OpenCL, the only non-proprietary, royalty-free industry standard available today for true heterogeneous computing, helps developers to harness the full compute power of both the CPU and GPU to create innovative applications for vivid computing experiences.
“With the launch of the AMD Fusion Accelerated Processing Unit, or APU, where AMD combined the GPU and CPU capabilities into a single die design, enabling outstanding graphics performance, improved energy efficiencies and exceptional compute capabilities, we have laid the foundation for heterogeneous computing,” said Jay Hiremath, director, AMD Platform and Software Engineering,
“AMD is committed to India through its investment in this market. We have a significant number of programmers and developers working at our R&D facilities in Hyderabad and Bangalore. With the advent of parallel computing, there is a need for creating a rich ecosystem of developers and programmers in the country, prepared for a changing global marketplace. This Faculty Development Program will facilitate exactly that, where large scale adoption of OpenCL will help leverage all the compute power at our disposal, be it in the CPU, GPU or APU.”
Dr. S.R.K.Prasad, correspondent, CIT added: “CIT is on the road to working in many frontier technologies in various fields of engineering. OpenCL will be the future platform to depict and understand complex real life engineering applications, especially in the field of computer simulation which would help in understanding and solving many problems even in medicine, science and management. I think engineering and technology universities, across the country should incorporate OpenCL into their curriculum right from the undergraduate level up to the doctoral level. We, at CIT would like to take the lead on this, as it will give our students an edge to compete globally.”
With many universities in India now working actively towards adoption of OpenCL, the transition to the parallel computing era is ready for its next phase of development.
This workshop was attended by faculty members from various Engineering and Technology universities and colleges including CIT, SSN, Bharathiar University, Bharathidasan University-Technology Park, Amrita University, Avinashilingam University, SRM University, Anna University (CEG) - Chennai, PSG College of Technology, The American College, Karpagam University, Lady Dock College, Sri Bhagawan Mahaveer Jain College of Engineering and RV College of Engineering.
The program is targeted towards the OpenCL (Open Computing Language) standard, which is a framework for writing programs that execute across heterogeneous platforms consisting of Central Processing Units (CPUs), Graphics Processing Units (GPUs) and other processors. Faculty members were trained in the subject using AMD’s University Kit, a set of materials that can be leveraged by any Indian university to assist them in teaching a semester course in OpenCL programming.
Included in the University Kit is a 13 lecture series, equipped with instructor and speaker notes, as well as code examples where necessary and can be downloaded from this link - OpenCL University Kit. The training methodology was interactive, using tools like case studies, live examples and free flowing discussions.
This effort underscores AMD’s commitment to the educational community, which currently includes a number of research initiatives, created to equip the next generation of software developers and programmers with the knowledge needed to lead the era of heterogeneous computing. OpenCL, the only non-proprietary, royalty-free industry standard available today for true heterogeneous computing, helps developers to harness the full compute power of both the CPU and GPU to create innovative applications for vivid computing experiences.
“With the launch of the AMD Fusion Accelerated Processing Unit, or APU, where AMD combined the GPU and CPU capabilities into a single die design, enabling outstanding graphics performance, improved energy efficiencies and exceptional compute capabilities, we have laid the foundation for heterogeneous computing,” said Jay Hiremath, director, AMD Platform and Software Engineering,
“AMD is committed to India through its investment in this market. We have a significant number of programmers and developers working at our R&D facilities in Hyderabad and Bangalore. With the advent of parallel computing, there is a need for creating a rich ecosystem of developers and programmers in the country, prepared for a changing global marketplace. This Faculty Development Program will facilitate exactly that, where large scale adoption of OpenCL will help leverage all the compute power at our disposal, be it in the CPU, GPU or APU.”
Dr. S.R.K.Prasad, correspondent, CIT added: “CIT is on the road to working in many frontier technologies in various fields of engineering. OpenCL will be the future platform to depict and understand complex real life engineering applications, especially in the field of computer simulation which would help in understanding and solving many problems even in medicine, science and management. I think engineering and technology universities, across the country should incorporate OpenCL into their curriculum right from the undergraduate level up to the doctoral level. We, at CIT would like to take the lead on this, as it will give our students an edge to compete globally.”
With many universities in India now working actively towards adoption of OpenCL, the transition to the parallel computing era is ready for its next phase of development.
TowerJazz announces new design center partnership incentive program
Design Automation Conference 2011, MIGDAL HA’EMEK, ISRAEL & NEWPORT BEACH, USA: TowerJazz announced its “Design Star Awards Program,” a new design center partnership incentive program offered to independent design centers. The program will encourage design centers that enroll in this program to refer new customers and new products to TowerJazz.
This will increase TowerJazz’s IP portfolio, specifically increasing the number of specialty designs taped into TowerJazz, thereby strengthening TowerJazz’s position as the leading specialty foundry. In turn, these design partners will receive benefits from TowerJazz on products and services ordered either by such design partners or their customers.
Aligned with TowerJazz’s position as a specialty foundry, the independent design centers are encouraged under the incentive program to refer their customers to manufacture products using TowerJazz specialty technologies such as RF/high performance analog, power management, CMOS image sensor, mixed-signal and MEMS as their preferred platform.
The TowerJazz Design Star Awards Program offers three levels of partnership: platinum, gold and silver. For each TowerJazz product or service ordered under this program, points are accrued and criteria are defined regarding participation at each level. The design partners can redeem their points against mask-sets, proto-lots, MPW or other engineering services.
“Our Design Star Awards Program benefits TowerJazz design partners and is a two-way stream; they will encourage their customers to manufacture products at TowerJazz and we will recommend our customers to design their products with our design partners,” said Ori Galzur, TowerJazz VP of Design Center and PDK Development. “This is a win-win program not only for our design partners and TowerJazz, but also for our mutual customers as they will benefit from best-in-class design and manufacturing services.”
This will increase TowerJazz’s IP portfolio, specifically increasing the number of specialty designs taped into TowerJazz, thereby strengthening TowerJazz’s position as the leading specialty foundry. In turn, these design partners will receive benefits from TowerJazz on products and services ordered either by such design partners or their customers.
Aligned with TowerJazz’s position as a specialty foundry, the independent design centers are encouraged under the incentive program to refer their customers to manufacture products using TowerJazz specialty technologies such as RF/high performance analog, power management, CMOS image sensor, mixed-signal and MEMS as their preferred platform.
The TowerJazz Design Star Awards Program offers three levels of partnership: platinum, gold and silver. For each TowerJazz product or service ordered under this program, points are accrued and criteria are defined regarding participation at each level. The design partners can redeem their points against mask-sets, proto-lots, MPW or other engineering services.
“Our Design Star Awards Program benefits TowerJazz design partners and is a two-way stream; they will encourage their customers to manufacture products at TowerJazz and we will recommend our customers to design their products with our design partners,” said Ori Galzur, TowerJazz VP of Design Center and PDK Development. “This is a win-win program not only for our design partners and TowerJazz, but also for our mutual customers as they will benefit from best-in-class design and manufacturing services.”
Mindspeed spotlights broad range of semiconductor solutions
COMPUTEX TAIPEI 2011, NEWPORT BEACH, USA: Mindspeed Technologies Inc., a leading supplier of semiconductor solutions for network infrastructure applications, announced that it is demonstrating its extensive family of fiber access, optical networking and signal conditioning products during Computex Taipei 2011, Asia's largest information and communications technology (ICT) event. The company will be showcasing its Comcerto multi-core packet processors and its advanced signal integrity and switching solutions.
Mindspeed will be demonstrating its products during Computex Taipei, today through June 4, 2011, in Rooms #1139 and #1140 at the Grand Hyatt Taipei in Taipei, Taiwan. Highlights include:
Fiber Access Service Delivery: Mindspeed will feature live demonstrations of its Comcerto multi-core packet processors, which are optimized to deliver gigabit rate triple play services, while consuming very little power. The processors will be shown delivering multiple simultaneous high definition (HD) video streams with robust Quality of Service (QoS), in a “headless” video gateway platform. Mindspeed will also demonstrate home automation/security powered by OSGi-based applications that can be run while delivering standard triple play services.
Signal Conditioning: Mindspeed’s planned demonstrations include a universal serial bus 3 (USB 3) redriver for laptops and docking stations, and a variety of signal integrity and switching products for PCI Express (PCIe), serial attached SCSI (SAS), serial advanced technology attachment (SATA), USB and other key standards. The company’s Amplif-Eye signal integrity solutions enable system designers to sustain error-free, high-fidelity data transmission as the industry migrates to higher data rates over long printed circuit board (PCB) traces and thinner cables.
Mindspeed will be demonstrating its products during Computex Taipei, today through June 4, 2011, in Rooms #1139 and #1140 at the Grand Hyatt Taipei in Taipei, Taiwan. Highlights include:
Fiber Access Service Delivery: Mindspeed will feature live demonstrations of its Comcerto multi-core packet processors, which are optimized to deliver gigabit rate triple play services, while consuming very little power. The processors will be shown delivering multiple simultaneous high definition (HD) video streams with robust Quality of Service (QoS), in a “headless” video gateway platform. Mindspeed will also demonstrate home automation/security powered by OSGi-based applications that can be run while delivering standard triple play services.
Signal Conditioning: Mindspeed’s planned demonstrations include a universal serial bus 3 (USB 3) redriver for laptops and docking stations, and a variety of signal integrity and switching products for PCI Express (PCIe), serial attached SCSI (SAS), serial advanced technology attachment (SATA), USB and other key standards. The company’s Amplif-Eye signal integrity solutions enable system designers to sustain error-free, high-fidelity data transmission as the industry migrates to higher data rates over long printed circuit board (PCB) traces and thinner cables.
TowerJazz announces availability of wireless antenna switch silicon-on-insulator (SOI) process technology
MIGDAL HA’EMEK, ISRAEL & NEWPORT BEACH, USA: TowerJazz, the global specialty foundry leader, announced availability of its wireless antenna switch SOI process technology applicable to multiple wireless standards. SOI based solutions cost substantially less than legacy solutions based on GaAs pHEMPT or silicon-on-sapphire (SOS) technologies.
The TowerJazz SOI technology is unique relative to other SOI processes in that it maintains full compatibility with its bulk CMOS process enabling integration of control functions, low-noise amplifiers and power amplifiers on a single chip. High-end smart-phones can benefit most from integration while lower-end phones can benefit simply from the lower cost of SOI making the technology relevant for most of the 1.4 billion handset units sold each year.
In addition to the process, design IP is available to kick-start the design effort. An example is a switch IP block optimized to achieve excellent channel isolation of better than -40 dBm, insertion loss of 0.47 dB in low-band and 0.58 dB in high-band, low harmonics of better than 75 dBc at cellular power levels, and intermodulation distortion measured as low as -117 dBm.
The TowerJazz SOI process combines a 6 or 4 metal layer CMOS process with high resistivity SOI substrates. It is a 0.18µm technology with dual gate 1.8V and 3.3V or 5V MOSFETs and a 5V RFLDMOS with Ft of 19 GHz and breakdown of 20V. The 3.3V and 5V FETs facilitate the integration of HVCMOS blocks while the 1.8V FETs are the integration of logic functions. The LDMOS device provides for reliable, high performance RF power. The passive components include silicided and unsilicided poly resistors, 2 fF/µm² and stacked 4 fF/µm² metal-insulator-metal capacitors, scalable inductors and discrete size baluns and transformers.
While using an SOI starting material, this unique technology offers “bulk-like” behavior of the active MOSFETs, free of floating body effects for ease of IP integration. Isolation between device wells and of field areas below sensitive passive components and metal routing is provided by an oxide filled trench to the buried oxide.
“TowerJazz’s SOI technology is providing our customers a unique set of features targeting the cellular switch market at a lower cost than the incumbent technologies of GaAs pHEMT and silicon-on-sapphire. Unlike other SOI technologies, our process allows the seamless integration of existing bulk IP such as power control, low-noise amplifiers and even power amplifiers,” said Dr. Marco Racanelli, Senior Vice President and General Manager, RF and High Performance Analog Business Group.
The TowerJazz SOI technology is unique relative to other SOI processes in that it maintains full compatibility with its bulk CMOS process enabling integration of control functions, low-noise amplifiers and power amplifiers on a single chip. High-end smart-phones can benefit most from integration while lower-end phones can benefit simply from the lower cost of SOI making the technology relevant for most of the 1.4 billion handset units sold each year.
In addition to the process, design IP is available to kick-start the design effort. An example is a switch IP block optimized to achieve excellent channel isolation of better than -40 dBm, insertion loss of 0.47 dB in low-band and 0.58 dB in high-band, low harmonics of better than 75 dBc at cellular power levels, and intermodulation distortion measured as low as -117 dBm.
The TowerJazz SOI process combines a 6 or 4 metal layer CMOS process with high resistivity SOI substrates. It is a 0.18µm technology with dual gate 1.8V and 3.3V or 5V MOSFETs and a 5V RFLDMOS with Ft of 19 GHz and breakdown of 20V. The 3.3V and 5V FETs facilitate the integration of HVCMOS blocks while the 1.8V FETs are the integration of logic functions. The LDMOS device provides for reliable, high performance RF power. The passive components include silicided and unsilicided poly resistors, 2 fF/µm² and stacked 4 fF/µm² metal-insulator-metal capacitors, scalable inductors and discrete size baluns and transformers.
While using an SOI starting material, this unique technology offers “bulk-like” behavior of the active MOSFETs, free of floating body effects for ease of IP integration. Isolation between device wells and of field areas below sensitive passive components and metal routing is provided by an oxide filled trench to the buried oxide.
“TowerJazz’s SOI technology is providing our customers a unique set of features targeting the cellular switch market at a lower cost than the incumbent technologies of GaAs pHEMT and silicon-on-sapphire. Unlike other SOI technologies, our process allows the seamless integration of existing bulk IP such as power control, low-noise amplifiers and even power amplifiers,” said Dr. Marco Racanelli, Senior Vice President and General Manager, RF and High Performance Analog Business Group.
Renesas Electronics intros CubeSuite+ integrated development environment for MCUs
TOKYO, JAPAN: Renesas Electronics Corp. announced the availability of the new integrated development environment, the CubeSuite+, that provides unified support for the company’s microcontrollers (MCUs) with 8-bit through 32-bit architectures.
An integrated development environment organically links all the tools (compiler, debugger for use with the emulator, etc.) needed when developing software (programs) for MCUs, making it possible to perform all design, coding, evaluation, and verification tasks on the same host machine.
Currently, customers must use either the CubeSuite or High-performance Embedded Workshop integrated development environment, depending on the type of MCU they are developing software for. In contrast, the new CubeSuite+ will support all newly developed MCU products released from this point forward.
The first release of CubeSuite+ will support the MCUs covered by the earlier CubeSuite product, such as the V850 Family, as well as the RL78 Family of low-power MCUs, the first MCU products to be released after the merger of NEC Electronics and Renesas Technology to form Renesas Electronics. Subsequent releases will expand the range of MCU families supported to include the RX Family of midrange MCUs among other products.
An integrated development environment organically links all the tools (compiler, debugger for use with the emulator, etc.) needed when developing software (programs) for MCUs, making it possible to perform all design, coding, evaluation, and verification tasks on the same host machine.
Currently, customers must use either the CubeSuite or High-performance Embedded Workshop integrated development environment, depending on the type of MCU they are developing software for. In contrast, the new CubeSuite+ will support all newly developed MCU products released from this point forward.
The first release of CubeSuite+ will support the MCUs covered by the earlier CubeSuite product, such as the V850 Family, as well as the RL78 Family of low-power MCUs, the first MCU products to be released after the merger of NEC Electronics and Renesas Technology to form Renesas Electronics. Subsequent releases will expand the range of MCU families supported to include the RX Family of midrange MCUs among other products.
Intel’s Maloney talks mobile growth, industry opportunities at Computex
COMPUTEX TAIPEI 2011, TAIPEI, TAIWAN: Intel Corp. executive VP Sean Maloney said that by the end of 2012, 40 percent of the consumer laptop market segment will encompass an emerging new breed of no-compromise computers, called “Ultrabook,” which will increasingly combine best-in-class performance, improved responsiveness and security in thin, elegant form factors.
During the opening keynote speech at Computex, one of the world’s largest technology trade shows, Maloney provided further details on the significant changes Intel is making to the Intel Core processor roadmap to enable this new category. He also reiterated Intel’s push to accelerate the pace of innovation for Intel Atom processor-based system-on-chips (SoCs) for netbooks, smartphones, tablets, and other companion devices.
“Computing is taking many forms,” said Maloney. “Technology innovation is a catalyst, and we believe the changes Intel is making to its roadmaps, together with strong industry collaboration, will bring about an exciting change in personal computing over the next few years.”
The “Ultrabook”
Intel’s vision is to enable a new user experience by accelerating a new class of mobile computers. These computers will marry the performance and capabilities of today’s laptops with tablet-like features and deliver a highly responsive and secure experience, in a thin, light and elegant design. The Ultrabook will be shaped by Moore’s Law and silicon technology in the same way they have shaped the traditional PC for the past 40 years.
Maloney described three key phases in the company’s strategy to accelerate this vision, which begins to unfold today with the company’s latest 2nd Generation Intel Core processors. This family of products will enable thin, light and beautiful designs that are less than 20mm (0.8 inch) thick, and mainstream price points under US$1,000. Systems based on these chips will be available for the 2011 winter holiday shopping season and include the UX21, ASUS Ultrabook.
ASUS chairman Jonney Shih joined Maloney on stage to showcase the company’s new ultra-thin laptop based on the latest 2nd Generation Intel Core processor.
“At ASUS, we are very much aligned with Intel’s vision of Ultrabook,” said Shih. “Our customers are demanding an uncompromised computing experience in a lightweight, highly portable design that responds to their needs quickly. Transforming the PC into an ultra thin, ultra responsive device will change the way people interact with their PC.”
Building on the latest 2nd Generation Intel Core technology, Maloney outlined the next generation Intel processor family codenamed “Ivy Bridge,” which is scheduled for availability in systems in the first half of 2012. Laptops based on “Ivy Bridge” will bring improved power efficiency, smart visual performance, increased responsiveness and enhanced security. “Ivy Bridge” is the first high-volume chip based on Intel’s 22 nanometer (nm) manufacturing technology that uses a revolutionary 3-D transistor design called Tri-Gate announced in May. Maloney also highlighted complementary USB 3.0 and Thunderbolt technologies which are part of Intel’s ongoing work to drive the PC platform forward.
Following “Ivy Bridge,” planned 2013 products codenamed “Haswell” are the third step toward achieving the Ultrabook and reinventing the capabilities of the laptop in ultra thin and light, responsive and more secure designs. With “Haswell,” Intel will change the mainstream laptop thermal design point by reducing the microprocessor power to half of today’s design point.
Accelerating the Intel Atom processor roadmap
Maloney highlighted key milestones and additional details on upcoming generations of Intel Atom processor-based platforms for tablets, netbooks and smartphones. The Atom processor will outpace Moore’s Law, accelerating from 32nm through 22nm to 14nm within 3 successive years. Having a cadence of a new-process-generation every year will result in significant reduction in transistor leakage, lower active power and an increase of transistor density to enable more powerful smartphones, tablets, and netbooks with more features and longer battery life.
Reaching its 100 million-unit milestone this month, Intel is preparing its next-generation netbook platform, codenamed “Cedar Trail.” “Cedar Trail” is the first netbook platform based on Intel’s 32nm technology, and will enable ultra-thin, fanless designs with new capabilities such as Intel Rapid Start technology which provides fast resume, Intel Smart Connect Technology which enables an always updated experience even during standby, Intel Wireless Display and PC Synch, which let users wirelessly update and synchronize documents, content and media across multiple devices.
In addition, the new platform is expected to enable more than 10 hours of battery life and weeks of standby. “Cedar Trail” will support leading operating systems, such as Microsoft Windows*, Google Chrome* and MeeGo*.
In addition, Maloney showcased more than 10 tablets, running on three different operating systems, that are available today based on the Intel Atom processor Z670. The platform already has more than 35 design wins since its launch in April, with several convertibles, sliders and other innovative designs on shelves now and more coming through the rest of the year.
Maloney also discussed “Medfield,” Intel’s first purpose-built 32nm platform for smartphones and tablets. “Medfield” has been optimized for both low power and high performance and will deliver long use-time, rich media and gaming, and advanced imaging capabilities. To illustrate this point in tablets, Intel showcased a “Medfield” design running Google Android 3.0 (“Honeycomb”) for the first time. In production later this year, the platform will enable sub-9mm designs that weigh less than 1.5 pounds for tablet designs in market the first half of 2012. It will support a range of operating systems including Android and MeeGo.
According to Maloney, “The work Intel is doing with the Intel Atom processor roadmap, coupled with the significant changes we are making to our Intel Core processor roadmaps, will continue to enhance Intel’s ability to deliver complete hardware solutions with a choice of software platforms across a full spectrum of computing -- from back-end servers that power the cloud to the billions of devices that access the cloud.”
Cloud’s rapid expansion
More people and devices connecting to the Internet will lead to unprecedented growth in cloud-based services for storage, synchronization and entertainment, according to Maloney, and Intel is poised to grow with it. He said that one new Intel-based server is needed for roughly every additional 600 new smartphones or 122 new tablets connecting to the Internet.
He also reiterated the company’s “Cloud 2015” vision of a world of interoperable “federated” clouds that allow enterprises to share data securely across public and private clouds; “automated” networks that allow the movement of workloads between servers in the data center for better utilization and energy efficiency, and “device-aware” clouds that know what types of applications, commands and processing.
In closing, Maloney stressed the critical role of the Taiwan IT industry in the next transformation of computing. He called for collective innovations that will lead the industry into the next era as computing takes many new forms and becomes ever more pervasive and affordable. “The Taiwan IT industry will be instrumental in realizing this vision,” said Maloney.
During the opening keynote speech at Computex, one of the world’s largest technology trade shows, Maloney provided further details on the significant changes Intel is making to the Intel Core processor roadmap to enable this new category. He also reiterated Intel’s push to accelerate the pace of innovation for Intel Atom processor-based system-on-chips (SoCs) for netbooks, smartphones, tablets, and other companion devices.
“Computing is taking many forms,” said Maloney. “Technology innovation is a catalyst, and we believe the changes Intel is making to its roadmaps, together with strong industry collaboration, will bring about an exciting change in personal computing over the next few years.”
The “Ultrabook”
Intel’s vision is to enable a new user experience by accelerating a new class of mobile computers. These computers will marry the performance and capabilities of today’s laptops with tablet-like features and deliver a highly responsive and secure experience, in a thin, light and elegant design. The Ultrabook will be shaped by Moore’s Law and silicon technology in the same way they have shaped the traditional PC for the past 40 years.
Maloney described three key phases in the company’s strategy to accelerate this vision, which begins to unfold today with the company’s latest 2nd Generation Intel Core processors. This family of products will enable thin, light and beautiful designs that are less than 20mm (0.8 inch) thick, and mainstream price points under US$1,000. Systems based on these chips will be available for the 2011 winter holiday shopping season and include the UX21, ASUS Ultrabook.
ASUS chairman Jonney Shih joined Maloney on stage to showcase the company’s new ultra-thin laptop based on the latest 2nd Generation Intel Core processor.
“At ASUS, we are very much aligned with Intel’s vision of Ultrabook,” said Shih. “Our customers are demanding an uncompromised computing experience in a lightweight, highly portable design that responds to their needs quickly. Transforming the PC into an ultra thin, ultra responsive device will change the way people interact with their PC.”
Building on the latest 2nd Generation Intel Core technology, Maloney outlined the next generation Intel processor family codenamed “Ivy Bridge,” which is scheduled for availability in systems in the first half of 2012. Laptops based on “Ivy Bridge” will bring improved power efficiency, smart visual performance, increased responsiveness and enhanced security. “Ivy Bridge” is the first high-volume chip based on Intel’s 22 nanometer (nm) manufacturing technology that uses a revolutionary 3-D transistor design called Tri-Gate announced in May. Maloney also highlighted complementary USB 3.0 and Thunderbolt technologies which are part of Intel’s ongoing work to drive the PC platform forward.
Following “Ivy Bridge,” planned 2013 products codenamed “Haswell” are the third step toward achieving the Ultrabook and reinventing the capabilities of the laptop in ultra thin and light, responsive and more secure designs. With “Haswell,” Intel will change the mainstream laptop thermal design point by reducing the microprocessor power to half of today’s design point.
Accelerating the Intel Atom processor roadmap
Maloney highlighted key milestones and additional details on upcoming generations of Intel Atom processor-based platforms for tablets, netbooks and smartphones. The Atom processor will outpace Moore’s Law, accelerating from 32nm through 22nm to 14nm within 3 successive years. Having a cadence of a new-process-generation every year will result in significant reduction in transistor leakage, lower active power and an increase of transistor density to enable more powerful smartphones, tablets, and netbooks with more features and longer battery life.
Reaching its 100 million-unit milestone this month, Intel is preparing its next-generation netbook platform, codenamed “Cedar Trail.” “Cedar Trail” is the first netbook platform based on Intel’s 32nm technology, and will enable ultra-thin, fanless designs with new capabilities such as Intel Rapid Start technology which provides fast resume, Intel Smart Connect Technology which enables an always updated experience even during standby, Intel Wireless Display and PC Synch, which let users wirelessly update and synchronize documents, content and media across multiple devices.
In addition, the new platform is expected to enable more than 10 hours of battery life and weeks of standby. “Cedar Trail” will support leading operating systems, such as Microsoft Windows*, Google Chrome* and MeeGo*.
In addition, Maloney showcased more than 10 tablets, running on three different operating systems, that are available today based on the Intel Atom processor Z670. The platform already has more than 35 design wins since its launch in April, with several convertibles, sliders and other innovative designs on shelves now and more coming through the rest of the year.
Maloney also discussed “Medfield,” Intel’s first purpose-built 32nm platform for smartphones and tablets. “Medfield” has been optimized for both low power and high performance and will deliver long use-time, rich media and gaming, and advanced imaging capabilities. To illustrate this point in tablets, Intel showcased a “Medfield” design running Google Android 3.0 (“Honeycomb”) for the first time. In production later this year, the platform will enable sub-9mm designs that weigh less than 1.5 pounds for tablet designs in market the first half of 2012. It will support a range of operating systems including Android and MeeGo.
According to Maloney, “The work Intel is doing with the Intel Atom processor roadmap, coupled with the significant changes we are making to our Intel Core processor roadmaps, will continue to enhance Intel’s ability to deliver complete hardware solutions with a choice of software platforms across a full spectrum of computing -- from back-end servers that power the cloud to the billions of devices that access the cloud.”
Cloud’s rapid expansion
More people and devices connecting to the Internet will lead to unprecedented growth in cloud-based services for storage, synchronization and entertainment, according to Maloney, and Intel is poised to grow with it. He said that one new Intel-based server is needed for roughly every additional 600 new smartphones or 122 new tablets connecting to the Internet.
He also reiterated the company’s “Cloud 2015” vision of a world of interoperable “federated” clouds that allow enterprises to share data securely across public and private clouds; “automated” networks that allow the movement of workloads between servers in the data center for better utilization and energy efficiency, and “device-aware” clouds that know what types of applications, commands and processing.
In closing, Maloney stressed the critical role of the Taiwan IT industry in the next transformation of computing. He called for collective innovations that will lead the industry into the next era as computing takes many new forms and becomes ever more pervasive and affordable. “The Taiwan IT industry will be instrumental in realizing this vision,” said Maloney.
Samsung begins mass producing 30nm-class, 32-Gigabyte memory modules for green IT systems
SEOUL, SOUTH KOREA: Samsung Electronics Co. Ltd announced that it is the first in the industry to start mass producing 32 gigabyte (GB) memory modules, essential for cloud computing and advanced server systems, using 30 nanometer (nm) class* four gigabit (Gb) DDR3 DRAM chips.
“With this module, Samsung has secured the highest level of product and solution competitiveness in the DRAM market for PC, server and mobile applications,” said Wanhoon Hong, executive vice president, memory sales & marketing, Samsung Electronics. “We also plan to ship more energy-efficient 4Gb DDR3 DRAM based on 20nm-class process technology in the second half of this year, which will significantly expand the rapidly growing market for green IT memory solutions. Moreover, we intend to keep delivering the greenest memory products with optimal performance for customers,” he added..
Samsung’s 30nm-class 4Gb DDR3 chip offers an approximate 50 percent increase in productivity over a 40nm-class 4Gb DDR3, and as a result is expected to achieve rapid market penetration.
Samsung started producing monolithic 4Gb DDR3 DRAM devices based on 30nm-class technology in February, which is only one year after it started producing 40nm-class 4Gb DDR3 DRAM devices. Just two months later, it began to provide 16GB modules to a number of server system manufacturers.
With its new 32GB registered dual inline memory module (RDIMM) and an 8GB small outline dual in-line memory module (SO-DIMM) added this month, Samsung has completed a full product line-up of 30nm-class 4Gb green DDR3-based solutions.
In addition, by offering its new DDR3 modules shortly after providing 30nm-class 4Gb LPDDR2 DRAM, Samsung is now supporting the needs of the entire marketplace for 30nm-class DRAM solutions from mobile devices to enterprise server systems.
Samsung’s new 1.35-volt 32GB RDIMM performs at up to 1,866 megabits per second (Mbps), achieving a 40 percent improvement over a 1,333 Mbps, 40nm-class 32GB RDIMM operating at 1.5 volts, therein consuming 18 percent less power. The 40nm-class 32GB RDIMM was bestowed an Eco-Design Award at the International Consumer Electronics Show (CES) 2011 Innovation Awards. Also, the new 8GB SO-DIMM version processes data at up to 2,133 Mbps when operating at 1.5 volts.
Samsung expects to have more than 10 percent of its total DRAM chip production in 2012 at the 4Gb (or higher) density.
According to IHS, shipments of 4Gb DRAM are expected to account for approximately 10 percent of total DRAM shipments in 2012, 35 percent in 2013 and up to 57 percent in 2014.
Meanwhile, Samsung plans to keep raising awareness of its green memory initiatives and its ‘Creating Shared Value’ (CSV) approach toward the global IT industry, as it seeks greater collaboration on energy-efficiency with CIOs of global companies.
“With this module, Samsung has secured the highest level of product and solution competitiveness in the DRAM market for PC, server and mobile applications,” said Wanhoon Hong, executive vice president, memory sales & marketing, Samsung Electronics. “We also plan to ship more energy-efficient 4Gb DDR3 DRAM based on 20nm-class process technology in the second half of this year, which will significantly expand the rapidly growing market for green IT memory solutions. Moreover, we intend to keep delivering the greenest memory products with optimal performance for customers,” he added..
Samsung’s 30nm-class 4Gb DDR3 chip offers an approximate 50 percent increase in productivity over a 40nm-class 4Gb DDR3, and as a result is expected to achieve rapid market penetration.
Samsung started producing monolithic 4Gb DDR3 DRAM devices based on 30nm-class technology in February, which is only one year after it started producing 40nm-class 4Gb DDR3 DRAM devices. Just two months later, it began to provide 16GB modules to a number of server system manufacturers.
With its new 32GB registered dual inline memory module (RDIMM) and an 8GB small outline dual in-line memory module (SO-DIMM) added this month, Samsung has completed a full product line-up of 30nm-class 4Gb green DDR3-based solutions.
In addition, by offering its new DDR3 modules shortly after providing 30nm-class 4Gb LPDDR2 DRAM, Samsung is now supporting the needs of the entire marketplace for 30nm-class DRAM solutions from mobile devices to enterprise server systems.
Samsung’s new 1.35-volt 32GB RDIMM performs at up to 1,866 megabits per second (Mbps), achieving a 40 percent improvement over a 1,333 Mbps, 40nm-class 32GB RDIMM operating at 1.5 volts, therein consuming 18 percent less power. The 40nm-class 32GB RDIMM was bestowed an Eco-Design Award at the International Consumer Electronics Show (CES) 2011 Innovation Awards. Also, the new 8GB SO-DIMM version processes data at up to 2,133 Mbps when operating at 1.5 volts.
Samsung expects to have more than 10 percent of its total DRAM chip production in 2012 at the 4Gb (or higher) density.
According to IHS, shipments of 4Gb DRAM are expected to account for approximately 10 percent of total DRAM shipments in 2012, 35 percent in 2013 and up to 57 percent in 2014.
Meanwhile, Samsung plans to keep raising awareness of its green memory initiatives and its ‘Creating Shared Value’ (CSV) approach toward the global IT industry, as it seeks greater collaboration on energy-efficiency with CIOs of global companies.
SanDisk intros iNAND Extreme embedded storage for tablets and mobile devices
Computex, TAIWAN: SanDisk Corp., a global leader in flash memory storage solutions, introduced the iNAND Extreme embedded flash drive (EFD), SanDisk’s first in a new line of products designed for high-end tablets running advanced operating systems and data-intensive applications. The drive features up to 50 megabyte per second (MB/sec)1 sequential write and up to 80MB/sec sequential read speeds.
High-performance embedded flash storage can significantly improve a tablet’s multimedia synchronization speeds, file-transfer rates and operating system responsiveness. Fast sequential performance is essential when capturing HD2 and 3D2 video content or when transferring large files via the high-speed USB 3.0 interface. By selecting the iNAND Extreme EFD for their next-generation tablet designs, OEMs can improve the key performance criteria that produce an enjoyable user experience.
“iNAND Extreme broadens our embedded product line to cover the needs of all mobile market segments, from feature phones to high-end tablets,” said Amir Lehr, vice president, embedded business, SanDisk. “We offer OEMs high-quality products as well as the experience and technical know-how needed to optimize our solutions for specific applications and usage scenarios.”
SanDisk engineers work closely with mobile and tablet manufacturers to ensure they integrate iNAND products for optimal performance and efficiency in new hardware designs. SanDisk developed its e.MMC based iNAND Extreme EFDs through industry-leading mobile usage analysis capabilities and the experience accumulated through many successful mobile and consumer electronic designs.
Already a dominant choice for embedded smartphone storage, the e.MMC interface has quickly established itself as an attractive solution for the tablet market.
“The embedded application market is experiencing significant growth through the increasing popularity and variety of mobile computing platforms,” said Jeff Janukowicz, research manager, solid state storage technology, IDC. “Companies with broad embedded product lineups and value-added services have an increasing capability to meet the diverse needs within the mobile market.”
Available in a highly compact 12mm x 16mm JEDEC package with heights as low as 1.0mm, the iNAND Extreme EFD enables slim and highly portable mobile and tablet designs. By conserving internal space, the drive allows more room for other components such as larger batteries—particularly important in high-end tablets with demanding energy needs or larger screens.
The iNAND Extreme EFD comes in 16 gigabyte (GB)3 to 64GB capacities and is scheduled for sampling in Q3 2011. The new drive expands SanDisk’s segmented embedded storage lineup, which includes iNAND and iNAND Ultra drives for handsets and tablets.
SanDisk iNAND and iNAND ultra EFDs
The iNAND EFD is available in storage capacities ranging from 2GB to 64GB for quick integration into handsets and other designs that require an e.MMC interface. The drive features up to 30MB/sec read and up to 13MB/sec write speeds and can serve as a reliable boot device and mass storage solution.
The iNAND Ultra EFD offers up to 40MB/sec read and 20MB/sec write speeds that increase the system responsiveness of feature-rich smartphones that need fast, high-capacity storage in a small form factor.
All iNAND EFDs utilize a highly advanced caching technology that increases system responsiveness for faster application loading, web-browsing and multitasking. SanDisk works closely with all major mobile OEMs, chipset and operating system vendors to ensure tight integration between host and storage devices. This engagement
is crucial to achieving a more enjoyable user experience and is a key reason why iNAND ranks among the leading e.MMC devices on the market.
High-performance embedded flash storage can significantly improve a tablet’s multimedia synchronization speeds, file-transfer rates and operating system responsiveness. Fast sequential performance is essential when capturing HD2 and 3D2 video content or when transferring large files via the high-speed USB 3.0 interface. By selecting the iNAND Extreme EFD for their next-generation tablet designs, OEMs can improve the key performance criteria that produce an enjoyable user experience.
“iNAND Extreme broadens our embedded product line to cover the needs of all mobile market segments, from feature phones to high-end tablets,” said Amir Lehr, vice president, embedded business, SanDisk. “We offer OEMs high-quality products as well as the experience and technical know-how needed to optimize our solutions for specific applications and usage scenarios.”
SanDisk engineers work closely with mobile and tablet manufacturers to ensure they integrate iNAND products for optimal performance and efficiency in new hardware designs. SanDisk developed its e.MMC based iNAND Extreme EFDs through industry-leading mobile usage analysis capabilities and the experience accumulated through many successful mobile and consumer electronic designs.
Already a dominant choice for embedded smartphone storage, the e.MMC interface has quickly established itself as an attractive solution for the tablet market.
“The embedded application market is experiencing significant growth through the increasing popularity and variety of mobile computing platforms,” said Jeff Janukowicz, research manager, solid state storage technology, IDC. “Companies with broad embedded product lineups and value-added services have an increasing capability to meet the diverse needs within the mobile market.”
Available in a highly compact 12mm x 16mm JEDEC package with heights as low as 1.0mm, the iNAND Extreme EFD enables slim and highly portable mobile and tablet designs. By conserving internal space, the drive allows more room for other components such as larger batteries—particularly important in high-end tablets with demanding energy needs or larger screens.
The iNAND Extreme EFD comes in 16 gigabyte (GB)3 to 64GB capacities and is scheduled for sampling in Q3 2011. The new drive expands SanDisk’s segmented embedded storage lineup, which includes iNAND and iNAND Ultra drives for handsets and tablets.
SanDisk iNAND and iNAND ultra EFDs
The iNAND EFD is available in storage capacities ranging from 2GB to 64GB for quick integration into handsets and other designs that require an e.MMC interface. The drive features up to 30MB/sec read and up to 13MB/sec write speeds and can serve as a reliable boot device and mass storage solution.
The iNAND Ultra EFD offers up to 40MB/sec read and 20MB/sec write speeds that increase the system responsiveness of feature-rich smartphones that need fast, high-capacity storage in a small form factor.
All iNAND EFDs utilize a highly advanced caching technology that increases system responsiveness for faster application loading, web-browsing and multitasking. SanDisk works closely with all major mobile OEMs, chipset and operating system vendors to ensure tight integration between host and storage devices. This engagement
is crucial to achieving a more enjoyable user experience and is a key reason why iNAND ranks among the leading e.MMC devices on the market.
Broadcom ignites innovation with PC industry's first 40nm Wi-Fi and Bluetooth combo chip
TAIPEI, TAIWAN: Broadcom Corp. is expanding the opportunity for OEMs to deliver wireless innovation in personal computers, notebooks and netbooks with its BCM43142 InConcert combo chip. The new chip combines Wi-Fi Direct connectivity with seamless proximity-based pairing, dramatically simplifying wireless connectivity in the home. The combo chip supports a variety of platforms including next generation Windows® and Android-based systems.
The single-die BCM43142 is the industry's first 40nm Wi-Fi Bluetooth Combo Chip for notebooks and netbooks. It features power savings and coexistence improvements over earlier InConcert PC combo modules that Broadcom has been shipping since 2008. With its high levels of integration, the 40nm device also provides a significant reduction in footprint and a lower bill-of-materials and a 40 percent reduction in power consumption, providing a cost effective, compact and high-performance solution for the PC market.
The BCM43142 software development kit includes APIs for Bluetooth Low Energy (BLE), Bluetooth High Speed and 802.11n Wi-Fi Direct functionality. This allows devices to automatically recognize and communicate with each other directly, delivering innovative applications such as proximity-based PC security, router-less collaboration and instant photo/video sharing.
The BCM43142 and accompanying software applications will be demonstrated in Broadcom's Computex Booth.
While nearly all smart phones already include combo chips, a study by ABI Research finds that demand for single-die Bluetooth and Wi-Fi combo chips will continue to grow by 15 percent CAGR between 2009 and 2015. The ABI Research study also indicates that more than 75 percent of the combined notebooks and netbooks shipments in 2013 will have both Bluetooth and Wi-Fi. Broadcom now extends this capability to address Windows and Android-based PCs and notebooks and netbooks with its fourth generation Bluetooth-Wi-Fi combo chip.
The single-die BCM43142 is the industry's first 40nm Wi-Fi Bluetooth Combo Chip for notebooks and netbooks. It features power savings and coexistence improvements over earlier InConcert PC combo modules that Broadcom has been shipping since 2008. With its high levels of integration, the 40nm device also provides a significant reduction in footprint and a lower bill-of-materials and a 40 percent reduction in power consumption, providing a cost effective, compact and high-performance solution for the PC market.
The BCM43142 software development kit includes APIs for Bluetooth Low Energy (BLE), Bluetooth High Speed and 802.11n Wi-Fi Direct functionality. This allows devices to automatically recognize and communicate with each other directly, delivering innovative applications such as proximity-based PC security, router-less collaboration and instant photo/video sharing.
The BCM43142 and accompanying software applications will be demonstrated in Broadcom's Computex Booth.
While nearly all smart phones already include combo chips, a study by ABI Research finds that demand for single-die Bluetooth and Wi-Fi combo chips will continue to grow by 15 percent CAGR between 2009 and 2015. The ABI Research study also indicates that more than 75 percent of the combined notebooks and netbooks shipments in 2013 will have both Bluetooth and Wi-Fi. Broadcom now extends this capability to address Windows and Android-based PCs and notebooks and netbooks with its fourth generation Bluetooth-Wi-Fi combo chip.
Monday, May 30, 2011
austriamicrosystems announces aggressive plan to be 100 percent carbon neutral by 2015
UNTERPREMSTAETTEN, AUSTRIA: austriamicrosystems announced ambitious plans to reach full carbon neutrality by 2015 and become the first semiconductor manufacturer worldwide to do so.
In its aggressive, ongoing efforts to be environmentally responsible, austriamicrosystems has been actively reducing its carbon footprint since 2004, achieving a reduction of 50 percent of CO2 equivalents or 31,000 tons until 2010 since implementing actions. Over the last two years austriamicrosystems has completely mapped the CO2 generation of all company activities including its employees. In 2011, the company will further reduce CO2 emission equivalents by more than 9,000 tons by switching to 100% green electricity based mainly on water generated sources.
John Heugle, austriamicrosystems’ CEO, stated: “At austriamicrosystems we consistently review the impact of our business on the environment and take steps to reduce pollution on the planet. Focused on clean technology to reduce our CO2 impact, we are proud to announce that we are making significant progress towards the zero carbon footprint goal we have set for the company. Investments into energy savings, sustainable energy projects and CO2 reduction programs not only help our environment, but also provide significant economic advantages to us which create benefits to our customers. austriamicrosystems has taken a leadership role in this important effort and hopes other companies in the semiconductor industry will follow.”
As a world-class design and manufacturing organization, austriamicrosystems continuously invests in the efficient use of energy and natural resources for environmental excellence. Programs in operation or in development include thermo solar cooling, state-of-the-art cleaning of waste water and exhaust air, creating products for renewable energy applications, and biomass plant construction to enable the use of renewable fuel sources for heating and chilling requirements.
The implementation of these programs has already reduced the company’s use of coal and oil generated electricity and will soon free austriamicrosystems from dependency on imported natural gas as a key step towards the carbon neutrality target.
In its aggressive, ongoing efforts to be environmentally responsible, austriamicrosystems has been actively reducing its carbon footprint since 2004, achieving a reduction of 50 percent of CO2 equivalents or 31,000 tons until 2010 since implementing actions. Over the last two years austriamicrosystems has completely mapped the CO2 generation of all company activities including its employees. In 2011, the company will further reduce CO2 emission equivalents by more than 9,000 tons by switching to 100% green electricity based mainly on water generated sources.
John Heugle, austriamicrosystems’ CEO, stated: “At austriamicrosystems we consistently review the impact of our business on the environment and take steps to reduce pollution on the planet. Focused on clean technology to reduce our CO2 impact, we are proud to announce that we are making significant progress towards the zero carbon footprint goal we have set for the company. Investments into energy savings, sustainable energy projects and CO2 reduction programs not only help our environment, but also provide significant economic advantages to us which create benefits to our customers. austriamicrosystems has taken a leadership role in this important effort and hopes other companies in the semiconductor industry will follow.”
As a world-class design and manufacturing organization, austriamicrosystems continuously invests in the efficient use of energy and natural resources for environmental excellence. Programs in operation or in development include thermo solar cooling, state-of-the-art cleaning of waste water and exhaust air, creating products for renewable energy applications, and biomass plant construction to enable the use of renewable fuel sources for heating and chilling requirements.
The implementation of these programs has already reduced the company’s use of coal and oil generated electricity and will soon free austriamicrosystems from dependency on imported natural gas as a key step towards the carbon neutrality target.
Qualcomm's Snapdragon family gains momentum with leading OEMs across multiple OSs
TAIPEI, TAIWAN: Qualcomm Inc. will be demonstrating the latest Snapdragon-powered mobile computing devices, including tablets running Android 3.0, at COMPUTEX TAIPEI 2011, May 31-June 4.
Qualcomm's Snapdragon family of smart mobile processors has steadily gained traction across a diverse array of mobile operating systems, including Android, BlackBerry, Chrome, HP webOS, Windows Phone and the next version of Windows. Qualcomm's Snapdragon mobile processors currently power 125 announced smartphones and tablets, with another 250 designs in development, more than 40 of which are tablets.
"We are very pleased with the tremendous Snapdragon traction we have been getting with a variety of companies," said Luis Pineda, senior vice president of product management, computing and consumer products at Qualcomm. "We are showcasing some truly innovative products from HTC, HP, ASUS and many more OEMs that are leading the mobile computing industry."
"Qualcomm and HTC agree that a great mobile device starts with a great foundation," said Kouji Kodera, chief product officer of HTC. "We are proud of our Snapdragon devices, including our HTC Sensation and HTC EVO 3D powered by the MSM8660, which is coming soon, and our HTC Flyer powered by MSM8655, which is now available. We look forward to continuing with the next generation of Snapdragon when the MSM8960 samples in June."
"We are pleased to be showing our latest ASUS tablet designs running Android 3.0, also known as Honeycomb, here at COMPUTEX," said HC Hung, vice president of ASUS. "We chose Qualcomm Snapdragon mobile processors to power our tablets because of their ability to provide the optimal combination of processing performance, efficient power usage and wireless connectivity on a single platform."
Qualcomm has built Snapdragon mobile processors from the ground up to deliver the best mobile processing, graphics and connectivity, intelligently integrated to deliver the highest performance with the least power consumption. The Snapdragon MSM8x60 family of mobile processors is a leading solution for the latest multitasking tablets and smartphones, offering two asynchronous processor cores; an integrated Adreno 220 GPU with twice the processing power of its predecessor; and support for up to a 16 megapixel camera. The Snapdragon MSM8x55 family of processors substantially improves overall user experience, increases system performance and further extends battery life.
At COMPUTEX 2011, Qualcomm will showcase a broad array of smart mobile devices powered by Qualcomm's Snapdragon single- and dual-core processors, including tablets and smartphones from Acer, Anydata, Asus, Compal Communications, Compal Electronics, Foxconn, Foxlink, HTC, Lenovo, QISDA, Quanta and ZTE. Qualcomm will also demonstrate the Snapdragon MSM8660 MDP, which features asynchronous dual-core CPU performance and power savings; console-quality 3D gaming and UIs; and stereoscopic 3D and 1080P video capture, preview and playback.
Qualcomm's Snapdragon family of smart mobile processors has steadily gained traction across a diverse array of mobile operating systems, including Android, BlackBerry, Chrome, HP webOS, Windows Phone and the next version of Windows. Qualcomm's Snapdragon mobile processors currently power 125 announced smartphones and tablets, with another 250 designs in development, more than 40 of which are tablets.
"We are very pleased with the tremendous Snapdragon traction we have been getting with a variety of companies," said Luis Pineda, senior vice president of product management, computing and consumer products at Qualcomm. "We are showcasing some truly innovative products from HTC, HP, ASUS and many more OEMs that are leading the mobile computing industry."
"Qualcomm and HTC agree that a great mobile device starts with a great foundation," said Kouji Kodera, chief product officer of HTC. "We are proud of our Snapdragon devices, including our HTC Sensation and HTC EVO 3D powered by the MSM8660, which is coming soon, and our HTC Flyer powered by MSM8655, which is now available. We look forward to continuing with the next generation of Snapdragon when the MSM8960 samples in June."
"We are pleased to be showing our latest ASUS tablet designs running Android 3.0, also known as Honeycomb, here at COMPUTEX," said HC Hung, vice president of ASUS. "We chose Qualcomm Snapdragon mobile processors to power our tablets because of their ability to provide the optimal combination of processing performance, efficient power usage and wireless connectivity on a single platform."
Qualcomm has built Snapdragon mobile processors from the ground up to deliver the best mobile processing, graphics and connectivity, intelligently integrated to deliver the highest performance with the least power consumption. The Snapdragon MSM8x60 family of mobile processors is a leading solution for the latest multitasking tablets and smartphones, offering two asynchronous processor cores; an integrated Adreno 220 GPU with twice the processing power of its predecessor; and support for up to a 16 megapixel camera. The Snapdragon MSM8x55 family of processors substantially improves overall user experience, increases system performance and further extends battery life.
At COMPUTEX 2011, Qualcomm will showcase a broad array of smart mobile devices powered by Qualcomm's Snapdragon single- and dual-core processors, including tablets and smartphones from Acer, Anydata, Asus, Compal Communications, Compal Electronics, Foxconn, Foxlink, HTC, Lenovo, QISDA, Quanta and ZTE. Qualcomm will also demonstrate the Snapdragon MSM8660 MDP, which features asynchronous dual-core CPU performance and power savings; console-quality 3D gaming and UIs; and stereoscopic 3D and 1080P video capture, preview and playback.
Saturday, May 28, 2011
Synopsys replenishes stock repurchase authorization to $500 million
MOUNTAIN VIEW, USA: Synopsys Inc. announced that its board of directors has replenished its stock repurchase authorization. Under the replenished program, the company may repurchase Synopsys common stock with a market value up to $500 million.
"During the last four quarters, we have repurchased more than 14.5 million shares of Synopsys stock," said Brian Beattie, chief financial officer of Synopsys. "Replenishing the authorization demonstrates our board's confidence in the long-term growth of our business."
Purchases may be made beginning immediately and ending at such time as the authorized funds are spent or the program is discontinued. The program does not obligate Synopsys to acquire any particular amount of common stock, and the program may be modified or suspended at any time at Synopsys' discretion.
"During the last four quarters, we have repurchased more than 14.5 million shares of Synopsys stock," said Brian Beattie, chief financial officer of Synopsys. "Replenishing the authorization demonstrates our board's confidence in the long-term growth of our business."
Purchases may be made beginning immediately and ending at such time as the authorized funds are spent or the program is discontinued. The program does not obligate Synopsys to acquire any particular amount of common stock, and the program may be modified or suspended at any time at Synopsys' discretion.
Magma reports revenue of $139.3 million for fiscal 2011
SAN JOSE, USA: Magma Design Automation Inc., a provider of chip design software, reported revenue of $38 million for its fourth quarter and $139.3 million for its 2011 fiscal year, both ended May 1, 2011.
"The fourth quarter continued a string of solid financial performance and capped off a great fiscal 2011, as for the ninth consecutive quarter we met or exceeded all guidance targets and generated cash," said Rajeev Madhavan, Magma chairman and chief executive officer.
"Bookings were up strongly and exceeded the high end of our guidance range as the semiconductor industry's push to 28-nanometer and smaller designs created opportunity for Magma's entire product line. Our core digital platform Talus gained traction, benefitting from the recently announced Talus Vortex 1.2 and Talus Vortex FX. In analog implementation, Titan added five new logos and now has a total of 25 customers, primarily added during fiscal 2011. The FineSim circuit simulation products had another year of great growth as they continued to replace legacy simulators. And our partnership with Applied Materials generated a lot of excitement for our yield management products and created new opportunities for growth by that product group."
GAAP results
In accordance with generally accepted accounting principles (GAAP), Magma reported net income of $1.7 million, or $0.03 per share (basic) and $0.02 per share (diluted), for the fourth quarter, compared to a net loss of $(0.7) million, or $(0.01) per share (basic and diluted), for the year-ago fourth quarter. For fiscal 2011 Magma reported a GAAP net loss of $(3.3) million, or $(0.05) per share (basic and diluted), compared to a net loss of $(3.3) million, or $(0.07) per share (basic and diluted), for fiscal 2010.
Non-GAAP results
Magma's non-GAAP net income was $6.1 million for the quarter, or $0.09 per share (basic and diluted), compared to non-GAAP net income of $3.7 million, or $0.07 per share (basic) and $0.06 per share (diluted), for the year-ago fourth quarter. For fiscal 2011 Magma's non-GAAP net income was $18.8 million, or $0.31 per share (basic) and $0.28 per share (diluted), compared to non-GAAP net income of $9.1 million, or $0.18 per share (basic) and $0.17 (diluted), for the year-ago fiscal year.
Non-GAAP net income for the fourth quarter and full fiscal year of 2011 excludes the effects of amortization of developed technology, amortization of intangible assets, stock-based compensation, amortization of debt issuance costs and debt premium accretion, charges associated with equity and other investments, restructuring charges and the related provision for income taxes. Non-GAAP net income for the fourth quarter and full fiscal year of 2010 excludes the effects of amortization of developed technology, amortization of intangible assets, stock-based compensation, amortization of debt issuance costs and debt discount/premium accretion, charges associated with equity and other investments, restructuring charges and the related provision for income taxes.
"The fourth quarter continued a string of solid financial performance and capped off a great fiscal 2011, as for the ninth consecutive quarter we met or exceeded all guidance targets and generated cash," said Rajeev Madhavan, Magma chairman and chief executive officer.
"Bookings were up strongly and exceeded the high end of our guidance range as the semiconductor industry's push to 28-nanometer and smaller designs created opportunity for Magma's entire product line. Our core digital platform Talus gained traction, benefitting from the recently announced Talus Vortex 1.2 and Talus Vortex FX. In analog implementation, Titan added five new logos and now has a total of 25 customers, primarily added during fiscal 2011. The FineSim circuit simulation products had another year of great growth as they continued to replace legacy simulators. And our partnership with Applied Materials generated a lot of excitement for our yield management products and created new opportunities for growth by that product group."
GAAP results
In accordance with generally accepted accounting principles (GAAP), Magma reported net income of $1.7 million, or $0.03 per share (basic) and $0.02 per share (diluted), for the fourth quarter, compared to a net loss of $(0.7) million, or $(0.01) per share (basic and diluted), for the year-ago fourth quarter. For fiscal 2011 Magma reported a GAAP net loss of $(3.3) million, or $(0.05) per share (basic and diluted), compared to a net loss of $(3.3) million, or $(0.07) per share (basic and diluted), for fiscal 2010.
Non-GAAP results
Magma's non-GAAP net income was $6.1 million for the quarter, or $0.09 per share (basic and diluted), compared to non-GAAP net income of $3.7 million, or $0.07 per share (basic) and $0.06 per share (diluted), for the year-ago fourth quarter. For fiscal 2011 Magma's non-GAAP net income was $18.8 million, or $0.31 per share (basic) and $0.28 per share (diluted), compared to non-GAAP net income of $9.1 million, or $0.18 per share (basic) and $0.17 (diluted), for the year-ago fiscal year.
Non-GAAP net income for the fourth quarter and full fiscal year of 2011 excludes the effects of amortization of developed technology, amortization of intangible assets, stock-based compensation, amortization of debt issuance costs and debt premium accretion, charges associated with equity and other investments, restructuring charges and the related provision for income taxes. Non-GAAP net income for the fourth quarter and full fiscal year of 2010 excludes the effects of amortization of developed technology, amortization of intangible assets, stock-based compensation, amortization of debt issuance costs and debt discount/premium accretion, charges associated with equity and other investments, restructuring charges and the related provision for income taxes.
Friday, May 27, 2011
DRAM module market to grow almost 11 percent this year, repeating successful 2010
EL SEGUNDO, USA: The market for dynamic random access memory (DRAM) modules, enjoying a spillover in success from a banner 2010, is headed for yet another year of double-digit growth in 2011 as DRAM module shipments bound up 10.8 percent, according to new research from IHS iSuppli.
Shipments of DRAM modules—packages containing DRAM chips for use in PCs and other electronic products—are projected to reach 812.8 million units in 2011, up from 733.2 million last year. Growth in 2011 for DRAM modules will be slightly down from the 14.6 percent expansion last year, but it will be ahead of the market’s performance during the next four years, as shown by the figure.
Source: IHS iSuppli, USA.
“With the worst of the recession behind, DRAM module makers have played their hand expertly during the strengthening global economic recovery, coinciding with strong DRAM chip and module prices,” said Clifford Leimbach, analyst for memory demand forecasting at IHS. “And despite continual shocks throughout many industries last year, DRAM module shipments have not stopped growing.”
In particular, consumers are becoming more comfortable in replacing old PCs or upgrading current models, prompting growth of the DRAM module market, Leimbach noted.
This year a full 63 percent of DRAM modules, equivalent to 510.4 million units, will be from original equipment manufacturers such as Samsung Electronics Co. Ltd.—entities that not only make DRAM modules for use in their own products but also sell to other computer manufacturers.
The second largest group, accounting for 19 percent or 155 million units, will be white-box DRAM modules from third-party suppliers that sell to companies like Dell Inc., which then integrates the memory packages into its computers and other products.
The remaining 18 percent of the DRAM module market in 2011, equivalent to 147.3 million units, will come in the form of upgrade modules, sold by third-party suppliers into the retail channel.
When added together, both white-box and upgrade modules constitute the third-party DRAM module market, valued at $10.6 billion in 2010. The biggest third-party DRAM module maker last year was Kingston Technology, which enjoyed revenue of $4.9 billion—nearly half of the entire third-party market.
Among all channels, double data rate 3 (DDR3) remains the dominant technology, Leimbach observed. While the older and slower DDR2 ruled the module landscape from 2006 to 2009, DDR3 now has taken over and likely will remain at the top for a longer period of time lasting about five years. The next-generation DDR4, whose standards have not been finalized, is expected to become the major DRAM module density in the second quarter of 2015.
DRAM content in PCs to rise
Although average DRAM content in PCs has been steadily on the rise, strong pricing in mid-2010 resulted in a rare decline in DRAM megabytes for computers. But despite the slight drop in overall PC DRAM content, average module content still rose and avoided a fall.
In a hypothetical example, PCs in an earlier period might have shipped out with 4 gigabytes (GB) of DRAM configured as 4 modules of 1 GB each, while a later period might have seen the same PCs shipping out with 2 GB of DRAM configured as a single module. In such an example, PC DRAM usage decreased but average module DRAM grew. As a result, annualized growth in 2010 of PC DRAM content was down to 24 percent—a low number when considered against the historic yearly expansion of DRAM in the 30 percent range.
With ASPs continuing to decline, however, DRAM densities are projected to climb in the next five years including 2011. Such a development would represent good news not only for module manufacturers hoping to see greater growth, but also for consumers standing to reap benefits from increased DRAM densities at lower prices, said Leimbach.
This year alone will see a 30 percent increase in average DRAM content for PCs, to be followed by a 36 percent growth in 2012. Average DRAM content this year is expected to rise steadily every quarter, mounting from 3.7 GB in the first quarter to 4.69 GB in the fourth. Next year, DRAM density in PCs will start on average at the 5-GB level.
Source: IHS iSuppli, USA.
Shipments of DRAM modules—packages containing DRAM chips for use in PCs and other electronic products—are projected to reach 812.8 million units in 2011, up from 733.2 million last year. Growth in 2011 for DRAM modules will be slightly down from the 14.6 percent expansion last year, but it will be ahead of the market’s performance during the next four years, as shown by the figure.
Source: IHS iSuppli, USA.“With the worst of the recession behind, DRAM module makers have played their hand expertly during the strengthening global economic recovery, coinciding with strong DRAM chip and module prices,” said Clifford Leimbach, analyst for memory demand forecasting at IHS. “And despite continual shocks throughout many industries last year, DRAM module shipments have not stopped growing.”
In particular, consumers are becoming more comfortable in replacing old PCs or upgrading current models, prompting growth of the DRAM module market, Leimbach noted.
This year a full 63 percent of DRAM modules, equivalent to 510.4 million units, will be from original equipment manufacturers such as Samsung Electronics Co. Ltd.—entities that not only make DRAM modules for use in their own products but also sell to other computer manufacturers.
The second largest group, accounting for 19 percent or 155 million units, will be white-box DRAM modules from third-party suppliers that sell to companies like Dell Inc., which then integrates the memory packages into its computers and other products.
The remaining 18 percent of the DRAM module market in 2011, equivalent to 147.3 million units, will come in the form of upgrade modules, sold by third-party suppliers into the retail channel.
When added together, both white-box and upgrade modules constitute the third-party DRAM module market, valued at $10.6 billion in 2010. The biggest third-party DRAM module maker last year was Kingston Technology, which enjoyed revenue of $4.9 billion—nearly half of the entire third-party market.
Among all channels, double data rate 3 (DDR3) remains the dominant technology, Leimbach observed. While the older and slower DDR2 ruled the module landscape from 2006 to 2009, DDR3 now has taken over and likely will remain at the top for a longer period of time lasting about five years. The next-generation DDR4, whose standards have not been finalized, is expected to become the major DRAM module density in the second quarter of 2015.
DRAM content in PCs to rise
Although average DRAM content in PCs has been steadily on the rise, strong pricing in mid-2010 resulted in a rare decline in DRAM megabytes for computers. But despite the slight drop in overall PC DRAM content, average module content still rose and avoided a fall.
In a hypothetical example, PCs in an earlier period might have shipped out with 4 gigabytes (GB) of DRAM configured as 4 modules of 1 GB each, while a later period might have seen the same PCs shipping out with 2 GB of DRAM configured as a single module. In such an example, PC DRAM usage decreased but average module DRAM grew. As a result, annualized growth in 2010 of PC DRAM content was down to 24 percent—a low number when considered against the historic yearly expansion of DRAM in the 30 percent range.
With ASPs continuing to decline, however, DRAM densities are projected to climb in the next five years including 2011. Such a development would represent good news not only for module manufacturers hoping to see greater growth, but also for consumers standing to reap benefits from increased DRAM densities at lower prices, said Leimbach.
This year alone will see a 30 percent increase in average DRAM content for PCs, to be followed by a 36 percent growth in 2012. Average DRAM content this year is expected to rise steadily every quarter, mounting from 3.7 GB in the first quarter to 4.69 GB in the fourth. Next year, DRAM density in PCs will start on average at the 5-GB level.
Source: IHS iSuppli, USA.
AppliedMicro launches industry's first 100G fully-integrated CMOS ICs for next-gen optical modules
SUNNYVALE, USA: Applied Micro Circuits Corp. or AppliedMicro announced S28010 Gearbox integrated circuit devices for 100 Gigabit Ethernet CFP client optical interfaces. As the industry’s first single-chip CMOS offering, the S28010 enables cost-effective, power-efficient 100GBASE-R4 optical modules to expand connection speeds from 10Gbps to 100Gbps for high-end switching and routing equipment.
AppliedMicro’s Gearbox translates a 10-lane, 10Gbps CAUI electrical interface to 4-lanes operating at 25Gbps and represents the company’s first product in a family of 100G ICs for the client market.
“There is a genuine need for cost-effective, power-efficient Gearbox semiconductors to enable 100-Gigabit-per-second Ethernet and OTU-4 client interfaces,” said George Jones, AppliedMicro's VP of Marketing and Business Development. “Deployment of CFP modules in enterprise and core router applications has been limited by inadequate supply. This new product from AppliedMicro will enable service providers to meet the bandwidth requirements that customers demand.”
The S28010 covers a broad frequency range up to 28.1Gbps for applications including 100G Ethernet, Fibre Channel, Infiniband and OTU-4 optical transport. It is also the first CMOS device to comply with IEEE802.3ba and CFP MSA standards.
“Telecom, datacom and cloud provider industries are all asking for 100 Gigabit Ethernet links. Just the 100G optical transport line card market alone will exceed $3 billion by 2016,” said Karen Liu, Principal Analyst, Components at Ovum. “At this high speed, the widely needed 10 km interface has been challenging in terms of cost, size and power consumption. AppliedMicro’s Gearbox IC is designed to address all three factors.”
The S28010 is designed to break barriers of high power, high cost and low reliability in the CFP market by enabling volume deployments of 100G modules in high-end switching and routing applications by providing key advantages:
* Fully-integrated single-chip solution reduces module bill of materials and allows module vendors to meet the CFP module MSA specification.
* Lowest power – Power consumption below 4 Watts is less than 50 percent of comparable 2-chip BiCMOS solutions and results in reduced system heat and lower operational costs.
* First-to-market – Module developers seeking scalable products can finally move to an integrated CMOS solution.
AppliedMicro’s Gearbox device offers the highest level of integration including MDIO and I2C support and extensive diagnostic features, including loopback. Sample availability is scheduled for September.
AppliedMicro’s Gearbox translates a 10-lane, 10Gbps CAUI electrical interface to 4-lanes operating at 25Gbps and represents the company’s first product in a family of 100G ICs for the client market.
“There is a genuine need for cost-effective, power-efficient Gearbox semiconductors to enable 100-Gigabit-per-second Ethernet and OTU-4 client interfaces,” said George Jones, AppliedMicro's VP of Marketing and Business Development. “Deployment of CFP modules in enterprise and core router applications has been limited by inadequate supply. This new product from AppliedMicro will enable service providers to meet the bandwidth requirements that customers demand.”
The S28010 covers a broad frequency range up to 28.1Gbps for applications including 100G Ethernet, Fibre Channel, Infiniband and OTU-4 optical transport. It is also the first CMOS device to comply with IEEE802.3ba and CFP MSA standards.
“Telecom, datacom and cloud provider industries are all asking for 100 Gigabit Ethernet links. Just the 100G optical transport line card market alone will exceed $3 billion by 2016,” said Karen Liu, Principal Analyst, Components at Ovum. “At this high speed, the widely needed 10 km interface has been challenging in terms of cost, size and power consumption. AppliedMicro’s Gearbox IC is designed to address all three factors.”
The S28010 is designed to break barriers of high power, high cost and low reliability in the CFP market by enabling volume deployments of 100G modules in high-end switching and routing applications by providing key advantages:
* Fully-integrated single-chip solution reduces module bill of materials and allows module vendors to meet the CFP module MSA specification.
* Lowest power – Power consumption below 4 Watts is less than 50 percent of comparable 2-chip BiCMOS solutions and results in reduced system heat and lower operational costs.
* First-to-market – Module developers seeking scalable products can finally move to an integrated CMOS solution.
AppliedMicro’s Gearbox device offers the highest level of integration including MDIO and I2C support and extensive diagnostic features, including loopback. Sample availability is scheduled for September.
Mentor Graphics reports fiscal Q1 results
WILSONVILLE, USA: Mentor Graphics Corp. announced financial results for the company’s fiscal first quarter ended April 30, 2011. The company reported revenues of $230 million, non-GAAP earnings per share of $.20, and a GAAP loss per share of $.02. The GAAP loss was driven primarily by non-cash charges associated with retirement of convertible debt.
“Our strategy of leveraging our strength in design automation into adjacent markets is working,” said Walden C. Rhines, chairman and CEO of Mentor Graphics. “The company reported record revenues for a first quarter as our New and Emerging product category delivered strong growth. In addition, our Integrated Systems Design product category continued to strengthen with year-on-year bookings up 45 percent. Leading indicators of the business remain strong with services and new customers both up sharply.”
During the quarter, the company refinanced a convertible debt offering, reducing annual cash interest expense, increasing conversion price, and reducing dilution. The company also announced a new four-year $125 million revolving credit facility. During the quarter, the company unveiled its 3D integrated circuit (IC) strategy and released test products designed to support 3D IC. The company extended its Calibre product line with the Calibre RealTime platform which allows IC designers to optimize their designs while immediately verifying the manufacturability of the chip. The Mentor Embedded Sourcery CodeBench won best software product of the show at the recent Embedded Systems Conference.
“We are well on track to achieve our full year goal of a non-GAAP operating margin of 15% of revenues,” said Gregory K. Hinckley, president of Mentor Graphics. “Looking forward, we will extend our cost-cutting efforts with further consolidations of facilities and IT, while we continue to raise the bar on commission and variable compensation expense to further align rewards with increasing shareholder value.”
Outlook
For the second quarter, the company expects revenues of about $210 million, non-GAAP earnings per share of about $.05, and a GAAP loss per share of approximately $.05. For the full year, the company now expects revenues of about $1,004 million, non-GAAP earnings per share of approximately $1.01 and GAAP earnings per share of about $.67.
“Our strategy of leveraging our strength in design automation into adjacent markets is working,” said Walden C. Rhines, chairman and CEO of Mentor Graphics. “The company reported record revenues for a first quarter as our New and Emerging product category delivered strong growth. In addition, our Integrated Systems Design product category continued to strengthen with year-on-year bookings up 45 percent. Leading indicators of the business remain strong with services and new customers both up sharply.”
During the quarter, the company refinanced a convertible debt offering, reducing annual cash interest expense, increasing conversion price, and reducing dilution. The company also announced a new four-year $125 million revolving credit facility. During the quarter, the company unveiled its 3D integrated circuit (IC) strategy and released test products designed to support 3D IC. The company extended its Calibre product line with the Calibre RealTime platform which allows IC designers to optimize their designs while immediately verifying the manufacturability of the chip. The Mentor Embedded Sourcery CodeBench won best software product of the show at the recent Embedded Systems Conference.
“We are well on track to achieve our full year goal of a non-GAAP operating margin of 15% of revenues,” said Gregory K. Hinckley, president of Mentor Graphics. “Looking forward, we will extend our cost-cutting efforts with further consolidations of facilities and IT, while we continue to raise the bar on commission and variable compensation expense to further align rewards with increasing shareholder value.”
Outlook
For the second quarter, the company expects revenues of about $210 million, non-GAAP earnings per share of about $.05, and a GAAP loss per share of approximately $.05. For the full year, the company now expects revenues of about $1,004 million, non-GAAP earnings per share of approximately $1.01 and GAAP earnings per share of about $.67.
Open-Silicon intros "On Time, or On Us" program
MILPITAS, USA: Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, has introduced the semiconductor industry's first money-backed design engineering schedules. Open-Silicon will meet the schedule, delivering a prototype on time, or the company will refund the cost of the design engineering, up to $500K.
In order to meet time-to-market goals and realize an integrated circuit's (IC) true market potential, execution to schedule is paramount. The semiconductor industry, however, does not have a good track record of delivering products on time, resulting in missed revenue. Open-Silicon has focused on meeting schedules since its first chip and continues to be held accountable at every board of directors' meeting. While the company has always considered schedule predictability extremely important, the company is now willing to sign up on qualifying programs that the engineering will be "On Time, or On Us."
"The semiconductor industry needs schedule predictability to be viewed with the same intense focus as design functionality. Open-Silicon's bold statement with "On Time, or On Us" is a call to customers and partners to address schedule predictability as the key concern for the coming decade," said Dr. Naveed Sherwani, CEO of Open-Silicon. "We founded Open-Silicon on this principle, and are now again taking a leadership position by putting our money behind it."
"On Time, or On Us" offer details
The "On Time, or On Us" offer is valid on qualifying designs in 40nm or 65nm process, where design schedules are still relatively long and where Open-Silicon has a well-matured design methodology. Under the terms of this program, the originally quoted design non-recurring engineering (DNRE) charge will be refunded, up to $500K, for programs that miss the committed development schedule for prototype delivery. This program will run through December 2011.
In order to meet time-to-market goals and realize an integrated circuit's (IC) true market potential, execution to schedule is paramount. The semiconductor industry, however, does not have a good track record of delivering products on time, resulting in missed revenue. Open-Silicon has focused on meeting schedules since its first chip and continues to be held accountable at every board of directors' meeting. While the company has always considered schedule predictability extremely important, the company is now willing to sign up on qualifying programs that the engineering will be "On Time, or On Us."
"The semiconductor industry needs schedule predictability to be viewed with the same intense focus as design functionality. Open-Silicon's bold statement with "On Time, or On Us" is a call to customers and partners to address schedule predictability as the key concern for the coming decade," said Dr. Naveed Sherwani, CEO of Open-Silicon. "We founded Open-Silicon on this principle, and are now again taking a leadership position by putting our money behind it."
"On Time, or On Us" offer details
The "On Time, or On Us" offer is valid on qualifying designs in 40nm or 65nm process, where design schedules are still relatively long and where Open-Silicon has a well-matured design methodology. Under the terms of this program, the originally quoted design non-recurring engineering (DNRE) charge will be refunded, up to $500K, for programs that miss the committed development schedule for prototype delivery. This program will run through December 2011.
NFC enables secure mobile transactions for Google Wallet
SINGAPORE: NXP Semiconductors N.V. announced that its world leading near field communication (NFC) technology enables the newly announced Google Wallet. NXP joins partners Google, Citibank, MasterCard, First Data, and Sprint, along with other market leaders, in New York to unveil Google Wallet, an open platform enabling mobile transactions.
With NXP’s secure contactless NFC solution, consumers can simply wave their phones over intelligent surfaces to pay for goods, apply a discount coupon, or receive loyalty points. Google Wallet allows consumers to replace a multitude of physical cards typically carried in wallets with a NFC enabled phone delivering convenience, personal interactivity and security for many different types of transactions.
NXP provides the complete embedded, secure NFC solution for Google Wallet and was instrumental in building this new application with Google. The NXP PN65 NFC mobile transaction solution incorporates the NFC radio controller, the embedded secure element and NFC software in a single device. The embedded secure element enables the payment part of Google Wallet, and uses advanced cryptography to offer a high level of security for mobile transactions.
NXP’s security technology has seen extensive global deployment with over 1 billion units of secure elements shipped to support mobile payment and bank cards, access management schemes, mass transit infrastructures, device authentication and eGovernment solutions such as ePassports, driver licenses, national ID and health cards.
“This latest move by Google is truly unleashing the full potential of NFC,” said Ruediger Stroh, executive vice president and general manager, Identification Business, NXP Semiconductors.
“NXP’s NFC technology essentially converts smart phones into loyalty cards, single-tap location “check in” devices, concert tickets, coupon carriers, contactless payment devices, transit tickets, and secure keys to access cars, hotel rooms, buildings, and computers – the possibilities are endless. Our technology greatly enhances the mobile user experience from the secure NFC solutions embedded in smartphones and POS terminals, to the NFC tags embedded in smart posters. Our leadership in NFC is supported by our deep understanding of the market, our broad portfolio of patents; and our security, performance and best-in-class transaction times.”
NFC is a market proven technology co-invented by NXP in 2002. In 2004, NXP co-founded the NFC Forum to lead the collaboration with all industry stakeholders and help standardize the technology. NFC technology evolved from a combination of contactless identification (RFID) and interconnection technologies. Ranked as the number one contactless IC vendor by ABI Research for three years in a row, NXP is the global leader in NFC solutions, field proven in over 150 NFC trials and landmark commercial deployments worldwide.
With NXP’s secure contactless NFC solution, consumers can simply wave their phones over intelligent surfaces to pay for goods, apply a discount coupon, or receive loyalty points. Google Wallet allows consumers to replace a multitude of physical cards typically carried in wallets with a NFC enabled phone delivering convenience, personal interactivity and security for many different types of transactions.
NXP provides the complete embedded, secure NFC solution for Google Wallet and was instrumental in building this new application with Google. The NXP PN65 NFC mobile transaction solution incorporates the NFC radio controller, the embedded secure element and NFC software in a single device. The embedded secure element enables the payment part of Google Wallet, and uses advanced cryptography to offer a high level of security for mobile transactions.
NXP’s security technology has seen extensive global deployment with over 1 billion units of secure elements shipped to support mobile payment and bank cards, access management schemes, mass transit infrastructures, device authentication and eGovernment solutions such as ePassports, driver licenses, national ID and health cards.
“This latest move by Google is truly unleashing the full potential of NFC,” said Ruediger Stroh, executive vice president and general manager, Identification Business, NXP Semiconductors.
“NXP’s NFC technology essentially converts smart phones into loyalty cards, single-tap location “check in” devices, concert tickets, coupon carriers, contactless payment devices, transit tickets, and secure keys to access cars, hotel rooms, buildings, and computers – the possibilities are endless. Our technology greatly enhances the mobile user experience from the secure NFC solutions embedded in smartphones and POS terminals, to the NFC tags embedded in smart posters. Our leadership in NFC is supported by our deep understanding of the market, our broad portfolio of patents; and our security, performance and best-in-class transaction times.”
NFC is a market proven technology co-invented by NXP in 2002. In 2004, NXP co-founded the NFC Forum to lead the collaboration with all industry stakeholders and help standardize the technology. NFC technology evolved from a combination of contactless identification (RFID) and interconnection technologies. Ranked as the number one contactless IC vendor by ABI Research for three years in a row, NXP is the global leader in NFC solutions, field proven in over 150 NFC trials and landmark commercial deployments worldwide.
Cadence US patents top 1,000
SAN JOSE, USA: Cadence Design Systems Inc. has received its 1000th US patent, carrying forward a tradition of innovation that began with the formation of the company in 1988. The company holds in excess of 1,200 patents worldwide. As one of the world’s leading EDA companies, Cadence leverages exceptional internal engineering prowess and exploits the brain trust of some of the industry’s most innovative companies through acquisitions to pioneer game-changing approaches.
“As the patent leader in the EDA market, Cadence embodies an inventive spirit that has led to many advancements in semiconductor and system design,” said Lip-Bu Tan, president and chief executive officer at Cadence. “This inventive spirit enables us to deliver on the EDA360 vision outlined last year, which advocates an application-driven approach to electronics design. We constantly challenge the industry and ourselves to think outside the box, and our patent history proves our ability to rise to the challenge.”
In many cases, Cadence patents have formed the foundation for design practices that have been adopted by the EDA industry as a whole to overcome some of the industry’s most complex design challenges. Cadence holds key patents in the areas of formal verification, analog and mixed-signal simulation, custom design environments and more.
“As the patent leader in the EDA market, Cadence embodies an inventive spirit that has led to many advancements in semiconductor and system design,” said Lip-Bu Tan, president and chief executive officer at Cadence. “This inventive spirit enables us to deliver on the EDA360 vision outlined last year, which advocates an application-driven approach to electronics design. We constantly challenge the industry and ourselves to think outside the box, and our patent history proves our ability to rise to the challenge.”
In many cases, Cadence patents have formed the foundation for design practices that have been adopted by the EDA industry as a whole to overcome some of the industry’s most complex design challenges. Cadence holds key patents in the areas of formal verification, analog and mixed-signal simulation, custom design environments and more.
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