STARC adopts Calypto’s PowerPro MG in STARCAD-CEL v4.0 design flow

SANTA CLARA, USA & SHIN-YOKOHAMA, JAPAN: Calypto Design Systems Inc., a leader in sequential analysis technology, announced that the Semiconductor Technology Academic Research Center (STARC) has adopted Calypto’s PowerPro MG product for their STARCAD-CEL Version 4.0 design flow.

STARC is a research consortium co-founded by major Japanese semiconductor companies. PowerPro MG automatically reduces both dynamic and leakage memory power in SoCs, and STARC made the decision after completing an extensive evaluation of the tool.

“Designers face significant pressure to reduce power in their designs, and until now, they have not had access to tools that can reduce memory power without requiring extensive, time-consuming analysis and error-prone manual modifications to the design,” said Nobuyuki Nishiguchi, Vice President, General Manager, Development Department-1 at STARC.

“PowerPro MG surpassed our initial goal to reduce dynamic memory power by 10 percent, delivering a reduction of over 40 percent. It is a tool that companies need to deliver the lowest power SoCs possible.”

PowerPro MG also delivered over 60 percent memory leakage power reduction by using a low leakage power mode called light sleep, which is enabled using a single pin. In both cases, SLEC Pro was then used to verify comprehensive equivalence between the original RTL design and the PowerPro MG-optimized RTL design.

“With memory power accounting for up to 70 percent of SoC power, PowerPro MG fills a critical gap in today’s power optimization methodolgies for SoC design,” says Eiki Suzuki, President of Calypto KK. “The STARC results demonstrate that PowerPro MG dramatically improves the ability of designers to create the most competitive, low-power devices possible.”