HENDERSON, USA: Aldec Inc., a leader in RTL Simulation and EDA, announced its latest Design Rule Checking application, ALINT 2010.02.
The release adds support for Reuse Methodology Manual (RMM) design rules that define a methodology for efficient reuse and verification of System-On-A-Chip (SoC) designs. Altera and Xilinx FPGA vendor primitives are now supported to enable accurate design rule checking on the latest FPGA devices.
ALINT is Design Rule Checking software for fast design closure. The software analyzes and detects issues early in the design and verification cycle of complex ASIC, FPGA and SoC designs.
The latest release includes advanced technology enabling detection of all the levels of RTL design issues – starting from comparatively simple naming conventions and design structure to advanced topics such as reuse, optimal synthesis, power and area consumption, Design-For-Test (DFT), and Clock Domain Crossings (CDC).
ALINT 2010.02 is available today and sold directly from Aldec and its authorized worldwide distributors. The product offers support for RMM, STARC, DO-254 and Aldec design rule plug-ins, which are sold separately.