SWITZERLAND: STMicroelectronics announced it has shipped three billion MEMS sensors to date—laid side by side, these chips would exceed the height of Mt Everest.
The achievement reconfirms ST’s position as the clear leader in MEMS (Micro-Electro-Mechanical Systems) devices for consumer and portable applications.
According to information and analytics firm IHS, ST’s total MEMS and sensor sales grew more than 19 percent in 2012, reaching a total of approximately $800 million. In the largest of these markets, motion sensors in mobile handsets and tablets, ST’s MEMS sales accounted for 48 percent of the market, well more than twice as large as that of its closest competitor, according to IHS.
“Our research shows that, in the mobile market, ST is the number one MEMS supplier across all of the important mobile handset operating systems,” said Jeremie Bouchaud, director and senior principal analyst for MEMS and sensors at IHS. “Even in the highly competitive Android market, ST has nearly twice the market share of its nearest competitor.”
ST’s MEMS sensors have enabled motion-activated user interfaces in many different popular consumer devices, including most of the leading smart phones, tablets, personal media players, game consoles, digital still cameras and remotes, making these more accessible and appealing to people.
ST’s MEMS devices are also widely used for free-fall protection in laptop hard-disk drives, in many health and fitness products, and for car infotainment and enhanced navigation. Today, they are being designed into new applications as varied as providing the crispest, clearest audio in mobile communications and adding localized weather/environmental monitoring capabilities to consumers’ mobile devices.
“Sensors play a crucial role in the evolving wireless world, in enabling the intuitive gesture-based control that is increasingly expected as the norm and in paving the way for new services and user experiences,” said Benedetto Vigna, ST executive VP and GM of the Analog, MEMS & Sensors Group. “From sensors to secure communications, from power management to display driving and projection, ST solutions are enabling wave after wave of innovation in the wireless world that is changing the lives of people everywhere.”
Thursday, January 31, 2013
Daou InCube to offer design platforms based on Cortus processors
FRANCE & KOREA: Cortus, a technology leader in cost effective, silicon efficient, 32-bit processor IP, and SoC solution provider Daou InCube, are teaming up to offer platforms and design services based on Cortus 32-bit processor cores.
Cortus S.A. licenses a range of 32-bit processor cores for embedded systems. The cores provide licensees with a scalable choice in embedded computational performance and silicon area to meet a wide variety of application needs.
“Today’s applications demand small silicon footprints and energy efficiency” says Kenny Seo, VP Semiconductor Business Unit of Daou InCube, “The Cortus 32-bit processors and peripherals give us the ideal starting point for creating design platforms”. He explains, “These platforms add to our existing portfolio of front-end design, back-end design, test and packaging services”.
“By working with Daou InCube we are pleased to offer a well-rounded design platform solution to Korean customers”, says Michael Chapman, CEO and president of Cortus, “Daou InCube has strong capabilities from design specification through to tested integrated circuits”.
The Cortus family of APS processors starts with the world’s smallest 32-bit core, the APS1, and goes up to the floating point FPS6. All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use. Ports of various RTOSs are available.
Cortus S.A. licenses a range of 32-bit processor cores for embedded systems. The cores provide licensees with a scalable choice in embedded computational performance and silicon area to meet a wide variety of application needs.
“Today’s applications demand small silicon footprints and energy efficiency” says Kenny Seo, VP Semiconductor Business Unit of Daou InCube, “The Cortus 32-bit processors and peripherals give us the ideal starting point for creating design platforms”. He explains, “These platforms add to our existing portfolio of front-end design, back-end design, test and packaging services”.
“By working with Daou InCube we are pleased to offer a well-rounded design platform solution to Korean customers”, says Michael Chapman, CEO and president of Cortus, “Daou InCube has strong capabilities from design specification through to tested integrated circuits”.
The Cortus family of APS processors starts with the world’s smallest 32-bit core, the APS1, and goes up to the floating point FPS6. All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use. Ports of various RTOSs are available.
Dreamchip announces plan for India's own processor based tablet SoC
INDIA: In perhaps a first for any Indian company so far, Dreamchip Electronics Pvt Ltd, a fabless semiconductor company founded in 2012, has announced plans for launching SoCs for tablet computers.
The SoCs come in three different variants named Siddhi, Vani and Sandesh. Each one of these has been specified and optimized for a distinct tablet application. Dreamchip will use a proprietary multi-core 32-bit RISC and DSP processor architecture and a unique optimized direct connect architecture for powering these SoCs.
Siddhi is designed to power basic student's book reader tablets that are optimized for low cost large volume applications. Siddhi powered tablets are expected to replace printed text books. Vani is targeted towards advanced student's multi-media tablets that offer a rich multi-media experience for students. Sandesh the high-end SoC is optimized for use in citizen-centric e-governance and e-commerce tablets.
All of the SoCs are designed to help Indian EMCs cater to the needs of rural as well as value conscious urban users and will be accompanied by reference tablet designs and embedded software with the option to support different Indian languages.
Solutions from Dreamchip are expected to play a critical role by enabling EMCs to create world class tablet computers and offer them to customers in India and the rest of the world at competitive rates. All the SoCs are expected to be priced in Indian Rupees for the Indian market thereby eliminating risk from exchange rate fluctuations for EMCs.
"Following the encouraging response from prospective customers Dreamchip Electronics is initially targeting the large and fast growing Indian market. Dreamchip plans to offer the SoCs globally at a later stage" said Gopi Kumar Bulusu, founder director at Dreamchip.
"From various technical discussions with Dreamchip Electronics, we believe that the new SoC platforms from Dreamchip will enable quick Innovation and shorten product development cycles" said a senior executive at TVS Electronics Limited.
Prototyping platforms for all three variants will be available by Q3 calendar year 2013 on the Teraptor Consumer Electronics Channel. Select customers are expected to receive early access FPGA Kits and test chips by Q1/Q3 2014, respectively.
The SoCs come in three different variants named Siddhi, Vani and Sandesh. Each one of these has been specified and optimized for a distinct tablet application. Dreamchip will use a proprietary multi-core 32-bit RISC and DSP processor architecture and a unique optimized direct connect architecture for powering these SoCs.
Siddhi is designed to power basic student's book reader tablets that are optimized for low cost large volume applications. Siddhi powered tablets are expected to replace printed text books. Vani is targeted towards advanced student's multi-media tablets that offer a rich multi-media experience for students. Sandesh the high-end SoC is optimized for use in citizen-centric e-governance and e-commerce tablets.
All of the SoCs are designed to help Indian EMCs cater to the needs of rural as well as value conscious urban users and will be accompanied by reference tablet designs and embedded software with the option to support different Indian languages.
Solutions from Dreamchip are expected to play a critical role by enabling EMCs to create world class tablet computers and offer them to customers in India and the rest of the world at competitive rates. All the SoCs are expected to be priced in Indian Rupees for the Indian market thereby eliminating risk from exchange rate fluctuations for EMCs.
"Following the encouraging response from prospective customers Dreamchip Electronics is initially targeting the large and fast growing Indian market. Dreamchip plans to offer the SoCs globally at a later stage" said Gopi Kumar Bulusu, founder director at Dreamchip.
"From various technical discussions with Dreamchip Electronics, we believe that the new SoC platforms from Dreamchip will enable quick Innovation and shorten product development cycles" said a senior executive at TVS Electronics Limited.
Prototyping platforms for all three variants will be available by Q3 calendar year 2013 on the Teraptor Consumer Electronics Channel. Select customers are expected to receive early access FPGA Kits and test chips by Q1/Q3 2014, respectively.
Mature fabs still process 40 percent of all silicon
USA: Advanced technologies and the latest consumer electronics grab the major headlines but the semiconductor industry depends on mature technologies and legacy equipment.
Today, about 40 percent of all silicon used to produce semiconductors are processed using mature manufacturing technologies. The manufacturing processes at 0.18 micron and larger still utilize 200mm and smaller wafer fabs.
Semico's Joanne Itow closely follows these markets, and has been invited to speak at the First Annual Collaborative Forum at the SEMI headquarters in San Jose, CA on Feb 6-7th, 2013. It's hosted by the Fab Owners Association, and the theme is "Innovating For Success In a Foundry-Dominated World."
Joanne Itow, Semico's MD, will be presenting on fab capacity and volume devices that continue to utilize mature technologies. In addition, she will moderate a panel on used equipment trends and issues related to maintaining legacy fabs.
Today, about 40 percent of all silicon used to produce semiconductors are processed using mature manufacturing technologies. The manufacturing processes at 0.18 micron and larger still utilize 200mm and smaller wafer fabs.
Semico's Joanne Itow closely follows these markets, and has been invited to speak at the First Annual Collaborative Forum at the SEMI headquarters in San Jose, CA on Feb 6-7th, 2013. It's hosted by the Fab Owners Association, and the theme is "Innovating For Success In a Foundry-Dominated World."
Joanne Itow, Semico's MD, will be presenting on fab capacity and volume devices that continue to utilize mature technologies. In addition, she will moderate a panel on used equipment trends and issues related to maintaining legacy fabs.
Xilinx stays a generation ahead with multiple 20nm firsts
USA: Xilinx Inc. announced three major milestones in the execution and introduction of its next generation 20nm All Programmable Devices.
The 20nm portfolio builds upon Xilinx breakthroughs proven at 28nm to provide an extra generation of system performance, lower power and programmable system integration. The 20nm portfolio will address a wide range of next generation systems and provides the most compelling programmable alternative ever to ASICs and ASSPs.
“Xilinx went ‘all in’ to move a generation ahead at 28nm, and is doing the same at 20nm to stay a generation ahead. We are on a very aggressive path to deliver our next generation design tools and devices into the hands of our customers,” said Victor Peng, senior vice president, Programmable Platform Group at Xilinx.
First design tools for 20nm
The Xilinx Vivado Design Suite, the first SoC strength design suite for programmable devices, will support initial 20nm devices in March 2013. At 20nm, the design suite will further accelerate time to integration and implementation by 4x as well as deliver up to 50 percent power reduction and three speed grades of performance improvement.
First 20nm product tape out
In the second quarter of 2013, Xilinx will tape out its first 20nm product on TSMC’s 20SoC manufacturing process. Xilinx will be readying device samples this year for strategic customers who can begin implementing next-generation applications. Xilinx optimized its 20nm All Programmable portfolio to address the requirements of ever smarter, highly integrated, bandwidth hungry systems in wired and wireless networks, data centers, vision based systems, and other high performance applications.
First ten early access customers
Xilinx is now engaging with the first ten customers on 20nm architecture evaluations and implementation activities. With availability of documentation since November 2012, Xilinx has been working closely with an increasing number of strategic customers doing early design work. With the upcoming availability of design tools this quarter, the level of design activity will grow significantly.
The 20nm portfolio builds upon Xilinx breakthroughs proven at 28nm to provide an extra generation of system performance, lower power and programmable system integration. The 20nm portfolio will address a wide range of next generation systems and provides the most compelling programmable alternative ever to ASICs and ASSPs.
“Xilinx went ‘all in’ to move a generation ahead at 28nm, and is doing the same at 20nm to stay a generation ahead. We are on a very aggressive path to deliver our next generation design tools and devices into the hands of our customers,” said Victor Peng, senior vice president, Programmable Platform Group at Xilinx.
First design tools for 20nm
The Xilinx Vivado Design Suite, the first SoC strength design suite for programmable devices, will support initial 20nm devices in March 2013. At 20nm, the design suite will further accelerate time to integration and implementation by 4x as well as deliver up to 50 percent power reduction and three speed grades of performance improvement.
First 20nm product tape out
In the second quarter of 2013, Xilinx will tape out its first 20nm product on TSMC’s 20SoC manufacturing process. Xilinx will be readying device samples this year for strategic customers who can begin implementing next-generation applications. Xilinx optimized its 20nm All Programmable portfolio to address the requirements of ever smarter, highly integrated, bandwidth hungry systems in wired and wireless networks, data centers, vision based systems, and other high performance applications.
First ten early access customers
Xilinx is now engaging with the first ten customers on 20nm architecture evaluations and implementation activities. With availability of documentation since November 2012, Xilinx has been working closely with an increasing number of strategic customers doing early design work. With the upcoming availability of design tools this quarter, the level of design activity will grow significantly.
ST reports Q4-2012 and full year financial results
SWITZERLAND: STMicroelectronics reported financial results for the fourth quarter and full year ended December 31, 2012.
Fourth quarter net revenues totaled $2.16 billion and gross margin was 32.3 percent. Net loss attributable to parent company was $428 million, mainly due to a charge of $544 million for the impairment of Wireless goodwill and other intangible assets following the company’s decision to exit the ST-Ericsson joint venture after the communicated transition period as part of the Company’s new strategic plan announced on December 10, 2012.
President and CEO, Carlo Bozotti, said: “In the fourth quarter, revenue and gross margin results came in above the midpoint of our guidance despite the ongoing softness in the semiconductor market. We extended our leadership in key areas. Thanks to new product momentum, revenues from our wholly-owned businesses increased 0.2 percent and 1.6 percent on a sequential and year-ago basis driven by a very strong ramp of our MEMS products in the fourth quarter.
“Looking at 2012 overall, we improved our net financial position compared to 2011 despite the significant cash used by ST-Ericsson as well as the impact of weak business conditions. We were able to end the year with significant financial flexibility and strong cash balances while providing shareholders with the same level of dividend compared to 2011.
“Important decisions were made in 2012 that are shaping a new, more focused, higher-performing ST. In December, we announced our new strategic plan targeting leadership in two product segments: Sense & Power and Automotive Products and Embedded Processing Solutions. This new strategy includes a sharper focus on five growth drivers: MEMS and sensors, Smart Power, automotive products, microcontrollers, and application processors including digital consumer products.
"Importantly, from a financial model perspective, we are targeting an operating margin of 10 percent or more. A key component to achieving this objective is bringing our net operating expenses to an average quarterly rate in the range of $600 million to $650 million by the beginning of 2014.
“In connection with our strategic plan, we decided to exit ST-Ericsson after a transition period and our actions this past quarter, including the further impairment charge, are aligned with moving this decision forward.”
Fourth quarter net revenues totaled $2.16 billion and gross margin was 32.3 percent. Net loss attributable to parent company was $428 million, mainly due to a charge of $544 million for the impairment of Wireless goodwill and other intangible assets following the company’s decision to exit the ST-Ericsson joint venture after the communicated transition period as part of the Company’s new strategic plan announced on December 10, 2012.
President and CEO, Carlo Bozotti, said: “In the fourth quarter, revenue and gross margin results came in above the midpoint of our guidance despite the ongoing softness in the semiconductor market. We extended our leadership in key areas. Thanks to new product momentum, revenues from our wholly-owned businesses increased 0.2 percent and 1.6 percent on a sequential and year-ago basis driven by a very strong ramp of our MEMS products in the fourth quarter.
“Looking at 2012 overall, we improved our net financial position compared to 2011 despite the significant cash used by ST-Ericsson as well as the impact of weak business conditions. We were able to end the year with significant financial flexibility and strong cash balances while providing shareholders with the same level of dividend compared to 2011.
“Important decisions were made in 2012 that are shaping a new, more focused, higher-performing ST. In December, we announced our new strategic plan targeting leadership in two product segments: Sense & Power and Automotive Products and Embedded Processing Solutions. This new strategy includes a sharper focus on five growth drivers: MEMS and sensors, Smart Power, automotive products, microcontrollers, and application processors including digital consumer products.
"Importantly, from a financial model perspective, we are targeting an operating margin of 10 percent or more. A key component to achieving this objective is bringing our net operating expenses to an average quarterly rate in the range of $600 million to $650 million by the beginning of 2014.
“In connection with our strategic plan, we decided to exit ST-Ericsson after a transition period and our actions this past quarter, including the further impairment charge, are aligned with moving this decision forward.”
Wednesday, January 30, 2013
Mentor Graphics announces new HyperLynx technology
DesignCon 2013, USA: Mentor Graphics Corp. announced the newest release of its market-leading HyperLynx product for superior high-speed design and analysis.
Key features in the new HyperLynx product release include advanced 3D channel and trace modeling, improved DDR signoff verification, and accelerated simulation performance—up to 5X faster.
Engineers and designers who use the HyperLynx products during the system design process can quickly analyze potential high-speed design issues that can impact signal integrity, power integrity, and electromagnetic interference (EMI) performance. These new capabilities will improve product quality and performance by correcting problems earlier in the design process with minimized risk and greater productivity.
“In applications above 10 Gbps, insertion loss will often exceed -12 dB at the Nyquist and eyes will be completely closed. Successful designs require getting everything in the design right and building confidence in the design early in the design cycle with accurate simulations,” stated Eric Bogatin, signal integrity evangelist, Bogatin Enterprises, a wholly owned subsidiary of Teledyne-LeCroy.
“The accuracy of the latest release of Mentor Graphics HyperLynx was recently validated with a 12.5 Gbps backplane design from Molex that included causal material models, copper surface texture contributions, via models, mode conversion and reflections from integrated S-parameter models of connectors.”
Advanced channel and trace modeling
The new HyperLynx product decreases the amount of channel modeling that requires 3D analysis with advanced area fill-aware 2.5D planar trace extraction. When this advanced feature is enabled, the system will model variations in signal trace impedance or delays due to non-ideal planes and references (complex area fills with voids and cuts). The resulting impedance variation effects are included during time domain simulation and s-parameter model extraction.
Where necessary, the HyperLynx product also provides full 3D extraction and modeling. The designer can quickly select board areas for 3D full wave analysis, including exporting the full channel to the schematic editor for auto-port creation, assignment and simulation, tightly integrating the HyperLynx 3D EM full wave solver.
Lightning fast simulator
The newest release of the HyperLynx product provides fast and powerful analysis results, with an average of 5x simulation performance improvement over the previous release. Internal tests of earlier versions and the new HyperLynx product release show a significant increase in the performance of the circuit simulator, especially for large-scale batch-mode analysis with complex stimulus (for example, DDRx simulation).
In addition to substantially increased performance, the upgraded simulator takes extra care to avoid accuracy problems for circuits involving short transmission lines, which are common when modeling PCB-trace meanders. Many of the non-Mentor simulators—especially SPICE-based ones—round-up or eliminate the short delays of small routing segments based on the analysis time step, but the HyperLynx tool accurately preserves such effects, including during complex crosstalk simulations.
Overall, especially for large boards with a significant number of delay-tuned nets, customers will see high-accuracy results in noticeably less simulation time.
Here are a few of the powerful analysis capabilities found in this new HyperLynx release:
* Pre-layout DDRx signal integrity and comprehensive cycle-based timing simulation during parametric sweeps. The HyperLynx DDRx wizard supports DDR3L and DDR3U supply levels by incorporating the required derating tables, timing models, and voltage levels, plus test-load compensation of signal launch delays using the DDRx wizard.
* Batch support of s-parameter models from the post-route environment; interconnect modeling with accurate wideband dielectric models and surface roughness.
* Advanced meshing for DC drop analysis to review accuracy of narrow slivers of metals within complex designs.
* Accelerated simulation flow of IBIS AMI models in statistical mode with LTI equalization algorithms; this feature is based on peak distortion analysis techniques and statistical algorithms that process impulse response of the channel directly for eye diagram generation to quickly produce results for buffers with LTI equalization schemes down to very low BER.
* Improvements to the advanced waveform viewer and processor, a graphical environment for displaying and analyzing large sets of simulation results that has many advanced measurements for complex waveform processing using a rich set of calculator functions. The improvements include an interactive simulation GUI that automatically plots centered eye diagrams.
The new HyperLynx release will ship in March 2013 and will be interfaced with all major PCB layout tools including the Mentor Expedition Enterprise, Board Station and PADS, Cadence Allegro and Zuken CR.
Key features in the new HyperLynx product release include advanced 3D channel and trace modeling, improved DDR signoff verification, and accelerated simulation performance—up to 5X faster.
Engineers and designers who use the HyperLynx products during the system design process can quickly analyze potential high-speed design issues that can impact signal integrity, power integrity, and electromagnetic interference (EMI) performance. These new capabilities will improve product quality and performance by correcting problems earlier in the design process with minimized risk and greater productivity.
“In applications above 10 Gbps, insertion loss will often exceed -12 dB at the Nyquist and eyes will be completely closed. Successful designs require getting everything in the design right and building confidence in the design early in the design cycle with accurate simulations,” stated Eric Bogatin, signal integrity evangelist, Bogatin Enterprises, a wholly owned subsidiary of Teledyne-LeCroy.
“The accuracy of the latest release of Mentor Graphics HyperLynx was recently validated with a 12.5 Gbps backplane design from Molex that included causal material models, copper surface texture contributions, via models, mode conversion and reflections from integrated S-parameter models of connectors.”
Advanced channel and trace modeling
The new HyperLynx product decreases the amount of channel modeling that requires 3D analysis with advanced area fill-aware 2.5D planar trace extraction. When this advanced feature is enabled, the system will model variations in signal trace impedance or delays due to non-ideal planes and references (complex area fills with voids and cuts). The resulting impedance variation effects are included during time domain simulation and s-parameter model extraction.
Where necessary, the HyperLynx product also provides full 3D extraction and modeling. The designer can quickly select board areas for 3D full wave analysis, including exporting the full channel to the schematic editor for auto-port creation, assignment and simulation, tightly integrating the HyperLynx 3D EM full wave solver.
Lightning fast simulator
The newest release of the HyperLynx product provides fast and powerful analysis results, with an average of 5x simulation performance improvement over the previous release. Internal tests of earlier versions and the new HyperLynx product release show a significant increase in the performance of the circuit simulator, especially for large-scale batch-mode analysis with complex stimulus (for example, DDRx simulation).
In addition to substantially increased performance, the upgraded simulator takes extra care to avoid accuracy problems for circuits involving short transmission lines, which are common when modeling PCB-trace meanders. Many of the non-Mentor simulators—especially SPICE-based ones—round-up or eliminate the short delays of small routing segments based on the analysis time step, but the HyperLynx tool accurately preserves such effects, including during complex crosstalk simulations.
Overall, especially for large boards with a significant number of delay-tuned nets, customers will see high-accuracy results in noticeably less simulation time.
Here are a few of the powerful analysis capabilities found in this new HyperLynx release:
* Pre-layout DDRx signal integrity and comprehensive cycle-based timing simulation during parametric sweeps. The HyperLynx DDRx wizard supports DDR3L and DDR3U supply levels by incorporating the required derating tables, timing models, and voltage levels, plus test-load compensation of signal launch delays using the DDRx wizard.
* Batch support of s-parameter models from the post-route environment; interconnect modeling with accurate wideband dielectric models and surface roughness.
* Advanced meshing for DC drop analysis to review accuracy of narrow slivers of metals within complex designs.
* Accelerated simulation flow of IBIS AMI models in statistical mode with LTI equalization algorithms; this feature is based on peak distortion analysis techniques and statistical algorithms that process impulse response of the channel directly for eye diagram generation to quickly produce results for buffers with LTI equalization schemes down to very low BER.
* Improvements to the advanced waveform viewer and processor, a graphical environment for displaying and analyzing large sets of simulation results that has many advanced measurements for complex waveform processing using a rich set of calculator functions. The improvements include an interactive simulation GUI that automatically plots centered eye diagrams.
The new HyperLynx release will ship in March 2013 and will be interfaced with all major PCB layout tools including the Mentor Expedition Enterprise, Board Station and PADS, Cadence Allegro and Zuken CR.
Imagination selects Synopsys as advanced verification technology partner
USA: Synopsys Inc. announced that Imagination Technologies has deployed Synopsys' C–to-RTL formal consistency checking technology, named HECTOR, to verify its PowerVR family of semiconductor IP cores for graphics, video and display processing applications. Following a multi-year collaboration with Synopsys, Imagination Technologies is utilizing HECTOR to enhance its verification environment with the ability to verify and debug corner cases.
"Synopsys' HECTOR technology has enabled us to perform formal equivalence checking between system-level models and RTL over a range of complex PowerVR cores," said Martin Ashton, vice president of Imagination's PowerVR IP engineering group.
"The HECTOR technology has allowed us to complete formal verification in minutes, where exhaustive techniques would have been impractical. As a result, HECTOR has enabled us to significantly improve the design verification capabilities within our PowerVR GPU team. We anticipate using HECTOR across all our IP design groups, while, thanks to our close and creative engagement with Synopsys' HECTOR R&D team, we continue to explore new applications of this exciting technology."
"With the increasing complexity of system-on-chips (SoCs), next-generation verification technologies are essential to more effectively manage SoC quality, schedule and cost," said Manoj Gandhi, senior VP and GM of Synopsys Verification Group. "We are delighted to have such close R&D level collaborations with Imagination Technologies, a leading innovator in the industry, enabling us to deliver ground-breaking technologies that address growing verification challenges."
Multimedia applications involve complex algorithmic functional blocks requiring their behavior to be modeled in high-level languages such as C, and subsequently ensuring that the implemented RTL description is functionally equivalent. Conventional simulation-based verification of these design elements can be time-consuming and is likely to miss corner-case design bugs that would manifest only in the SoC where the IP core becomes embedded.
With HECTOR, design teams are able to exhaustively verify all combinations of inputs and gain a high level of confidence in the quality of their IP blocks.
"Synopsys' HECTOR technology has enabled us to perform formal equivalence checking between system-level models and RTL over a range of complex PowerVR cores," said Martin Ashton, vice president of Imagination's PowerVR IP engineering group.
"The HECTOR technology has allowed us to complete formal verification in minutes, where exhaustive techniques would have been impractical. As a result, HECTOR has enabled us to significantly improve the design verification capabilities within our PowerVR GPU team. We anticipate using HECTOR across all our IP design groups, while, thanks to our close and creative engagement with Synopsys' HECTOR R&D team, we continue to explore new applications of this exciting technology."
"With the increasing complexity of system-on-chips (SoCs), next-generation verification technologies are essential to more effectively manage SoC quality, schedule and cost," said Manoj Gandhi, senior VP and GM of Synopsys Verification Group. "We are delighted to have such close R&D level collaborations with Imagination Technologies, a leading innovator in the industry, enabling us to deliver ground-breaking technologies that address growing verification challenges."
Multimedia applications involve complex algorithmic functional blocks requiring their behavior to be modeled in high-level languages such as C, and subsequently ensuring that the implemented RTL description is functionally equivalent. Conventional simulation-based verification of these design elements can be time-consuming and is likely to miss corner-case design bugs that would manifest only in the SoC where the IP core becomes embedded.
With HECTOR, design teams are able to exhaustively verify all combinations of inputs and gain a high level of confidence in the quality of their IP blocks.
Real Intent unveils major performance enhancements in Ascent IIV and Ascent XV tools
USA: Real Intent Inc. announced new releases of its Ascent Implied Intent Verification (IIV) and Ascent X-Verification (XV) tools for early functional analysis of digital designs, delivering significant performance enhancements for users.
Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved quality of results (QoR) and productivity of design teams.
Among new Ascent IIV features and enhancements are:
* Up to 50-percent faster performance on designs greater than 100K gates.
* Incremental runs enabling users to resume previous analysis and avoid a complete re-start.
* A new double-toggle net check that eliminates toggle net false positives caused by reset state values.
* VCD traces that provide a marker to show the time of failure.
Likewise, new features in Ascent XV for detecting unknowns in digital hardware include:
* Enhanced modeling of X’s that come from retention flops, a major source of X’s in a design.
* Broader coverage in identifying all X-sources and X-sensitive logic found by fast design audit.
* Tighter SimPortal integration to logic simulation that automatically generates a simulation free of unnecessary X issues.
* A new debug interface that shows the path from the sensitive construct to an X-source, facilitates waivers of X-sources and X-sensitive nets, and provides links for source code navigation.
Lisa Piper, technical marketing manager at Real Intent, said: “The enhanced performance of IIV means designers can find more bugs more quickly without the need for any test benches. Our latest release of XV provides a unique X-hazard report that quickly pinpoints where sources of unknowns can obscure functional bugs or generate false problems in gate-level netlists.
"IIV’s 50-percent faster performance for blocks greater than 100K gates and XV’s enhanced detection of unknowns (X’s) in digital hardware including retention flops are further proof that Real Intent delivers what we believe are the industry’s best-in-class tools. Our Ascent products are the fastest and highest-capacity verification solutions available for uncovering issues prior to digital simulation.”
Ascent IIV and Ascent XV now deliver enhanced support for SystemVerilog, Verilog and VHDL languages, and improve ease of use in both the GUI and low-noise reporting of design issues. They also come with Verdi3 integration now to support this industry-leading debug platform from Synopsys (formerly SpringSoft).
The latest releases of Ascent IIV and Ascent XV are available immediately for download from the Real Intent web-site.
Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved quality of results (QoR) and productivity of design teams.
Among new Ascent IIV features and enhancements are:
* Up to 50-percent faster performance on designs greater than 100K gates.
* Incremental runs enabling users to resume previous analysis and avoid a complete re-start.
* A new double-toggle net check that eliminates toggle net false positives caused by reset state values.
* VCD traces that provide a marker to show the time of failure.
Likewise, new features in Ascent XV for detecting unknowns in digital hardware include:
* Enhanced modeling of X’s that come from retention flops, a major source of X’s in a design.
* Broader coverage in identifying all X-sources and X-sensitive logic found by fast design audit.
* Tighter SimPortal integration to logic simulation that automatically generates a simulation free of unnecessary X issues.
* A new debug interface that shows the path from the sensitive construct to an X-source, facilitates waivers of X-sources and X-sensitive nets, and provides links for source code navigation.
Lisa Piper, technical marketing manager at Real Intent, said: “The enhanced performance of IIV means designers can find more bugs more quickly without the need for any test benches. Our latest release of XV provides a unique X-hazard report that quickly pinpoints where sources of unknowns can obscure functional bugs or generate false problems in gate-level netlists.
"IIV’s 50-percent faster performance for blocks greater than 100K gates and XV’s enhanced detection of unknowns (X’s) in digital hardware including retention flops are further proof that Real Intent delivers what we believe are the industry’s best-in-class tools. Our Ascent products are the fastest and highest-capacity verification solutions available for uncovering issues prior to digital simulation.”
Ascent IIV and Ascent XV now deliver enhanced support for SystemVerilog, Verilog and VHDL languages, and improve ease of use in both the GUI and low-noise reporting of design issues. They also come with Verdi3 integration now to support this industry-leading debug platform from Synopsys (formerly SpringSoft).
The latest releases of Ascent IIV and Ascent XV are available immediately for download from the Real Intent web-site.
Semico Research and Algotochip collaborate on design methodology research
USA: Algotochip, specialists in converting C models of algorithms directly to a complete SoC silicon IP, announced the availability of a research report from Semico Research that states the researchers belief “that the Algotochip design methodology offers a very good alternative to the current SoC design flows employed today.”
The semiconductor industry today is faced with several substantial issues—not the least of which are the continuing rise in design costs for SoCs (System-on-a-Chip), the decrease in the incidence of 1st time effort designs and the increase in the design cycle time against shrinking market windows and decreasing product lifetimes.
An additional factor has now been added to SoC design costs with the emergence of the very complicated software applications intended to run on the SoC silicon. The costs of the software effort have outstripped the silicon design costs and have become the major part of the cost in most of these designs.
Although these problems may seem insurmountable, Semico believes that the Algotochip design methodology offers a very suitable alternative to the current SoC design flows employed today.
“Not only is Algotochip able to make the silicon design effort more efficient by reducing design cycle times and design costs,” said Richard Warzyniak, senior analyst. “Their design approach can offer customers the opportunity to have more designs completed in less time and for less money than competing alternatives.”
“Algotochip guarantees that its SoC meets all the performance specifications made by the customer, and insures that it will be first time right,” said Didier Boivin, VP marketing, Algotochip. “Given the increasingly complex nature of SoC designs, this guarantee means companies can deliver products more quickly and less expensively than previously thought possible.”
The report addresses several of the interrelated issues that impact SoC designs. Topics covered include how economic turmoil, raising design costs and unpredictable demand inhibit a company’s ability to deploy the latest innovations.
The semiconductor industry today is faced with several substantial issues—not the least of which are the continuing rise in design costs for SoCs (System-on-a-Chip), the decrease in the incidence of 1st time effort designs and the increase in the design cycle time against shrinking market windows and decreasing product lifetimes.
An additional factor has now been added to SoC design costs with the emergence of the very complicated software applications intended to run on the SoC silicon. The costs of the software effort have outstripped the silicon design costs and have become the major part of the cost in most of these designs.
Although these problems may seem insurmountable, Semico believes that the Algotochip design methodology offers a very suitable alternative to the current SoC design flows employed today.
“Not only is Algotochip able to make the silicon design effort more efficient by reducing design cycle times and design costs,” said Richard Warzyniak, senior analyst. “Their design approach can offer customers the opportunity to have more designs completed in less time and for less money than competing alternatives.”
“Algotochip guarantees that its SoC meets all the performance specifications made by the customer, and insures that it will be first time right,” said Didier Boivin, VP marketing, Algotochip. “Given the increasingly complex nature of SoC designs, this guarantee means companies can deliver products more quickly and less expensively than previously thought possible.”
The report addresses several of the interrelated issues that impact SoC designs. Topics covered include how economic turmoil, raising design costs and unpredictable demand inhibit a company’s ability to deploy the latest innovations.
STATS ChipPAC and UMC unveil world’s first 3D IC developed under an open ecosystem model
TAIWAN: STATS ChipPAC Ltd and United Microelectronics Corp. have announced the world’s first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration.
The 3D chip stack, consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip, successfully reached a major milestone on package-level reliability assessment. This success demonstrates a total solution for reliable 3D IC manufacturing through the combination of UMC’s foundry and STATS ChipPAC’s packaging services.
”The next level of chip integration is rapidly evolving, and 3D IC technology is poised to enable the next frontier of IC capabilities for customers under various deployment models.” said Shim Il Kwon, VP of Technology Innovation of STATS ChipPAC.
“The open ecosystem collaborative approach drives proven and reliable 3D IC solutions for the semiconductor market by combining the foundry partner’s robust, leading-edge TSV and front-end-of-line (FEOL) process technologies in a complementary platform with an Outsourced Semiconductor Assembly and Test (OSAT) service provider with innovative engineering excellence to seamlessly integrate mid-end-of-line (MEOL) and back-end-of-line (BEOL) 3D IC processes. We are pleased with UMC’s commitment to this role and look forward to future collaborations. The results are a proven solution platform that will enable customers to capitalize on new market opportunities.”
S.C. Chien, VP of Advanced Technology Development at UMC, said: “We see no imperative to restrict 3D IC to a captive business model, as UMC’s development work with nearly all the major OSAT partners for 3D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach. This model should work especially well for our mutual 3D IC customers, as foundry and OSAT can utilize their respective core strengths during development and delivery, while customers can benefit from keeping supply chain management flexible and realize better transparency over technology access compared to closed, captive 3D IC business models.”
UMC and STATS ChipPAC’s proven open ecosystem 3D IC approach sets an important standard for collaboration within the industry supply chain to achieve mutual success. Under the 3DIC open development project with STATS ChipPAC, UMC provides the FEOL wafer manufacturing, with a foundry grade fine pitch, high density TSV process that can be seamlessly integrated with UMC’s 28nm poly SiON process flow.
The know-how developed will be applied towards implementation on the foundry’s 28nm High-K/metal gate process. For MEOL and BEOL, STATS ChipPAC performs the wafer thinning, wafer backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking.
The 3D chip stack, consisting of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip, successfully reached a major milestone on package-level reliability assessment. This success demonstrates a total solution for reliable 3D IC manufacturing through the combination of UMC’s foundry and STATS ChipPAC’s packaging services.
”The next level of chip integration is rapidly evolving, and 3D IC technology is poised to enable the next frontier of IC capabilities for customers under various deployment models.” said Shim Il Kwon, VP of Technology Innovation of STATS ChipPAC.
“The open ecosystem collaborative approach drives proven and reliable 3D IC solutions for the semiconductor market by combining the foundry partner’s robust, leading-edge TSV and front-end-of-line (FEOL) process technologies in a complementary platform with an Outsourced Semiconductor Assembly and Test (OSAT) service provider with innovative engineering excellence to seamlessly integrate mid-end-of-line (MEOL) and back-end-of-line (BEOL) 3D IC processes. We are pleased with UMC’s commitment to this role and look forward to future collaborations. The results are a proven solution platform that will enable customers to capitalize on new market opportunities.”
S.C. Chien, VP of Advanced Technology Development at UMC, said: “We see no imperative to restrict 3D IC to a captive business model, as UMC’s development work with nearly all the major OSAT partners for 3D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach. This model should work especially well for our mutual 3D IC customers, as foundry and OSAT can utilize their respective core strengths during development and delivery, while customers can benefit from keeping supply chain management flexible and realize better transparency over technology access compared to closed, captive 3D IC business models.”
UMC and STATS ChipPAC’s proven open ecosystem 3D IC approach sets an important standard for collaboration within the industry supply chain to achieve mutual success. Under the 3DIC open development project with STATS ChipPAC, UMC provides the FEOL wafer manufacturing, with a foundry grade fine pitch, high density TSV process that can be seamlessly integrated with UMC’s 28nm poly SiON process flow.
The know-how developed will be applied towards implementation on the foundry’s 28nm High-K/metal gate process. For MEOL and BEOL, STATS ChipPAC performs the wafer thinning, wafer backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking.
Databeans projects modest growth for 2013 semiconductor industry
USA: The global semiconductor market witnessed another flat market for the year 2012 with sluggish demand across all market segments resulting from lingering uncertainties in the global economic situation, particularly in major regional markets such as the US, EU, and China, all of which saw poorer than expected results for the year.
This situation put unavoidable pressure on the semiconductor industries, as poor demand meant that existing chip inventories could not move quickly enough in order to facilitate the building of new inventory.
With that being said, Databeans expects that the year 2013 will see a solid rebound, growing by 7 percent from 2012 totals to reach $313.04 billion in total global sales for the entire 2013 year. In all market segments supply has managed to better align with demand, which is steadily growing. ASPs across the board, but particularly in memory devices, have stabilized.
The strongest demand is coming from the highly popular consumer and wireless segments, and specifically in the mobile phones and tablet sectors which have provided a big boost to the sales of high value chips such as mobile processors, logic ICs and NAND Flash memory.
When broken down into individual market segments the greatest growth from 2012 to 2013 will take place in the wired communications market which will grow 15 percent and will reach nearly $32.5 billion. This strong growth will mainly result from the continued rollout of infrastructure equipment supporting data centers worldwide. The strongest growth rates are coming from the various countries that make up the Asia Pacific region.
The wireless communications industry is expected to follow with a year over year (Y/Y) growth rate of 9 percent and will reach nearly $79.5 billion in global chip sales for 2013. Specifically, a huge portion of growth will come from China. Heading into 2013, China’s domestic handset OEMs including Lenovo, ZTE, and Huawei will fully target the lower income individuals that make up the vast bulk of China’s consumer base with several series of low-end and mid-range handsets priced at or around 1000 Yuan (or $160).
This move will further increase the prevalence of feature phones in China. It is expected that a similar trend will take place in other emerging markets including India, Southeast Asia, and Central/South America during the next two to three years.
Other market segments that will see modest growth include Automotive, Industrial, and Consumer Electronics (CE), all of which are slated to grow by 6 percent from 2012 to 2013. In the automotive industry growth will be perpetuated by the expanding industries for in-car information, entertainment, mobile integration, increased vehicle safety and efficiency, and new types of propulsion systems. More focus will also be placed on in-car apps and open-source software that will provide automakers with faster, better ways to incorporate advancements into their vehicle systems.
Meanwhile, the traditional CE market will continue be driven by solid demand for home entertainment devices including HDTVs, set-top-boxes, and home audio, all of which are expected to remain major market segments in 2013. Despite weakness in this industry over the past two years, the future is expected to be bright for this industry, driven by major advancements in TV display size and quality, as well as substantial growth in streaming, digital download, and cloud services which allow for a more personalized entertainment experience.
Finally, the weakest growth will be seen in the computer segment, which will grow by just 4 percent in 2013 to $82.5 billion in semiconductor sales. While the traditional desktop and server markets will continue to grow at a slower pace, the market for mobile tablets and laptops will help prop the industry up. The release of Windows 8 OS in the latter half of 2012 is also expected to have an impact here. Specifically, Windows 8 should drive additional high end PC revenue and could also end up pushing tablets into the corporate computing environment, as the OS allows users to do tasks using the Microsoft Office Suite.
While some experts remain cautious about a full-fledged recovery, most indications are signaling a modest return to growth for the overall global economy with improved consumer confidence, easier availability of credit, and lower unemployment rates around the world. Certain regions, including the U.S. and APAC will outperform their counterparts in the EU and Japan. But even with that being said, Databeans fully believes that the semiconductor industry as a whole will see much better results this year and will continue this momentum into the years to come.
This situation put unavoidable pressure on the semiconductor industries, as poor demand meant that existing chip inventories could not move quickly enough in order to facilitate the building of new inventory.
With that being said, Databeans expects that the year 2013 will see a solid rebound, growing by 7 percent from 2012 totals to reach $313.04 billion in total global sales for the entire 2013 year. In all market segments supply has managed to better align with demand, which is steadily growing. ASPs across the board, but particularly in memory devices, have stabilized.
The strongest demand is coming from the highly popular consumer and wireless segments, and specifically in the mobile phones and tablet sectors which have provided a big boost to the sales of high value chips such as mobile processors, logic ICs and NAND Flash memory.
The wireless communications industry is expected to follow with a year over year (Y/Y) growth rate of 9 percent and will reach nearly $79.5 billion in global chip sales for 2013. Specifically, a huge portion of growth will come from China. Heading into 2013, China’s domestic handset OEMs including Lenovo, ZTE, and Huawei will fully target the lower income individuals that make up the vast bulk of China’s consumer base with several series of low-end and mid-range handsets priced at or around 1000 Yuan (or $160).
This move will further increase the prevalence of feature phones in China. It is expected that a similar trend will take place in other emerging markets including India, Southeast Asia, and Central/South America during the next two to three years.
Other market segments that will see modest growth include Automotive, Industrial, and Consumer Electronics (CE), all of which are slated to grow by 6 percent from 2012 to 2013. In the automotive industry growth will be perpetuated by the expanding industries for in-car information, entertainment, mobile integration, increased vehicle safety and efficiency, and new types of propulsion systems. More focus will also be placed on in-car apps and open-source software that will provide automakers with faster, better ways to incorporate advancements into their vehicle systems.
Meanwhile, the traditional CE market will continue be driven by solid demand for home entertainment devices including HDTVs, set-top-boxes, and home audio, all of which are expected to remain major market segments in 2013. Despite weakness in this industry over the past two years, the future is expected to be bright for this industry, driven by major advancements in TV display size and quality, as well as substantial growth in streaming, digital download, and cloud services which allow for a more personalized entertainment experience.
Finally, the weakest growth will be seen in the computer segment, which will grow by just 4 percent in 2013 to $82.5 billion in semiconductor sales. While the traditional desktop and server markets will continue to grow at a slower pace, the market for mobile tablets and laptops will help prop the industry up. The release of Windows 8 OS in the latter half of 2012 is also expected to have an impact here. Specifically, Windows 8 should drive additional high end PC revenue and could also end up pushing tablets into the corporate computing environment, as the OS allows users to do tasks using the Microsoft Office Suite.
While some experts remain cautious about a full-fledged recovery, most indications are signaling a modest return to growth for the overall global economy with improved consumer confidence, easier availability of credit, and lower unemployment rates around the world. Certain regions, including the U.S. and APAC will outperform their counterparts in the EU and Japan. But even with that being said, Databeans fully believes that the semiconductor industry as a whole will see much better results this year and will continue this momentum into the years to come.
BioMEMS market will almost triple in size over next five years
FRANCE: Yole Développement announced its report “BioMEMS”. In this new edition, Yole Développement has gone a step further in its forecasts by splitting each general application into more detailed sub-applications. For example, “Blood Pressure applications” is separated into “blood monitoring disposable” and “blood monitoring equipment”. Moreover, compared to the previous edition, the company added the latest market data for each device category explored and specific case studies.
“The BioMEMS market is expected to grow rapidly, from $1.9 billion in 2012 to $6.6 billion in 2018”, announces Benjamin Roussel, Technology & Market Analyst, Microfluidics & Medical Technologies at Yole Développement. According to him, microsystems integration is fast becoming a key added-value for system manufacturers.
The BioMEMS market will almost triple in size over the next five years, with mobile care applications contributing significantly to this impressive growth!
Microsystem devices have become increasingly visible in the healthcare market by serving as solutions adapted to the requirements of various applications. The usefulness of these devices is two-fold: for one, they improve medical device performance for the patient; and secondly, they offer competitive advantages to system manufacturers. For example, the introduction of accelerometers in pacemakers has revolutionized the treatment of cardiac diseases.
The microsystem technologies market for healthcare applications looks promising, and should reach $6.6B by 2018. Yole Développement has followed this market’s innovations and key players for the last several years, and based on an accurate analysis of the market’s last three years, this new report consolidates market data for 2010-2012 and provides forecasts for 2012-2018.
The devices considered in the BioMEMS 2013 report are pressure sensors, silicon microphones, accelerometers, gyroscopes, optical MEMS and Image sensors, microfluidic chips, microdispensers for drug delivery, flow meters, infrared temperature sensors, emerging MEMS (RFID, Strain sensors, Energy Harvesting).
For each of the above, Yole Développement’s report provides a market description, the main device and system manufacturers, current market data, and forecasts. Additionally, main technological trends are reviewed.
Yole Développement’s analyst, Benjamin Roussel, also takes a look at the microsystem devices dedicated to cell phone applications. Though mobile care is still in its infancy, we believe this market will grow significantly in the coming years.
Furthermore, specific case studies (including technology and player-specific overviews, innovative developments, supply chain data and patent information) have been included to better address two of the industry’s hottest topics: microfluidic chips and retinal implants. Indeed, these two micro devices possess the largest growth opportunity for the coming years.
Regulation overview
The regulation particulars for medical device development, included organisms and process overview, are described for five different regions: Europe, North America, Japan, China and India. This section is particularly important for microsystem device and systems manufacturers.
Microsystem devices have applications in four key healthcare markets: pharmaceutical, in-vitro diagnostics, medical devices and medical home care. Each of these markets has its own unique dynamics, players and global drivers. Motivation for the acceptance of BioMEMS technologies is highly dependent on each individual market.
Whereas the acceptance of microsystems is linked to sensibility and automation constraints in the Pharmaceutical market, in the in-vitro diagnostic market it’s all about portability and cost reduction; while the Medical Devices market is focused on addition of functionalities.
Concerning the Home Care market, the motivations are to increase system safety and connectivity. Yole Développement’s report reviews all four of these markets in a detailed manner.
Yole Développement’s experts have identified a number of applications for each device type. These applications can be placed into five groups: patient monitoring, patient care, medical imaging, in-vitro diagnostic testing and drug delivery. For each of these groups, the report provides an overview of devices and key market drivers, along with market data.
The BioMEMS 2013 report also pays particular attention to Chinese microsystems players, as a number of new players have recently entered the market.
“The BioMEMS market is expected to grow rapidly, from $1.9 billion in 2012 to $6.6 billion in 2018”, announces Benjamin Roussel, Technology & Market Analyst, Microfluidics & Medical Technologies at Yole Développement. According to him, microsystems integration is fast becoming a key added-value for system manufacturers.
The BioMEMS market will almost triple in size over the next five years, with mobile care applications contributing significantly to this impressive growth!
The microsystem technologies market for healthcare applications looks promising, and should reach $6.6B by 2018. Yole Développement has followed this market’s innovations and key players for the last several years, and based on an accurate analysis of the market’s last three years, this new report consolidates market data for 2010-2012 and provides forecasts for 2012-2018.
The devices considered in the BioMEMS 2013 report are pressure sensors, silicon microphones, accelerometers, gyroscopes, optical MEMS and Image sensors, microfluidic chips, microdispensers for drug delivery, flow meters, infrared temperature sensors, emerging MEMS (RFID, Strain sensors, Energy Harvesting).
For each of the above, Yole Développement’s report provides a market description, the main device and system manufacturers, current market data, and forecasts. Additionally, main technological trends are reviewed.
Yole Développement’s analyst, Benjamin Roussel, also takes a look at the microsystem devices dedicated to cell phone applications. Though mobile care is still in its infancy, we believe this market will grow significantly in the coming years.
Furthermore, specific case studies (including technology and player-specific overviews, innovative developments, supply chain data and patent information) have been included to better address two of the industry’s hottest topics: microfluidic chips and retinal implants. Indeed, these two micro devices possess the largest growth opportunity for the coming years.
Regulation overview
The regulation particulars for medical device development, included organisms and process overview, are described for five different regions: Europe, North America, Japan, China and India. This section is particularly important for microsystem device and systems manufacturers.
Microsystem devices have applications in four key healthcare markets: pharmaceutical, in-vitro diagnostics, medical devices and medical home care. Each of these markets has its own unique dynamics, players and global drivers. Motivation for the acceptance of BioMEMS technologies is highly dependent on each individual market.
Whereas the acceptance of microsystems is linked to sensibility and automation constraints in the Pharmaceutical market, in the in-vitro diagnostic market it’s all about portability and cost reduction; while the Medical Devices market is focused on addition of functionalities.
Concerning the Home Care market, the motivations are to increase system safety and connectivity. Yole Développement’s report reviews all four of these markets in a detailed manner.
Yole Développement’s experts have identified a number of applications for each device type. These applications can be placed into five groups: patient monitoring, patient care, medical imaging, in-vitro diagnostic testing and drug delivery. For each of these groups, the report provides an overview of devices and key market drivers, along with market data.
The BioMEMS 2013 report also pays particular attention to Chinese microsystems players, as a number of new players have recently entered the market.
TI's home gateway reference design makes homes smarter
USA: A leading innovator of energy management, communication and control solutions for the smart grid, Texas Instruments Inc. (TI) has announced its first integrated HG3352 Home Gateway Reference Design to be demonstrated at DistribuTECH 2013.
The easy-to-use reference design links home energy systems that use ZigBee to any Wi-Fi router, so consumers can monitor or control their smart energy devices or home automation systems in the palm of a hand via smartphones or tablets. The reference design supports ZigBee, Wi-Fi and Ethernet connectivity right out of the box to allow developers to create home gateways that can interface with multiple systems, products and applications within a smart home.
TI's new reference design has been designed in partnership with Alektrona – a specialist in creating networked smart energy products and applications.
The Home Gateway Reference Design gives developers all of the hardware and software needed to build a home gateway system, including a 275 MHz Sitara ARM AM3352 Cortex-A8 processor that runs applications, multiple communication stacks, and provides local intelligence for energy management and home automation activities.
For wireless connectivity to the smart grid and within the home, the reference design includes TI's CC2530 ZigBee system-on-chip (SoC), WiLink 8.0 combo-connectivity solution, and TPS650250 power management integrated circuit. The home gateway design demonstrates how TI's complementary portfolio of embedded, analog and connectivity components can help developers save time and money by using tested and interoperable components from a single supplier.
The new Home Gateway Reference Design is the latest example of TI's commitment to helping developers create innovative technology that reduces energy consumption and smarter connected devices for the smart grid. With TI's extensive ARM processor portfolio that has more than 500 products and boasts offerings from $1 in price and up to 5 GHz in performance, developers can maximize their investment, accelerate time to market and enable differentiated products based on customer needs.
The easy-to-use reference design links home energy systems that use ZigBee to any Wi-Fi router, so consumers can monitor or control their smart energy devices or home automation systems in the palm of a hand via smartphones or tablets. The reference design supports ZigBee, Wi-Fi and Ethernet connectivity right out of the box to allow developers to create home gateways that can interface with multiple systems, products and applications within a smart home.
TI's new reference design has been designed in partnership with Alektrona – a specialist in creating networked smart energy products and applications.
The Home Gateway Reference Design gives developers all of the hardware and software needed to build a home gateway system, including a 275 MHz Sitara ARM AM3352 Cortex-A8 processor that runs applications, multiple communication stacks, and provides local intelligence for energy management and home automation activities.
For wireless connectivity to the smart grid and within the home, the reference design includes TI's CC2530 ZigBee system-on-chip (SoC), WiLink 8.0 combo-connectivity solution, and TPS650250 power management integrated circuit. The home gateway design demonstrates how TI's complementary portfolio of embedded, analog and connectivity components can help developers save time and money by using tested and interoperable components from a single supplier.
The new Home Gateway Reference Design is the latest example of TI's commitment to helping developers create innovative technology that reduces energy consumption and smarter connected devices for the smart grid. With TI's extensive ARM processor portfolio that has more than 500 products and boasts offerings from $1 in price and up to 5 GHz in performance, developers can maximize their investment, accelerate time to market and enable differentiated products based on customer needs.
TI's smart data concentrator module slashes up to nine months from development time
USA: Texas Instruments Inc. announced the Smart Data Concentrator Evaluation Module (EVM) at DistribuTECH 2013.
The TMDSDC-EVMAM335x is a highly integrated EVM that gives developers the ultimate level of flexibility and scalability with numerous performance, cost and connectivity options for their data concentrator designs. Based on TI's Sitara AM335x ARM Cortex-A8 processors, the EVM includes advanced hardware and software that reduce development time by up to nine months while still supporting connectivity to more than 1,000 smart meters.
The Smart Data Concentrator EVM expands the functionality of designs and enables quick connectivity to the smart grid. Developers can easily plug in different connectivity modules, including Sub-1GHz (LPRF), general packet radio service (GPRS), near field communication (NFC) and TI's power line communication (PLC) system-on-module contains a C2000 Piccolo F28PLC83 and AFE031 analog front end for robust G3 and PRIME support.
In addition, the data concentrator EVM offers an extensive open-source Linux software development kit that includes fully customizable, pre-written code. Developers can easily add functionality and features to data concentrator designs without the hassle of writing and tweaking code. It also includes resources such as PLC stacks (PLC-Lite, PRIME, G3, IEEE-P1901.2), network protocols and applications like DLMS/COSEM so developers can customize their products for multiple regional and global standards.
Developers can also leverage the customizable hardware and software to easily fit the new data concentrator evaluation module into a final product. With a sophisticated evaluation module that saves up to nine months in the design cycle, developers can instead focus on getting a differentiated product to market more quickly.
The new Smart Data Concentrator EVM is the latest example of TI's commitment to helping developers create innovative technology that reduces energy consumption and smarter connected devices for the smart grid. With TI's extensive ARM processor portfolio that has more than 500 products and boasts offerings from $1 in price and up to 5 GHz in performance, smart grid developers can maximize their investment, accelerate time to market and enable differentiated products based on customer needs.
Features and benefits:
* Sitara AM335x ARM Cortex-A8 processors provide the necessary performance headroom for the complex routing algorithm in the data concentrator to connect with more than 1,000 e-meters.
* Flexible Sitara processor portfolio is scalable from 300MHz to 1GHz based on customers' performance and cost needs.
* Integrated communication interfaces include two Ethernet (MAC) ports, USB and up to eight UARTs for easy connectivity to other systems on the smart grid.
* Multiple PLC stacks for MAC and PHY layers let developers create designs that support PLC-Lite, PRIME, G3, IEEE-P1901.2.
* IPv4, IPv6 and 6LoWPAN protocols allow developers to connect their data concentrator products to a wide range of home and building automation applications.
* DLMS/COSEM applications standard, supported by third party Aricent, defines how the data concentrator will organize the metering data and how to send it back to the utility.
The TMDSDC-EVMAM335x Smart Data Concentrator Evaluation Module is available for $695.
The TMDSDC-EVMAM335x is a highly integrated EVM that gives developers the ultimate level of flexibility and scalability with numerous performance, cost and connectivity options for their data concentrator designs. Based on TI's Sitara AM335x ARM Cortex-A8 processors, the EVM includes advanced hardware and software that reduce development time by up to nine months while still supporting connectivity to more than 1,000 smart meters.
The Smart Data Concentrator EVM expands the functionality of designs and enables quick connectivity to the smart grid. Developers can easily plug in different connectivity modules, including Sub-1GHz (LPRF), general packet radio service (GPRS), near field communication (NFC) and TI's power line communication (PLC) system-on-module contains a C2000 Piccolo F28PLC83 and AFE031 analog front end for robust G3 and PRIME support.
In addition, the data concentrator EVM offers an extensive open-source Linux software development kit that includes fully customizable, pre-written code. Developers can easily add functionality and features to data concentrator designs without the hassle of writing and tweaking code. It also includes resources such as PLC stacks (PLC-Lite, PRIME, G3, IEEE-P1901.2), network protocols and applications like DLMS/COSEM so developers can customize their products for multiple regional and global standards.
Developers can also leverage the customizable hardware and software to easily fit the new data concentrator evaluation module into a final product. With a sophisticated evaluation module that saves up to nine months in the design cycle, developers can instead focus on getting a differentiated product to market more quickly.
The new Smart Data Concentrator EVM is the latest example of TI's commitment to helping developers create innovative technology that reduces energy consumption and smarter connected devices for the smart grid. With TI's extensive ARM processor portfolio that has more than 500 products and boasts offerings from $1 in price and up to 5 GHz in performance, smart grid developers can maximize their investment, accelerate time to market and enable differentiated products based on customer needs.
Features and benefits:
* Sitara AM335x ARM Cortex-A8 processors provide the necessary performance headroom for the complex routing algorithm in the data concentrator to connect with more than 1,000 e-meters.
* Flexible Sitara processor portfolio is scalable from 300MHz to 1GHz based on customers' performance and cost needs.
* Integrated communication interfaces include two Ethernet (MAC) ports, USB and up to eight UARTs for easy connectivity to other systems on the smart grid.
* Multiple PLC stacks for MAC and PHY layers let developers create designs that support PLC-Lite, PRIME, G3, IEEE-P1901.2.
* IPv4, IPv6 and 6LoWPAN protocols allow developers to connect their data concentrator products to a wide range of home and building automation applications.
* DLMS/COSEM applications standard, supported by third party Aricent, defines how the data concentrator will organize the metering data and how to send it back to the utility.
The TMDSDC-EVMAM335x Smart Data Concentrator Evaluation Module is available for $695.
GSA adds three members to board of directors
USA: The Global Semiconductor Alliance (GSA) announced the appointment of three new members to the GSA Board of Directors. The new members include David Baillie, CEO, CamSemi; Jeff Waters, senior VP and GM, Altera Corp. and Dr. Albert Wu, VP of Operations, Marvell Semiconductor Inc.
“I warmly welcome David, Jeff and Albert to the GSA Board,” said Jodi Shelton, co-founder and president of GSA. “I am honored to have these outstanding leaders join the board and look forward to their insight and contribution in the upcoming year.”
In his new position, Baillie has been appointed to represent emerging semiconductor companies. GSA is committed to reducing the barriers and improving the probabilities for success of emerging companies in the semiconductor industry. Baillie, a longtime GSA supporter, has been instrumental in leading the GSA EMEA Leadership Council and his vision and business acumen will add a unique emerging company perspective to the board.
“I am honored to join the GSA Board,” said Baillie. “I appreciate the work GSA has done and look forward to collaborating with my fellow board members to represent the challenges and issues facing the industry’s start-ups and emerging businesses.”
Baillie is CEO of CamSemi and has over 25 years of international experience in general management, marketing, sales and technical roles. He has worked in successful start-ups that have grown to be established companies such as LSI Logic and C-Cube Microsystems where he initially established their European operations before taking on executive management roles in the USA with worldwide responsibility. Baillie has a Master’s Degree in Microelectronics and Business Studies and a Bachelor’s degree in Applied Physics, both from Durham University, UK.
Jeff Waters from Altera will represent one of the semiconductor member positions. Altera has been a GSA member since 2006 and has held a board position since 2007. Altera is also a member of the GSA’s Technology Steering Committee.
“It is a privilege to be chosen as a member of the GSA board of directors. GSA is an important and unique voice in bringing industry leaders together in a collaborative environment to address challenges in the semiconductor industry,” said Waters. “I look forward to participating in the GSA’s work in advancing further collaboration and innovation in our dynamic and global sector.”
Jeff Waters joined Altera in January 2012 and serves as senior VP and GM of the Military, Industrial and Computing Division. Prior to that, he was with Texas Instruments/National Semiconductor as product line VP for the company’s Precision Signal Path Division. He was with National for 18 years in leadership positions, including VP of sales and marketing for Japan, and VP of worldwide marketing, as well as a variety of marketing and engineering management roles in analog and microprocessors.
In addition to his time at National, Waters held positions in management consulting as well as in research and development. He holds a BSEE from the University of Notre Dame, an MSEE from Santa Clara University, and an MBA from Northwestern University.
Dr. Albert Wu has rejoined the board and will serve as a semiconductor member. Marvell has been a longtime supporter and member of GSA since 1999 and held a board seat since 2006. Dr. Wu has served on the GSA Board in the past from 2006-2009, and his vast knowledge and support will provide the GSA with a unique market perspective and thought leadership making the board stronger and more diversified.
“It is my honor to re-join the GSA Board of Directors. Marvell has greatly benefited from being a member of GSA and I look forward to further contributing to the goals and principles of the organization to further guide GSA’s initiatives,” said Dr. Wu.
Dr. Wu joined Marvell Semiconductor, Inc. in August 1998 as the director of manufacturing technology, supervising test development, product engineering, foundry operations, and assembly engineering activities. In November 2001, he was appointed VP of operations of Marvell Semiconductor.
Before joining Marvell, Dr. Wu served in key manufacturing technology roles in several companies, including Silicon Spice Inc., Monolithic System Technologies Inc. and ISSI, after leaving an R&D position at Intel Corp. Dr. Wu holds a bachelor of science degree in electrical engineering from National Taiwan University and master of science and Ph.D. degrees in electrical engineering from the University of California at Berkeley.
“I warmly welcome David, Jeff and Albert to the GSA Board,” said Jodi Shelton, co-founder and president of GSA. “I am honored to have these outstanding leaders join the board and look forward to their insight and contribution in the upcoming year.”
In his new position, Baillie has been appointed to represent emerging semiconductor companies. GSA is committed to reducing the barriers and improving the probabilities for success of emerging companies in the semiconductor industry. Baillie, a longtime GSA supporter, has been instrumental in leading the GSA EMEA Leadership Council and his vision and business acumen will add a unique emerging company perspective to the board.
“I am honored to join the GSA Board,” said Baillie. “I appreciate the work GSA has done and look forward to collaborating with my fellow board members to represent the challenges and issues facing the industry’s start-ups and emerging businesses.”
Baillie is CEO of CamSemi and has over 25 years of international experience in general management, marketing, sales and technical roles. He has worked in successful start-ups that have grown to be established companies such as LSI Logic and C-Cube Microsystems where he initially established their European operations before taking on executive management roles in the USA with worldwide responsibility. Baillie has a Master’s Degree in Microelectronics and Business Studies and a Bachelor’s degree in Applied Physics, both from Durham University, UK.
Jeff Waters from Altera will represent one of the semiconductor member positions. Altera has been a GSA member since 2006 and has held a board position since 2007. Altera is also a member of the GSA’s Technology Steering Committee.
“It is a privilege to be chosen as a member of the GSA board of directors. GSA is an important and unique voice in bringing industry leaders together in a collaborative environment to address challenges in the semiconductor industry,” said Waters. “I look forward to participating in the GSA’s work in advancing further collaboration and innovation in our dynamic and global sector.”
Jeff Waters joined Altera in January 2012 and serves as senior VP and GM of the Military, Industrial and Computing Division. Prior to that, he was with Texas Instruments/National Semiconductor as product line VP for the company’s Precision Signal Path Division. He was with National for 18 years in leadership positions, including VP of sales and marketing for Japan, and VP of worldwide marketing, as well as a variety of marketing and engineering management roles in analog and microprocessors.
In addition to his time at National, Waters held positions in management consulting as well as in research and development. He holds a BSEE from the University of Notre Dame, an MSEE from Santa Clara University, and an MBA from Northwestern University.
Dr. Albert Wu has rejoined the board and will serve as a semiconductor member. Marvell has been a longtime supporter and member of GSA since 1999 and held a board seat since 2006. Dr. Wu has served on the GSA Board in the past from 2006-2009, and his vast knowledge and support will provide the GSA with a unique market perspective and thought leadership making the board stronger and more diversified.
“It is my honor to re-join the GSA Board of Directors. Marvell has greatly benefited from being a member of GSA and I look forward to further contributing to the goals and principles of the organization to further guide GSA’s initiatives,” said Dr. Wu.
Dr. Wu joined Marvell Semiconductor, Inc. in August 1998 as the director of manufacturing technology, supervising test development, product engineering, foundry operations, and assembly engineering activities. In November 2001, he was appointed VP of operations of Marvell Semiconductor.
Before joining Marvell, Dr. Wu served in key manufacturing technology roles in several companies, including Silicon Spice Inc., Monolithic System Technologies Inc. and ISSI, after leaving an R&D position at Intel Corp. Dr. Wu holds a bachelor of science degree in electrical engineering from National Taiwan University and master of science and Ph.D. degrees in electrical engineering from the University of California at Berkeley.
memsstar sells first memsstar systems in Korea and India
SCOTLAND: memsstar Ltd announced two strategic etch system order wins from new MEMS customers in Asia. memsstar recently shipped its memsstar R&D system to manufacturing customers in Korea and India for use in MEMS research and development, representing the first memsstar etch release system orders from these countries.
The R&D tool was selected by both customers for vapor phase isotropic etching of silicon for MEMS structures to support their new product development efforts. In addition to being ideally suited to R&D applications, all memsstar¹s processes are scalable for volume manufacturing using the same processing techniques, offering a seamless process transfer and lower cost of ownership from R&D through to full scale production.
"Our proprietary memsstar systems are aggressively positioned for growth, delivering critical technological differentiators to customers engaged in MEMS etch release and surface coatings," said Tony McKie, GM of memsstar. "Our advanced process capability is key to minimizing process limitations, in turn driving the next generation of structures for our customers. These new orders mark our entry into two important MEMS markets in Asia and reflect our ability to deliver and support our technology around the world."
memsstar's patented process is compatible with the widest wide range of metals especially Al/alloy and other metals commonly used in MEMS mirrors and electrical contacts, while the single wafer processing platform guarantees excellent release etch repeatability with a wide process window to maximize performance and yield. memsstar¹s dry release etch process using hydrogen fluoride (HF), or xenon difluoride (XeF2),is unique because of its ability to eliminate stiction in a single process.
memsstar processes are stable with excellent repeatability, tunable etch rates, high uniformity and selectivity. Coupled with the system¹s unique endpoint capability and thermal control of the wafer during the sacrificial etch process, memsstar systems ensure that each wafer receives the same etch process across a wide process window. The combination of these features allows customers to achieve high yield, highly repeatable processing to drive down manufacturing costs.
The R&D tool was selected by both customers for vapor phase isotropic etching of silicon for MEMS structures to support their new product development efforts. In addition to being ideally suited to R&D applications, all memsstar¹s processes are scalable for volume manufacturing using the same processing techniques, offering a seamless process transfer and lower cost of ownership from R&D through to full scale production.
"Our proprietary memsstar systems are aggressively positioned for growth, delivering critical technological differentiators to customers engaged in MEMS etch release and surface coatings," said Tony McKie, GM of memsstar. "Our advanced process capability is key to minimizing process limitations, in turn driving the next generation of structures for our customers. These new orders mark our entry into two important MEMS markets in Asia and reflect our ability to deliver and support our technology around the world."
memsstar's patented process is compatible with the widest wide range of metals especially Al/alloy and other metals commonly used in MEMS mirrors and electrical contacts, while the single wafer processing platform guarantees excellent release etch repeatability with a wide process window to maximize performance and yield. memsstar¹s dry release etch process using hydrogen fluoride (HF), or xenon difluoride (XeF2),is unique because of its ability to eliminate stiction in a single process.
memsstar processes are stable with excellent repeatability, tunable etch rates, high uniformity and selectivity. Coupled with the system¹s unique endpoint capability and thermal control of the wafer during the sacrificial etch process, memsstar systems ensure that each wafer receives the same etch process across a wide process window. The combination of these features allows customers to achieve high yield, highly repeatable processing to drive down manufacturing costs.
Tuesday, January 29, 2013
Synopsys announces energy-efficient 28-nm PCI Express 3.0 PHY with support for 10GBASE-KR
USA: Synopsys Inc. announced the availability of its multiprotocol DesignWare Enterprise 10G PHY IP to address the connectivity needs of a broad range of high-end, energy efficient networking and computing applications.
Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nanometer (nm) Enterprise 10G PHY supports multiple interface standards, including PCI Express (PCIe) 3.0 and 10GBASE-KR, for a flexible interconnect solution.
The new DesignWare IP also implements a multi-lane PHY architecture to support data rates from 1.25 Gbps to 10.3 Gbps per lane, with capabilities to aggregate to 40 Gbps and 100 Gbps Ethernet, giving designers a proven, scalable solution to address the growing demand for additional networking bandwidth in high-speed systems-on-chips (SoCs).
"As the fastest growing protocol in the enterprise and data center market, 10 Gigabit Ethernet is becoming a key backplane interface," said Jag Bolaria, senior analyst at The Linley Group.
"Our research indicates over 25 percent CAGR through 2016 in the number of 10 Gigabit Ethernet ports deployed in the enterprise and data centers. The growth of 10GBASE-KR ports, combined with the rapid adoption of integrated PCI Express 3.0 in multiprocessor cores, elevates the importance of Synopsys' multiprotocol SerDes IP for designers developing ASICs that embed high-speed interfaces."
The DesignWare Enterprise 10G PHY offers a modular design with a highly configurable physical coding sub-layer (PCS) capable of bifurcation and aggregation. Its analog front-end includes multi-tap decision feedback equalization (DFE) and continuous time linear equalization (CTLE), which enhance signal integrity in high throughput communication channels. The DesignWare Enterprise 10G PHY is optimized for area, power and width to ease integration into the rest of the SoC.
The Enterprise 10G PHY is part of Synopsys' complete PCI Express 3.0 and 10G Ethernet solutions, each of which include a PCS, controller and verification IP. The PHY's support for 10GBASE-KR includes physical medium attachment (PMA), auto negotiation (AN), PCS, forward error correction (FEC) and energy-efficient Ethernet (EEE). Providing comprehensive 10GBASE-KR support, including the optional EEE and FEC features, enables SoC designers to single-source IP solutions to help ensure interoperability while reducing risk and time-to-market.
"From the start, we designed the DesignWare Enterprise 10G PHY to enable a flexible range of implementations with scalable data rates, support all major networking and computing protocols, and be available at multiple leading foundries," said John Koeter, VP of marketing for IP and systems at Synopsys. "Synopsys' complete PCI Express 3.0 and 10G Ethernet IP solutions enable design teams to integrate ultra-high data throughput functionality into their devices with less risk and without compromising time-to-market."
Optimized for long backplane interfaces in server blade chassis, switches, routers and other high-performance computing and networking systems, the 28-nanometer (nm) Enterprise 10G PHY supports multiple interface standards, including PCI Express (PCIe) 3.0 and 10GBASE-KR, for a flexible interconnect solution.
The new DesignWare IP also implements a multi-lane PHY architecture to support data rates from 1.25 Gbps to 10.3 Gbps per lane, with capabilities to aggregate to 40 Gbps and 100 Gbps Ethernet, giving designers a proven, scalable solution to address the growing demand for additional networking bandwidth in high-speed systems-on-chips (SoCs).
"As the fastest growing protocol in the enterprise and data center market, 10 Gigabit Ethernet is becoming a key backplane interface," said Jag Bolaria, senior analyst at The Linley Group.
"Our research indicates over 25 percent CAGR through 2016 in the number of 10 Gigabit Ethernet ports deployed in the enterprise and data centers. The growth of 10GBASE-KR ports, combined with the rapid adoption of integrated PCI Express 3.0 in multiprocessor cores, elevates the importance of Synopsys' multiprotocol SerDes IP for designers developing ASICs that embed high-speed interfaces."
The DesignWare Enterprise 10G PHY offers a modular design with a highly configurable physical coding sub-layer (PCS) capable of bifurcation and aggregation. Its analog front-end includes multi-tap decision feedback equalization (DFE) and continuous time linear equalization (CTLE), which enhance signal integrity in high throughput communication channels. The DesignWare Enterprise 10G PHY is optimized for area, power and width to ease integration into the rest of the SoC.
The Enterprise 10G PHY is part of Synopsys' complete PCI Express 3.0 and 10G Ethernet solutions, each of which include a PCS, controller and verification IP. The PHY's support for 10GBASE-KR includes physical medium attachment (PMA), auto negotiation (AN), PCS, forward error correction (FEC) and energy-efficient Ethernet (EEE). Providing comprehensive 10GBASE-KR support, including the optional EEE and FEC features, enables SoC designers to single-source IP solutions to help ensure interoperability while reducing risk and time-to-market.
"From the start, we designed the DesignWare Enterprise 10G PHY to enable a flexible range of implementations with scalable data rates, support all major networking and computing protocols, and be available at multiple leading foundries," said John Koeter, VP of marketing for IP and systems at Synopsys. "Synopsys' complete PCI Express 3.0 and 10G Ethernet IP solutions enable design teams to integrate ultra-high data throughput functionality into their devices with less risk and without compromising time-to-market."
Microchip launches world's first analog-based power management controller with integrated MCU
USA: Microchip Technology Inc. announced the MCP19111, the world's first digitally enhanced power analog controller, which expands its diverse range of intelligent DC/DC power-conversion solutions.
Microchip also announced the expansion of its high-speed MOSFET family, with the new MCP87018, MCP87030, MCP87090 and MCP87130. These are 25V-rated, 1.8 mΩ, 3 mΩ, 9 mΩ and 13 mΩ logic-level MOSFETs that are optimised specifically for Switched-Mode-Power-Supply (SMPS) applications.
The MCP19111 Digitally Enhanced Power Analog controller, a new hybrid, digital and analog power-management device, in combination with the expanded MCP87XXX family of low-Figure-of-Merit (FOM) MOSFETs, supports configurable, high-efficiency DC/DC power-conversion designs for a broad array of consumer and industrial applications.
The MCP19111 Digitally Enhanced Power Analog family operates across a wide voltage range of 4.5 to 32V and offers a significant increase in flexibility over conventional analog-based solutions. In fact, the MCP19111 offers the world's first hybrid, mixed-signal power-management controller, integrating an analog-based PWM controller with a fully functional Flash-based microcontroller.
This integration offers the flexibility of a digital solution, with the speed, performance and resolution of an analog-based controller. The MCP19111 devices support operation up to 32V, and have integrated MOSFET drivers configured for synchronous, step-down applications. When combined with Microchip's expanded family of high-speed MOSFETs, the MCP19111 drives customisable, high-efficiency power conversion.
Microchip also announced the expansion of its high-speed MOSFET family, with the new MCP87018, MCP87030, MCP87090 and MCP87130. These are 25V-rated, 1.8 mΩ, 3 mΩ, 9 mΩ and 13 mΩ logic-level MOSFETs that are optimised specifically for Switched-Mode-Power-Supply (SMPS) applications.
The MCP19111 Digitally Enhanced Power Analog controller, a new hybrid, digital and analog power-management device, in combination with the expanded MCP87XXX family of low-Figure-of-Merit (FOM) MOSFETs, supports configurable, high-efficiency DC/DC power-conversion designs for a broad array of consumer and industrial applications.
The MCP19111 Digitally Enhanced Power Analog family operates across a wide voltage range of 4.5 to 32V and offers a significant increase in flexibility over conventional analog-based solutions. In fact, the MCP19111 offers the world's first hybrid, mixed-signal power-management controller, integrating an analog-based PWM controller with a fully functional Flash-based microcontroller.
This integration offers the flexibility of a digital solution, with the speed, performance and resolution of an analog-based controller. The MCP19111 devices support operation up to 32V, and have integrated MOSFET drivers configured for synchronous, step-down applications. When combined with Microchip's expanded family of high-speed MOSFETs, the MCP19111 drives customisable, high-efficiency power conversion.
Imec, Qualcomm extend R&D collaboration
BELGIUM & USA: Nanoelectronics research centre, imec, and Qualcomm Technologies Inc. announced an extended collaboration agreement to accelerate scaling technologies for logic and memory devices.
The first fabless integrated circuit company to become a core partner of imec, Qualcomm Technologies will gain comprehensive insight into all advanced process technologies under investigation at imec to help shape future product roadmaps.
Increasingly, it is challenging to design advanced systems and applications for each new technology node. By gaining early information on CMOS advancements, the product design community in IDMs, fabless, fablite and system-design companies can better anticipate the future impact and potential of new technologies to shape development efforts.
“We continue to invest heavily into technology leadership which includes advanced semiconductor technologies” said Jim Thompson, executive VP of engineering at Qualcomm Technologies. “We have collaborated with imec on the 3D stacking program for the last four years and we look forward to expanding our engagement with imec to include CMOS research and the new MRAM program. Early engagement on new microelectronic technologies with imec enables Qualcomm to deepen the co-optimization of product architecture and technology while mitigating new technology risk in collaboration with our supply partners.”
Imec offers R&D program members comprehensive insight into future IC technologies, which aren’t widely available to the industry yet. This enables participating fabless and fablite organizations to stay at the forefront of next-generation semiconductor manufacturing and design. Program members are able to provide early feedback toward technology specification, make timely architectural design changes, and adopt new technology faster with reduced risks.
“Strong collaboration between foundries, IDMs, fabless and fablite companies, packaging and assembly companies, and equipment and material suppliers at imec play a critical role in pushing forward the development of innovative solutions,” stated Luc Van den hove, president and CEO at imec. “A true win-win situation, we are confident our new broadened collaboration agreement with Qualcomm will continue to pay dividends in the future.”
The first fabless integrated circuit company to become a core partner of imec, Qualcomm Technologies will gain comprehensive insight into all advanced process technologies under investigation at imec to help shape future product roadmaps.
Increasingly, it is challenging to design advanced systems and applications for each new technology node. By gaining early information on CMOS advancements, the product design community in IDMs, fabless, fablite and system-design companies can better anticipate the future impact and potential of new technologies to shape development efforts.
“We continue to invest heavily into technology leadership which includes advanced semiconductor technologies” said Jim Thompson, executive VP of engineering at Qualcomm Technologies. “We have collaborated with imec on the 3D stacking program for the last four years and we look forward to expanding our engagement with imec to include CMOS research and the new MRAM program. Early engagement on new microelectronic technologies with imec enables Qualcomm to deepen the co-optimization of product architecture and technology while mitigating new technology risk in collaboration with our supply partners.”
Imec offers R&D program members comprehensive insight into future IC technologies, which aren’t widely available to the industry yet. This enables participating fabless and fablite organizations to stay at the forefront of next-generation semiconductor manufacturing and design. Program members are able to provide early feedback toward technology specification, make timely architectural design changes, and adopt new technology faster with reduced risks.
“Strong collaboration between foundries, IDMs, fabless and fablite companies, packaging and assembly companies, and equipment and material suppliers at imec play a critical role in pushing forward the development of innovative solutions,” stated Luc Van den hove, president and CEO at imec. “A true win-win situation, we are confident our new broadened collaboration agreement with Qualcomm will continue to pay dividends in the future.”
China’s IC market growth continues to outpace IC manufacturing
USA: IC Insights’ 2013 edition of The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry contains over 500 pages and 400 tables and graphs has been released and is available for purchase.
China’s IC market is forecast to continue growing at a strong rate through 2017—faster than the growth rate of the worldwide IC market—according to IC Insights’ latest forecast contained in the pages of
The 2013 McClean Report. The Chinese IC market is forecast to have a 2012-2017 CAGR of 13 percent, five points higher than the 8 percent CAGR forecast for the total IC market during this same time period.
China’s IC market is expected to reach over $100 billion for the first time in 2014 and almost $150 billion in 2017. In 2017, China is expected to represent 38 percent of the worldwide IC market, up from 23 percent, 10 years earlier in 2007.
A very clear distinction should be made between the IC market in China and indigenous IC production in China. As IC Insights has oftentimes stated, although China has been the largest consuming country for ICs since 2005, it does not necessarily mean that large increases in IC production within China will immediately, or ever, follow.
As shown, IC production in China represented only 11.2 percent of its $81 billion IC market in 2012. Moreover, IC Insights forecasts that this share will increase only about two points to 13.1 percent in 2017.
Overall, China-based IC production is forecast to exhibit a very strong 2012-2017 CAGR of 16.5 percent. However, considering that China-based IC production was only about $9.1 billion in 2012, this growth will come off a relatively small base. If China-based IC production rises to $19.5 billion in 2017, it would represent only about 5 percent of the total forecasted worldwide IC market of $389.3 billion in 2017.
In 2012, SK Hynix, TSMC, and Intel were the only foreign IC manufacturers that had significant IC production in China. In fact, SK Hynix’s China fab had the most capacity of any of its fabs in 2012.
Last year, Intel continued to ramp-up its 300mm fab in Dalian, China (it started production in late October 2010), which is expected to give a noticeable boost to the China-based IC production figures over the next few years (the fab currently has an installed capacity of 30,000 300mm wafers per month with a maximum capacity of 52,000 wafers per month).
In early January of 2012, it was reported that Samsung gained approval from the South Korean government to construct a 300mm IC fabrication facility to produce NAND flash memory in in Xian, China. Samsung started construction of the fab in September of 2012 with production set to begin in the first half of 2014.
The company expects to invest $2.3 billion in the first phase of the fab with $7.0 billion budgeted in total. This facility is targeting NAND flash production using 10-19nm feature sizes.
Historically, the lack of consistent intellectual property protection has been a major deterrent for foreign firms seeking to establish state-of-the-art IC fabrication facilities in China. In fact, Samsung’s 300mm NAND flash memory fab in China in 2014 will be the first IC production fab in the country to incorporate state-of-the-art IC technology!
IC Insights believes that the future size of the IC production base in China is more dependent upon whether foreign companies (e.g., SK Hynix, TSMC, Intel, Samsung, etc.) continue to locate, or re-locate, IC fabrication facilities in China than on the success of indigenous Chinese IC producers (e.g., SMIC, Hua Hong Grace, etc.). As a result, IC Insights forecasts that at least 70 percent of IC production in China in 2017 will come from foreign companies such as SK Hynix, Intel, TSMC, and Samsung.
China’s IC market is forecast to continue growing at a strong rate through 2017—faster than the growth rate of the worldwide IC market—according to IC Insights’ latest forecast contained in the pages of
The 2013 McClean Report. The Chinese IC market is forecast to have a 2012-2017 CAGR of 13 percent, five points higher than the 8 percent CAGR forecast for the total IC market during this same time period.
China’s IC market is expected to reach over $100 billion for the first time in 2014 and almost $150 billion in 2017. In 2017, China is expected to represent 38 percent of the worldwide IC market, up from 23 percent, 10 years earlier in 2007.
As shown, IC production in China represented only 11.2 percent of its $81 billion IC market in 2012. Moreover, IC Insights forecasts that this share will increase only about two points to 13.1 percent in 2017.
In 2012, SK Hynix, TSMC, and Intel were the only foreign IC manufacturers that had significant IC production in China. In fact, SK Hynix’s China fab had the most capacity of any of its fabs in 2012.
Last year, Intel continued to ramp-up its 300mm fab in Dalian, China (it started production in late October 2010), which is expected to give a noticeable boost to the China-based IC production figures over the next few years (the fab currently has an installed capacity of 30,000 300mm wafers per month with a maximum capacity of 52,000 wafers per month).
In early January of 2012, it was reported that Samsung gained approval from the South Korean government to construct a 300mm IC fabrication facility to produce NAND flash memory in in Xian, China. Samsung started construction of the fab in September of 2012 with production set to begin in the first half of 2014.
The company expects to invest $2.3 billion in the first phase of the fab with $7.0 billion budgeted in total. This facility is targeting NAND flash production using 10-19nm feature sizes.
Historically, the lack of consistent intellectual property protection has been a major deterrent for foreign firms seeking to establish state-of-the-art IC fabrication facilities in China. In fact, Samsung’s 300mm NAND flash memory fab in China in 2014 will be the first IC production fab in the country to incorporate state-of-the-art IC technology!
IC Insights believes that the future size of the IC production base in China is more dependent upon whether foreign companies (e.g., SK Hynix, TSMC, Intel, Samsung, etc.) continue to locate, or re-locate, IC fabrication facilities in China than on the success of indigenous Chinese IC producers (e.g., SMIC, Hua Hong Grace, etc.). As a result, IC Insights forecasts that at least 70 percent of IC production in China in 2017 will come from foreign companies such as SK Hynix, Intel, TSMC, and Samsung.
JDSU adopts Altera Stratix V GT FPGA for production of next-gen optical testers
HONG KONG: Altera Corp. announced the Stratix V GT FPGA is shipping to JDSU for volume production of the company’s next-generation Optical Network Tester (ONT) solutions.
JDSU, a leading provider of optical products and test and measurement solutions for the communications industry, is leveraging Altera’s high-end 28 nm FPGA in its ONT-600 series to deliver the first test solution targeting CFP2 100G optical transport network (OTN) environments. The Stratix V GT FPGA is the industry’s only production-qualified FPGA available today that integrates 28.05 Gbps transceivers monolithically, offering customers superior signal integrity and reducing design complexity.
The Stratix V GT FPGA supports the rapid growth in network traffic being driven by Internet and IP-based services and applications. Companies like JDSU leverage solutions from Altera to get the earliest access to the most advanced technologies for use in their next-generation test and measurement solutions.
The 28.05 Gbps transceivers featured in the Stratix V GT FPGA deliver the highest system bandwidth at the lowest power consumption while complying with the latest Optical Internetworking Forum (OIF) 100G standards.
“JDSU is on the leading edge of providing advanced testing solutions that enable networking companies and carriers to keep pace with the high-speed evolution of communications technologies. Working with Altera has enabled us to deliver the solutions our customers want at the right time," said Paul Brooks, product line manager in JDSU’s communications test and measurement business segment.
"Leveraging Altera’s production-ready Stratix V GT FPGA in our latest ONT-600 family of testers allows our customers to bring to market the next generation of 100G solutions based on 25G/28G I/O.”
JDSU’s ONT-600 platform is a multifunctional and multiport solution for testing OTN environments. The interchangeable Stratix V GT FPGA-based plug-in modules within the ONT-600 family provide customers flexibility by enabling a single platform to support multiple technologies, including Ethernet, OTN, jitter/wander, SDH/SONET, VCat, GFP, Fibre Channel and 40G/100G CFP.
The ONT-600 family’s plug-in modules address the optical and digital testing needs in research and development, system verification testing, production and troubleshooting.
“The Stratix V GT FPGA is built to support the evolution of OTN infrastructure, which faces bandwidth exhaustion as existing solutions approach their maximum capacity,” said Jordon Inkeles, senior product marketing manager at Altera.
“Our latest OTN solutions are built on the industry’s highest performance 28 nm FPGAs and provide leading-edge companies like JDSU the only production-qualified 28 Gbps FPGA platform that includes hardened IP, programmable logic, and OTN processing in a monolithic die. Our Stratix V GT FPGA delivers superior signal integrity for the highest performance, lowest power OTN deployments.”
The Stratix V GT FPGA supports the rapid growth in network traffic being driven by Internet and IP-based services and applications. Companies like JDSU leverage solutions from Altera to get the earliest access to the most advanced technologies for use in their next-generation test and measurement solutions.
The 28.05 Gbps transceivers featured in the Stratix V GT FPGA deliver the highest system bandwidth at the lowest power consumption while complying with the latest Optical Internetworking Forum (OIF) 100G standards.
“JDSU is on the leading edge of providing advanced testing solutions that enable networking companies and carriers to keep pace with the high-speed evolution of communications technologies. Working with Altera has enabled us to deliver the solutions our customers want at the right time," said Paul Brooks, product line manager in JDSU’s communications test and measurement business segment.
"Leveraging Altera’s production-ready Stratix V GT FPGA in our latest ONT-600 family of testers allows our customers to bring to market the next generation of 100G solutions based on 25G/28G I/O.”
JDSU’s ONT-600 platform is a multifunctional and multiport solution for testing OTN environments. The interchangeable Stratix V GT FPGA-based plug-in modules within the ONT-600 family provide customers flexibility by enabling a single platform to support multiple technologies, including Ethernet, OTN, jitter/wander, SDH/SONET, VCat, GFP, Fibre Channel and 40G/100G CFP.
The ONT-600 family’s plug-in modules address the optical and digital testing needs in research and development, system verification testing, production and troubleshooting.
“The Stratix V GT FPGA is built to support the evolution of OTN infrastructure, which faces bandwidth exhaustion as existing solutions approach their maximum capacity,” said Jordon Inkeles, senior product marketing manager at Altera.
“Our latest OTN solutions are built on the industry’s highest performance 28 nm FPGAs and provide leading-edge companies like JDSU the only production-qualified 28 Gbps FPGA platform that includes hardened IP, programmable logic, and OTN processing in a monolithic die. Our Stratix V GT FPGA delivers superior signal integrity for the highest performance, lowest power OTN deployments.”
Valens announce reference design for transmission of Display Port over HDBaseT
Integrated Systems Europe 2013, ISRAEL: Valens has developed a new reference design solution for transmitting Display Port audio and video over HDBaseT together with ST Microelectronics. The solution will be demonstrated this week at the HDBaseT Alliance's booth at the Integrated Systems Europe 2013 conference (Hall 7, Booth #7C171).
The HDBaseT technology features the unique 5Play feature set that enables the delivery of uncompressed high definition video, audio, Internet, controls and power over a single cat5e/6 cable up to 100 meters, eliminating the common issues professional installers face concerning cable distance and location of available power outlets.
Until now, HDBaseT products were mainly transmitting HDMI and/or DVI. The new ST-Valens solution provides professional installers and systems integrators with the flexibility of being able to use the commonly-used Display Port interface.
Valens developed this solution in response to the growing demand for display port solutions, enabling customers to benefit HDBaseT’s convergence and long distance capabilities with Display Port.
The new Display Port over HDBaseT reference design solution uses ST DP2650 and STDP2600 chipset and Valens’ VS100 chipset to transmit uncompressed video and audio over a single CAT5e/6 cable. It facilitates the transmission of Display port over long distances, in a simple, plug-and-play manner.
The HDBaseT technology features the unique 5Play feature set that enables the delivery of uncompressed high definition video, audio, Internet, controls and power over a single cat5e/6 cable up to 100 meters, eliminating the common issues professional installers face concerning cable distance and location of available power outlets.
Until now, HDBaseT products were mainly transmitting HDMI and/or DVI. The new ST-Valens solution provides professional installers and systems integrators with the flexibility of being able to use the commonly-used Display Port interface.
Valens developed this solution in response to the growing demand for display port solutions, enabling customers to benefit HDBaseT’s convergence and long distance capabilities with Display Port.
The new Display Port over HDBaseT reference design solution uses ST DP2650 and STDP2600 chipset and Valens’ VS100 chipset to transmit uncompressed video and audio over a single CAT5e/6 cable. It facilitates the transmission of Display port over long distances, in a simple, plug-and-play manner.
MEMS Industry Group announces MEMS Executive Congress Europe 2013
USA: MEMS Industry Group (MIG) will host its second annual MEMS Executive Congress Europe, March 12, 2013 in Amsterdam.
This European edition of MIG’s highly successful executive event features an opening presentation by MIG Managing Director Karen Lightman, keynotes by Continental Automotive GmbH and SORIN GROUP, and panels exploring micro-electromechanical systems (MEMS) as a core enabling technology in both established and emerging markets.
“European companies and research organizations are breaking new ground in mobile communications, automotive systems, energy production and conservation, and medical/quality of life applications for aging populations—and a share of the astounding progress they are making is attributable to MEMS,” said Karen Lightman, managing director, MEMS Industry Group.
“MEMS Executive Congress Europe allows the global MEMS community to tap into the expertise of some of the top European minds in these growing fields. It is a forum for exchanging vital information about business and market challenges and opportunities in using MEMS for life-improving and life-changing applications.”
This European edition of MIG’s highly successful executive event features an opening presentation by MIG Managing Director Karen Lightman, keynotes by Continental Automotive GmbH and SORIN GROUP, and panels exploring micro-electromechanical systems (MEMS) as a core enabling technology in both established and emerging markets.
“European companies and research organizations are breaking new ground in mobile communications, automotive systems, energy production and conservation, and medical/quality of life applications for aging populations—and a share of the astounding progress they are making is attributable to MEMS,” said Karen Lightman, managing director, MEMS Industry Group.
“MEMS Executive Congress Europe allows the global MEMS community to tap into the expertise of some of the top European minds in these growing fields. It is a forum for exchanging vital information about business and market challenges and opportunities in using MEMS for life-improving and life-changing applications.”
Pericom launches HiFlex clock generator family
USA: Pericom Semiconductor Corp. has introduced a new family of HiFlex clock generators offering multiple frequency outputs with very low jitter, high integration, and high flexibility - perfect for use in networking, cloud computing, and other high performance platforms that require multiple frequencies and outputs.
The new HiFlex clock generator family is designed to drive down the Bill of Materials (BOM) cost and to increase board space utilization of the timing tree. By integrating multiple components of a timing tree into a single clock generator IC, instead of using crystal oscillators (XOs) and fan out buffers, Pericom’s family of HiFlex clock generators enables cost savings without sacrificing the necessary performance of customer designs.
One of the main drivers of growth today in the networking segment is the growth in cloud computing and services. According to Forrester Research, cloud computing is projected to be a $241 billion market by 2020 and the infrastructure market has a significant portion of it.
Pericom’s HiFlex clocks can provide the high performance timing needed for infrastructure, enterprise networking, and data center servers that are part of the cloud-computing ecosystem. Various Tier 1 networking system manufacturers in North America, Asia and Japan have already deployed this family of innovative products in their equipment.
“Timing is absolutely critical in high performance systems to ensure everything is in sync,” said Wendy Zhou, marketing director for Pericom’s Timing group. “Traditional XOs can provide very good jitter performance, but lack flexibility in terms of output frequency, number of outputs, and also increase board space and costs. Pericom’s HiFlex clock family provides a better alternative to system engineers who want a simple and easy design clock tree that meets all performance requirements.”
Key features and benefits of the HiFlex clock IC family include: multiple frequency outputs specific to key protocols, user programmable frequencies across different output protocol types via pin strapping or I2C, jitter performance comparable to traditional XO products, and reduced BOM cost and board space.
The new HiFlex clock generator family is designed to drive down the Bill of Materials (BOM) cost and to increase board space utilization of the timing tree. By integrating multiple components of a timing tree into a single clock generator IC, instead of using crystal oscillators (XOs) and fan out buffers, Pericom’s family of HiFlex clock generators enables cost savings without sacrificing the necessary performance of customer designs.
One of the main drivers of growth today in the networking segment is the growth in cloud computing and services. According to Forrester Research, cloud computing is projected to be a $241 billion market by 2020 and the infrastructure market has a significant portion of it.
Pericom’s HiFlex clocks can provide the high performance timing needed for infrastructure, enterprise networking, and data center servers that are part of the cloud-computing ecosystem. Various Tier 1 networking system manufacturers in North America, Asia and Japan have already deployed this family of innovative products in their equipment.
“Timing is absolutely critical in high performance systems to ensure everything is in sync,” said Wendy Zhou, marketing director for Pericom’s Timing group. “Traditional XOs can provide very good jitter performance, but lack flexibility in terms of output frequency, number of outputs, and also increase board space and costs. Pericom’s HiFlex clock family provides a better alternative to system engineers who want a simple and easy design clock tree that meets all performance requirements.”
Key features and benefits of the HiFlex clock IC family include: multiple frequency outputs specific to key protocols, user programmable frequencies across different output protocol types via pin strapping or I2C, jitter performance comparable to traditional XO products, and reduced BOM cost and board space.
Intel intros mSATA SSD for ultrabook and low-power embedded apps
USA: Intel Corp. announced the Intel Solid-State Drive 525 Series (Intel SSD 525 Series) in a small mSATA form factor with 6-gigabit-per-second (Gb/s) performance.
The Intel SSD 525 Series gives OEM customers, channel and tech enthusiasts an ultra-portable, low-power storage solution in one-eighth the space of a traditional 2.5-inch hard disk drive (HDD) to drive innovative Ultrabook™, tablet and embedded applications.
The Intel SSD 525 is the latest entry to the Intel 500 Series SSD Family aimed at higher-performance, enthusiast solutions. Measuring 3.7mm x 50.8mm x 29.85mm and weighing 10 grams, the mSATA with PCI Express (PCIe) mini-connector delivers the performance of the company’s Intel SSD 520 Series client drive. This makes the Intel SSD 525 suitable for All-in-One desktops, notebooks, Ultrabooks and workstation upgrades, as well as automotive, digital signage, embedded video and retail solutions.
With random read performance of up to 50,000 input/output operations per second (IOPS) and sequential read performance up to 550 megabytes per second (MB/s), systems using the Intel SSD 525 Series will receive a performance boost for the most demanding applications and intense multi-tasking needs. This is coupled with random write performance of up to 80,000 IOPS and sequential writes of 520 MB/s to deliver a top-performing mSATA SSD.
“The Intel SSD 525 Series is Intel’s latest 6 Gb/s mSATA product, which brings high performance to an ultra-portable form factor targeted for Ultrabooks and a myriad of embedded solutions,” said James Slattery, product line manager for Intel Non-Volatile Memory Solutions Group Client SSDs.
“Intel SSDs reduce the risk of data loss due to shock, vibration or jarring. With these new performance thresholds available in a small form factor package, and backed by Intel quality and reliability, the Intel SSD 525 opens the door to an unlimited number of creative embedded solutions such as in-flight entertainment, mobile workstations, microservers and IP phone storage.”
The Intel SSD 525 Series will be available in 30 gigabyte (GB), 60GB, 90GB, 120GB, 180GB and 240GB capacities. The company has begun shipping the 120GB and 180GB options, with additional capacities and volume shipments to follow this quarter.
The Intel SSD 525 Series features Advanced Encryption Standard (AES) 128-bit encryption capabilities for added data protection should a device be stolen or lost. It uses Intel 25-nanometer (nm) multi-level cell (MLC) NAND flash memory and is backed by a 5-year limited warranty.
Also available for Intel SSD purchasers is the Intel SSD Toolbox with Intel SSD Optimizer, a free utility that provides Microsoft Windows* users with a powerful set of management, information and diagnostic tools to help maintain the health and out-of-box performance of the drive. Available in 11 languages, the Intel SSD Toolbox is also Windows 8-compatible.
The Intel SSD 525 Series gives OEM customers, channel and tech enthusiasts an ultra-portable, low-power storage solution in one-eighth the space of a traditional 2.5-inch hard disk drive (HDD) to drive innovative Ultrabook™, tablet and embedded applications.
The Intel SSD 525 is the latest entry to the Intel 500 Series SSD Family aimed at higher-performance, enthusiast solutions. Measuring 3.7mm x 50.8mm x 29.85mm and weighing 10 grams, the mSATA with PCI Express (PCIe) mini-connector delivers the performance of the company’s Intel SSD 520 Series client drive. This makes the Intel SSD 525 suitable for All-in-One desktops, notebooks, Ultrabooks and workstation upgrades, as well as automotive, digital signage, embedded video and retail solutions.
With random read performance of up to 50,000 input/output operations per second (IOPS) and sequential read performance up to 550 megabytes per second (MB/s), systems using the Intel SSD 525 Series will receive a performance boost for the most demanding applications and intense multi-tasking needs. This is coupled with random write performance of up to 80,000 IOPS and sequential writes of 520 MB/s to deliver a top-performing mSATA SSD.
“The Intel SSD 525 Series is Intel’s latest 6 Gb/s mSATA product, which brings high performance to an ultra-portable form factor targeted for Ultrabooks and a myriad of embedded solutions,” said James Slattery, product line manager for Intel Non-Volatile Memory Solutions Group Client SSDs.
“Intel SSDs reduce the risk of data loss due to shock, vibration or jarring. With these new performance thresholds available in a small form factor package, and backed by Intel quality and reliability, the Intel SSD 525 opens the door to an unlimited number of creative embedded solutions such as in-flight entertainment, mobile workstations, microservers and IP phone storage.”
The Intel SSD 525 Series will be available in 30 gigabyte (GB), 60GB, 90GB, 120GB, 180GB and 240GB capacities. The company has begun shipping the 120GB and 180GB options, with additional capacities and volume shipments to follow this quarter.
The Intel SSD 525 Series features Advanced Encryption Standard (AES) 128-bit encryption capabilities for added data protection should a device be stolen or lost. It uses Intel 25-nanometer (nm) multi-level cell (MLC) NAND flash memory and is backed by a 5-year limited warranty.
Also available for Intel SSD purchasers is the Intel SSD Toolbox with Intel SSD Optimizer, a free utility that provides Microsoft Windows* users with a powerful set of management, information and diagnostic tools to help maintain the health and out-of-box performance of the drive. Available in 11 languages, the Intel SSD Toolbox is also Windows 8-compatible.
Monday, January 28, 2013
Cadence unveils Virtuoso advanced node for 20nm design
DESIGNCON, USA: Cadence Design Systems Inc. announced the availability of Virtuoso Advanced Node, a new set of breakthrough custom/analog capabilities designed specifically for the advanced technology nodes of 20 nanometers and below.
Built on the industry-leading Cadence® Virtuoso custom/analog technology, Virtuoso Advanced Node features unique and innovative capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of complex mixed-signal chips that power today’s leading consumer electronics devices.
The new and advanced Virtuoso technologies address the toughest challenges facing engineers, including layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. They integrate seamlessly with the Cadence Integrated Physical Verification System (IPVS) — a foundry-qualified technology for signoff DRC and DPT checking — to conduct on-the-fly checks that reduce layout iterations.
“As a semiconductor leader, we have moved aggressively to meet the new complexities of 20-nanometer technology to stay on the cutting edge of design,” said Pierre Dautriche, senior director at STMicroelectronics. “The new Virtuoso advanced-node capabilities have contributed to our transition by providing high-quality automation for our custom/analog chips. Virtuoso Advanced Node takes into account the idiosyncrasies of designing at 20 nanometers and ensures a much more efficient development cycle.”
Features and capabilities:
LDE analysis using incremental layout -- Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end. It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle.
LDEs — such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics -- are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.
When this technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time. By methodically building and checking the design, the designer should eliminate massive “rip ups” and “reroutes” that can be found at the end if the circuit wasn’t checked along the way.
Double patterning and color-aware layout—Double patterning, a manufacturing requirement at 20 nanometers, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “coloring” challenges to designers.
Virtuoso Advanced Node delivers real-time automated color-aware, design-rule-driven layout to enable the creation of area-optimized layout. It provides engineers the ability to match, lock and store colors on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix.
New routing layers—Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors.
Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.
Developed specifically for the most cutting-edge designs, the Virtuoso Advanced Node options do not replace the industry-leading 6.x version of the Virtuoso technology, which targets mature and mainstream geometries, and which will continue to be enhanced by Cadence.
“Moving to smaller geometries always creates new obstacles, but the move to 20 nanometers has been especially challenging for our customers, many of whom are reporting that layout is taking two to five times as long as for 28 nanometers on the same circuit,” said Dr. Chi-Ping Hsu, senior VP, Silicon Realization Group at Cadence.
“Virtuoso Advanced Node enables design teams to optimize their designs for performance, power and area while reducing or even eliminating tasks that would make 20-nanometer design much more time consuming and labor intensive.”
Built on the industry-leading Cadence® Virtuoso custom/analog technology, Virtuoso Advanced Node features unique and innovative capabilities that prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of complex mixed-signal chips that power today’s leading consumer electronics devices.
The new and advanced Virtuoso technologies address the toughest challenges facing engineers, including layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. They integrate seamlessly with the Cadence Integrated Physical Verification System (IPVS) — a foundry-qualified technology for signoff DRC and DPT checking — to conduct on-the-fly checks that reduce layout iterations.
“As a semiconductor leader, we have moved aggressively to meet the new complexities of 20-nanometer technology to stay on the cutting edge of design,” said Pierre Dautriche, senior director at STMicroelectronics. “The new Virtuoso advanced-node capabilities have contributed to our transition by providing high-quality automation for our custom/analog chips. Virtuoso Advanced Node takes into account the idiosyncrasies of designing at 20 nanometers and ensures a much more efficient development cycle.”
Features and capabilities:
LDE analysis using incremental layout -- Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end. It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle.
LDEs — such as stress effects, poly and diffusion spacing/length, well proximity effects, and parasitics -- are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.
When this technique is combined with Cadence MODGENs and constraints, IPVS and final hotspot detection and correction with Virtuoso DFM, users can expect up to a 30 percent improvement in their overall verification time. By methodically building and checking the design, the designer should eliminate massive “rip ups” and “reroutes” that can be found at the end if the circuit wasn’t checked along the way.
Double patterning and color-aware layout—Double patterning, a manufacturing requirement at 20 nanometers, splits the design layers into two masks, separating structures that are too close together. But double patterning brings “coloring” challenges to designers.
Virtuoso Advanced Node delivers real-time automated color-aware, design-rule-driven layout to enable the creation of area-optimized layout. It provides engineers the ability to match, lock and store colors on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix.
New routing layers—Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors.
Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.
Developed specifically for the most cutting-edge designs, the Virtuoso Advanced Node options do not replace the industry-leading 6.x version of the Virtuoso technology, which targets mature and mainstream geometries, and which will continue to be enhanced by Cadence.
“Moving to smaller geometries always creates new obstacles, but the move to 20 nanometers has been especially challenging for our customers, many of whom are reporting that layout is taking two to five times as long as for 28 nanometers on the same circuit,” said Dr. Chi-Ping Hsu, senior VP, Silicon Realization Group at Cadence.
“Virtuoso Advanced Node enables design teams to optimize their designs for performance, power and area while reducing or even eliminating tasks that would make 20-nanometer design much more time consuming and labor intensive.”
Rambus intros R+ LPDDR3 memory architecture solution
USA: Rambus Inc. announced its first LPDDR3 offering targeted at the mobile industry. In the Rambus R+ solution set, the R+ LPDDR3 memory architecture is fully compatible with industry standards while providing improved power and performance.
This allows customers to differentiate their products in a cost-effective manner with improved time-to-market. Further helping improve design and development cycles, the R+ LPDDR3 is also available with Rambus’ collaborative design and integration services.
The R+ LPDDR3 architecture includes both a controller and a DRAM interface and can reduce active memory system power by up to 25% and supports data rates of up to 3200 megabits per second (Mbps), which is double the performance of existing LPDDR3 technologies. These improvements to power efficiency and performance enable longer battery life and enhanced mobile device functionality for streaming HD video, gaming and data-intensive apps.
“Each generation of mobile devices demands even higher performance with lower power. The R+ LPDDR3 technology enables the mobile market to use our controller and DRAM solutions to provide unprecedented levels of performance, with a significant power savings,” said Kevin Donnelly, senior VP and GM of the Memory and Interface Division at Rambus.
“Since this technology is a part of our R+ platform, beyond the improvements in power and performance, we’re also maintaining compatibility with today’s standards to ensure our customers have all the benefits of the Rambus’ superior technology with reduced adoption risk.”
The seed to the improved power and performance offered by the R+ LPDDR3 architecture is a low-swing implementation of the Rambus Near Ground Signaling technology. Essentially, this single-ended, ground-terminated signaling technology allows devices to achieve higher data rates with significantly reduced IO power.
The R+ LPDDR3 architecture is built from ground up to be backward compatible with LPDDR3 supporting same protocol, power states and existing package definitions and system environments.
The R+ LPDDR3 memory controller and DRAM interface solutions are currently available.
This allows customers to differentiate their products in a cost-effective manner with improved time-to-market. Further helping improve design and development cycles, the R+ LPDDR3 is also available with Rambus’ collaborative design and integration services.
The R+ LPDDR3 architecture includes both a controller and a DRAM interface and can reduce active memory system power by up to 25% and supports data rates of up to 3200 megabits per second (Mbps), which is double the performance of existing LPDDR3 technologies. These improvements to power efficiency and performance enable longer battery life and enhanced mobile device functionality for streaming HD video, gaming and data-intensive apps.
“Each generation of mobile devices demands even higher performance with lower power. The R+ LPDDR3 technology enables the mobile market to use our controller and DRAM solutions to provide unprecedented levels of performance, with a significant power savings,” said Kevin Donnelly, senior VP and GM of the Memory and Interface Division at Rambus.
“Since this technology is a part of our R+ platform, beyond the improvements in power and performance, we’re also maintaining compatibility with today’s standards to ensure our customers have all the benefits of the Rambus’ superior technology with reduced adoption risk.”
The seed to the improved power and performance offered by the R+ LPDDR3 architecture is a low-swing implementation of the Rambus Near Ground Signaling technology. Essentially, this single-ended, ground-terminated signaling technology allows devices to achieve higher data rates with significantly reduced IO power.
The R+ LPDDR3 architecture is built from ground up to be backward compatible with LPDDR3 supporting same protocol, power states and existing package definitions and system environments.
The R+ LPDDR3 memory controller and DRAM interface solutions are currently available.
Fairchild intros shorted-anode IGBTs
USA: High-power and high-frequency induction heating (IH) appliances require lower conduction losses and superior switching performance in order to achieve higher efficiency and system reliability in applications such as IH rice cookers, table-top induction cookers and inverter-based microwave ovens.
Fairchild Semiconductor’s high-voltage field-stop shorted-anode trench IGBTs provide designers with a highly efficient, cost-effective solution to these design challenges.
Ranging from 1100-1400V, this new product family is optimized with intrinsic anti-parallel diodes for soft switching applications. With advancements over the typical non-punch-through (NPT) IGBT technology, Fairchild’s shorted-anode silicon technology offers a lower saturation voltage of over 12 percent less than the same rating NPT-trench IGBT.
Additionally, when compared to the competitor’s IGBT offerings, this product family offers a lower tail-current rate of over 20 percent. These rich features allow Fairchild’s advanced IGBTs to provide better thermal performance, higher efficiency and reduced power losses.
Features and benefits:
• High-speed switching frequency range: 10 to 50 kHz.
• Lowest tail-current in industry for improved switching loss (FGA20S140P).
• Low saturation voltage drop than existing NPT trench IGBTs.
• Robust pot detection noise immunity for reliability.
• High temperature stable behavior: Tj(max) = 175 degree C.
• RoHS compliant (Pb-free lead plating).
Fairchild Semiconductor’s high-voltage field-stop shorted-anode trench IGBTs provide designers with a highly efficient, cost-effective solution to these design challenges.
Ranging from 1100-1400V, this new product family is optimized with intrinsic anti-parallel diodes for soft switching applications. With advancements over the typical non-punch-through (NPT) IGBT technology, Fairchild’s shorted-anode silicon technology offers a lower saturation voltage of over 12 percent less than the same rating NPT-trench IGBT.
Additionally, when compared to the competitor’s IGBT offerings, this product family offers a lower tail-current rate of over 20 percent. These rich features allow Fairchild’s advanced IGBTs to provide better thermal performance, higher efficiency and reduced power losses.
Features and benefits:
• High-speed switching frequency range: 10 to 50 kHz.
• Lowest tail-current in industry for improved switching loss (FGA20S140P).
• Low saturation voltage drop than existing NPT trench IGBTs.
• Robust pot detection noise immunity for reliability.
• High temperature stable behavior: Tj(max) = 175 degree C.
• RoHS compliant (Pb-free lead plating).
Synopsys' LightTools 8.0 increases designer productivity with faster performance and enhanced 3D design
USA: Synopsys Inc. announced the availability of version 8.0 of its LightTools illumination design software, which delivers multi-CPU support that dramatically improves the speed of lighting system simulations. With the addition of several new 3D objects, application-specific utilities and enhancements to parametric controls, this version also provides features that simplify the design of state-of-the-art lighting components.
"We've made LightTools even better with significantly faster performance as well as new and improved tools for building and visualizing illumination designs," said George Bayz, vice president and general manager of the Optical Solutions Group at Synopsys. "These updates help pave the way for lighting engineers to design, manufacture and deploy their products faster and more cost effectively."
Multi-CPU support
LightTools has been enhanced with a multi-threading capability that enables illumination simulation processes to take advantage of all CPUs or cores on a computer. The multi-CPU feature can dramatically improve the speed of simulations, analyses and design optimizations.
"The multi-thread capabilities of LightTools 8.0 efficiently leverage my computer resources," said Dr. Juan Manuel Teijido, chief scientist at Haag-Streit AG. "The fast ray tracing allows me to perform rapid iterations and stay focused on my optical design. My productivity has been greatly improved with this release."
"The LightTools multi-CPU feature has yielded great results. On my latest project, simulation times with 1.5 million rays were reduced from 177 seconds to 41 seconds," said Kris Young, opto-mechanical engineer at Konstant Products. "This is more than a 4X speed improvement that enables me to run hundreds of simulations at the beginning of a project and also allows for much more complex optimizations at the end of the project."
New 3D objects
To facilitate the creation of complex lighting components, LightTools introduces new types of 3D objects, including revolved sheets and solids, extruded sheets and solids and freeform sheets. These objects expand the range of shapes available for creating state-of-the-art illumination optics such as compact, freeform surfaces used in automotive headlights.
Source array utility
The LightTools Source Array Utility simplifies the construction of source arrays used for applications such as edge-lit displays and luminaires. It enables users to quickly and easily convert a given surface of a solid to an array of identical sources while requiring only a single source in the model.
Street lighting utility
The LightTools Street Lighting Utility provides a specialized set of tools that guides users through the process of evaluating, designing and optimizing luminance and illuminance patterns on roadways to meet industry-standard specifications. The utility has been enhanced to broaden capabilities for street lighting design.
For example, users can now define a light distribution that is either Gaussian or uniform across a roadway in order to determine the type of distribution that is needed to meet roadway lighting specifications.
Improvements to parametric controls
Improvements to LightTools' parametric controls include convenient new ways to move and group them. These enhancements help users more easily organize and manage elements that control the geometry, position and function of each component in a LightTools model.
Enhanced illuminance display in 3D model
Additional tools are now available for visualizing the shape and orientation of a light source's illuminance distribution with respect to model geometry. This includes the ability to display true color output in the LightTools 3D Design view, as well as the ability to concurrently display illuminance results for all surface receivers in a model, making it easier to compare results.
LightTools version 8.0 is available now. Customers with a current maintenance agreement can download this version from the Synopsys website using their SolvNet account.
"We've made LightTools even better with significantly faster performance as well as new and improved tools for building and visualizing illumination designs," said George Bayz, vice president and general manager of the Optical Solutions Group at Synopsys. "These updates help pave the way for lighting engineers to design, manufacture and deploy their products faster and more cost effectively."
Multi-CPU support
LightTools has been enhanced with a multi-threading capability that enables illumination simulation processes to take advantage of all CPUs or cores on a computer. The multi-CPU feature can dramatically improve the speed of simulations, analyses and design optimizations.
"The multi-thread capabilities of LightTools 8.0 efficiently leverage my computer resources," said Dr. Juan Manuel Teijido, chief scientist at Haag-Streit AG. "The fast ray tracing allows me to perform rapid iterations and stay focused on my optical design. My productivity has been greatly improved with this release."
"The LightTools multi-CPU feature has yielded great results. On my latest project, simulation times with 1.5 million rays were reduced from 177 seconds to 41 seconds," said Kris Young, opto-mechanical engineer at Konstant Products. "This is more than a 4X speed improvement that enables me to run hundreds of simulations at the beginning of a project and also allows for much more complex optimizations at the end of the project."
New 3D objects
To facilitate the creation of complex lighting components, LightTools introduces new types of 3D objects, including revolved sheets and solids, extruded sheets and solids and freeform sheets. These objects expand the range of shapes available for creating state-of-the-art illumination optics such as compact, freeform surfaces used in automotive headlights.
Source array utility
The LightTools Source Array Utility simplifies the construction of source arrays used for applications such as edge-lit displays and luminaires. It enables users to quickly and easily convert a given surface of a solid to an array of identical sources while requiring only a single source in the model.
Street lighting utility
The LightTools Street Lighting Utility provides a specialized set of tools that guides users through the process of evaluating, designing and optimizing luminance and illuminance patterns on roadways to meet industry-standard specifications. The utility has been enhanced to broaden capabilities for street lighting design.
For example, users can now define a light distribution that is either Gaussian or uniform across a roadway in order to determine the type of distribution that is needed to meet roadway lighting specifications.
Improvements to parametric controls
Improvements to LightTools' parametric controls include convenient new ways to move and group them. These enhancements help users more easily organize and manage elements that control the geometry, position and function of each component in a LightTools model.
Enhanced illuminance display in 3D model
Additional tools are now available for visualizing the shape and orientation of a light source's illuminance distribution with respect to model geometry. This includes the ability to display true color output in the LightTools 3D Design view, as well as the ability to concurrently display illuminance results for all surface receivers in a model, making it easier to compare results.
LightTools version 8.0 is available now. Customers with a current maintenance agreement can download this version from the Synopsys website using their SolvNet account.
Chip inventory at semiconductor suppliers reaches worrisome high
USA: Chip inventory held by semiconductor suppliers reached alarmingly high levels in the third quarter of 2012 amid weak market conditions, according to an IHS iSuppli Semiconductor Inventory Insider market brief.
Overall semiconductor revenue declined by 0.7 percent sequentially during the fourth quarter last year. The poor results came after inventory reached exceedingly high levels by the end of the third quarter in 2012, amounting to 49.3 percent of total semiconductor revenue—more elevated than at any point since the first quarter of 2006.
Chip stockpiles among semiconductor suppliers had actually gone down during the final two quarters of 2011, showing a promising drawdown. But then, inventories steadily ticked up again after that, reaching 47.5 percent of total revenue in the second quarter before hitting the current peak in the third—the latest time for which full figures are available.
Sizing the stockpiles
The inventory level being measured refers to chip stockpiles specifically in the hands of semiconductor suppliers, not to inventory throughout the electronics supply chain. Chip level at the supplier level is then compared against combined revenue from a sample of 75 semiconductor supplier companies excluding memory, which is tracked separately because of that market’s typical late results.
A low inventory-to-revenue ratio is preferable, given that higher levels indicate not only unsold stockpiles but also unrealized revenue tied up with the stagnant inventory.
Demand debacle
“The uncomfortably high level of inventory among semiconductor manufacturers of nearly all stripes is a result of key demand drivers failing to materialize,” said Sharon Stiefel, analyst for semiconductor market intelligence at IHS.
“Demand for semiconductor devices has typically come from new products that consumers feel compelled to purchase. But going into the holiday season last year, no such new products marshaled enough impetus to overcome consumer fears about lingering economic woes. Two months prior to Christmas, consumer purchases of electronics had grown by only 0.7 percent, the worst performance since 2008.”
Also contributing to depressed conditions was the poor performance of the industry’s data processing segment, traditionally the largest user of semiconductors. In fact, mobile PCs were projected to decline in 2012 when final figures are tallied, toppled from dominance by media tablets. Ultrabooks and other ultrathin PCs, meanwhile, did not produce the demand for semiconductors originally expected as the year progressed.
Semiconductor sectors
Despite the collective rise in inventory stockpiles, some semiconductor segments performed better than others. For instance, with feature-rich smartphones and tablets taking the place of traditional PCs among consumers and eroding PC market share, the devices were anticipated to provide the strongest demand in the final quarter of 2012.
As a result, semiconductor revenue for the wireless segment was expected to climb almost 4 percent. Semiconductor sectors benefiting from the tremendous growth of handsets and tablets included logic, analog and NAND flash memory, with those semiconductor channels refilling following strong shipments even into the beginning of this year.
The first quarter of 2013 likely will see growth in the industrial and automotive electronics segments. Other semiconductor markets, for their part, will overcome the seasonal decline normally expected at this time of year and then start to rebound around the second and third quarters. Such assumptions, however, rest on the even larger factor of the global economy, currently a volatile variable itself with no set outcome.
If the global economic forecasts perform according to positive expectations, semiconductor revenue could grow by 4 percent in the second quarter and by a very solid 9 percent in the third. However, if demand evaporates, semiconductor suppliers will find themselves in a deplorable oversupply situation, which would then lead to inventory write-downs throughout the year.
Overall semiconductor revenue declined by 0.7 percent sequentially during the fourth quarter last year. The poor results came after inventory reached exceedingly high levels by the end of the third quarter in 2012, amounting to 49.3 percent of total semiconductor revenue—more elevated than at any point since the first quarter of 2006.
Chip stockpiles among semiconductor suppliers had actually gone down during the final two quarters of 2011, showing a promising drawdown. But then, inventories steadily ticked up again after that, reaching 47.5 percent of total revenue in the second quarter before hitting the current peak in the third—the latest time for which full figures are available.
Sizing the stockpiles
The inventory level being measured refers to chip stockpiles specifically in the hands of semiconductor suppliers, not to inventory throughout the electronics supply chain. Chip level at the supplier level is then compared against combined revenue from a sample of 75 semiconductor supplier companies excluding memory, which is tracked separately because of that market’s typical late results.
A low inventory-to-revenue ratio is preferable, given that higher levels indicate not only unsold stockpiles but also unrealized revenue tied up with the stagnant inventory.
Demand debacle
“The uncomfortably high level of inventory among semiconductor manufacturers of nearly all stripes is a result of key demand drivers failing to materialize,” said Sharon Stiefel, analyst for semiconductor market intelligence at IHS.
“Demand for semiconductor devices has typically come from new products that consumers feel compelled to purchase. But going into the holiday season last year, no such new products marshaled enough impetus to overcome consumer fears about lingering economic woes. Two months prior to Christmas, consumer purchases of electronics had grown by only 0.7 percent, the worst performance since 2008.”
Also contributing to depressed conditions was the poor performance of the industry’s data processing segment, traditionally the largest user of semiconductors. In fact, mobile PCs were projected to decline in 2012 when final figures are tallied, toppled from dominance by media tablets. Ultrabooks and other ultrathin PCs, meanwhile, did not produce the demand for semiconductors originally expected as the year progressed.
Semiconductor sectors
Despite the collective rise in inventory stockpiles, some semiconductor segments performed better than others. For instance, with feature-rich smartphones and tablets taking the place of traditional PCs among consumers and eroding PC market share, the devices were anticipated to provide the strongest demand in the final quarter of 2012.
As a result, semiconductor revenue for the wireless segment was expected to climb almost 4 percent. Semiconductor sectors benefiting from the tremendous growth of handsets and tablets included logic, analog and NAND flash memory, with those semiconductor channels refilling following strong shipments even into the beginning of this year.
The first quarter of 2013 likely will see growth in the industrial and automotive electronics segments. Other semiconductor markets, for their part, will overcome the seasonal decline normally expected at this time of year and then start to rebound around the second and third quarters. Such assumptions, however, rest on the even larger factor of the global economy, currently a volatile variable itself with no set outcome.
If the global economic forecasts perform according to positive expectations, semiconductor revenue could grow by 4 percent in the second quarter and by a very solid 9 percent in the third. However, if demand evaporates, semiconductor suppliers will find themselves in a deplorable oversupply situation, which would then lead to inventory write-downs throughout the year.
DSP Group intros DECT ultra low energy DHX91 chipset
USA: DSP Group Inc. has released its cutting-edge DHX91 DECT ultra low energy (ULE) chipset, addressing the demanding requirements of smart home and smart energy devices.
The new DHX91 chipset is a flexible, high-performance and highly-integrated system on a chip (SoC), enabling ultra low energy (ULE) DECT wireless communication for smart home and smart energy applications such as home automation, security, monitoring, metering, healthcare and others. Combining unique DECT ULE features with a high level of integration and optimized connectivity to various types of sensors, the DHX91 is the most cost-optimized solution for home area network (HAN) devices.
The DHX91 chipset includes rich set of technologies, such as a cutting-edge ULE block, a digital baseband controller based on advanced ARM9(TM) core, a state-of-the-art RF transceiver, power amplifiers, various peripherals, and enhanced hardware accelerators for voice and video applications. The DHX91 is offered in various cost/performance optimized configurations.
The DHX91's small footprint and high integration allows for highly compact designs. The DSP Group's DECT ULE module, demonstrated at CES 2013 in Las Vegas, meets the demands of HAN devices such as door magnets, healthcare pendants, smoke and motion detectors, AC outlets, and more. DSP Group provides full hardware and software reference designs for the DHX91 in order to minimize time to market and reduce cost and risk for home automation device manufacturers.
The new DHX91 chipset is a flexible, high-performance and highly-integrated system on a chip (SoC), enabling ultra low energy (ULE) DECT wireless communication for smart home and smart energy applications such as home automation, security, monitoring, metering, healthcare and others. Combining unique DECT ULE features with a high level of integration and optimized connectivity to various types of sensors, the DHX91 is the most cost-optimized solution for home area network (HAN) devices.
The DHX91 chipset includes rich set of technologies, such as a cutting-edge ULE block, a digital baseband controller based on advanced ARM9(TM) core, a state-of-the-art RF transceiver, power amplifiers, various peripherals, and enhanced hardware accelerators for voice and video applications. The DHX91 is offered in various cost/performance optimized configurations.
The DHX91's small footprint and high integration allows for highly compact designs. The DSP Group's DECT ULE module, demonstrated at CES 2013 in Las Vegas, meets the demands of HAN devices such as door magnets, healthcare pendants, smoke and motion detectors, AC outlets, and more. DSP Group provides full hardware and software reference designs for the DHX91 in order to minimize time to market and reduce cost and risk for home automation device manufacturers.
DSP chipset powers Huawei home gateway and Swissvoice handset for Turkcell SuperOnLine
USA: DSP Group Inc. announced that its cordless chipset solutions are powering a CAT-iq 2.0 ready global solution offered by Turkcell SuperOnLine in Turkey.
The Huawei HG253 Fiber home gateway combined with Swissvoice IH250 handsets are enabling Turkcell SuperOnLine subscribers to enjoy HD-voice quality and value-added multi-line, multi-handset services.
Already in use by Turkcell SuperOnLine Fiber subscribers, the voice over IP service is powered by DSP Group's XceedR family of market-leading chipset solutions. The Huawei HG253 home fiber gateway leverages DSP Group's digital cordless chipset reference design, which enables development of a low-cost, small form-factor module.
This module can be seamlessly integrated into various broadband residential gateways, including integrated access devices (IADs), cable embedded multimedia terminal adapters (EMTAs), and IP office PBXs. Based on a single-chip architecture, DSP Group's reference design reduces development risk, minimizes R&D costs, and lowers time to market, while guaranteeing the latest DECT CAT-iq technology support.
The Huawei HG253 Fiber home gateway combined with Swissvoice IH250 handsets are enabling Turkcell SuperOnLine subscribers to enjoy HD-voice quality and value-added multi-line, multi-handset services.
Already in use by Turkcell SuperOnLine Fiber subscribers, the voice over IP service is powered by DSP Group's XceedR family of market-leading chipset solutions. The Huawei HG253 home fiber gateway leverages DSP Group's digital cordless chipset reference design, which enables development of a low-cost, small form-factor module.
This module can be seamlessly integrated into various broadband residential gateways, including integrated access devices (IADs), cable embedded multimedia terminal adapters (EMTAs), and IP office PBXs. Based on a single-chip architecture, DSP Group's reference design reduces development risk, minimizes R&D costs, and lowers time to market, while guaranteeing the latest DECT CAT-iq technology support.
Renesas Electronics America intros RX-based solutions kit for graphic/touch panel solutions
USA: Renesas Electronics America Inc. announced the development of a new, cost-effective Solutions Kit for the RX family of MCUs, enabling engineers working in a broad mix of application segments to take advantage of Renesas’ low-power and high-performance RX family.
The Embedded GUI Solution Kit will continue to drive innovation for the next generation of connected “smart society” applications, helping designers simplify and speed the development cycle to add a touchscreen LCD for medical, instrumentation, home automation, energy management, fitness and transportation products.
Featuring Renesas’ RX63N MCU, graphical software from Micrium and a Serious Integrated graphic/touch module, the new solution kit offers enhanced development tools in a convenient package, accelerating design time-to-GUI. The low price point makes it easier to put a kit on every engineer’s desktop or lab bench.
The new solution kit includes support for Micrium’s µC/GUI graphic library, a powerful graphic package that allows developers to add a state-of-the-art GUI with touchscreen to any embedded solution. In September 2012, Renesas and Micrium introduced the “The Power of Two” program, where Renesas customers designing products with RX and RL78 MCUs can receive a single, complementary production RTOS/Middleware license and source code from Micrium.
With this Embedded GUI Solution Kit, Renesas and Micrium extend “The Power of Two” program, adding the µC/GUI development software package to the offering. The “Power of Two” Program runs until March 31, 2013.
“The Embedded GUI solution kit marks the next stage in our ongoing partnership with Serious Integrated and Micrium,” said Peter Carbone, VP of Marketing at Renesas Electronics America. “Leveraging comprehensive knowledge of our touchscreen LCD solution, we’ve built a solution kit with an integrated development environment that can dramatically reduce development time from months to days for quick prototype solutions to support new and emerging market opportunities.”
The Embedded GUI Solution Kit will continue to drive innovation for the next generation of connected “smart society” applications, helping designers simplify and speed the development cycle to add a touchscreen LCD for medical, instrumentation, home automation, energy management, fitness and transportation products.
Featuring Renesas’ RX63N MCU, graphical software from Micrium and a Serious Integrated graphic/touch module, the new solution kit offers enhanced development tools in a convenient package, accelerating design time-to-GUI. The low price point makes it easier to put a kit on every engineer’s desktop or lab bench.
The new solution kit includes support for Micrium’s µC/GUI graphic library, a powerful graphic package that allows developers to add a state-of-the-art GUI with touchscreen to any embedded solution. In September 2012, Renesas and Micrium introduced the “The Power of Two” program, where Renesas customers designing products with RX and RL78 MCUs can receive a single, complementary production RTOS/Middleware license and source code from Micrium.
With this Embedded GUI Solution Kit, Renesas and Micrium extend “The Power of Two” program, adding the µC/GUI development software package to the offering. The “Power of Two” Program runs until March 31, 2013.
“The Embedded GUI solution kit marks the next stage in our ongoing partnership with Serious Integrated and Micrium,” said Peter Carbone, VP of Marketing at Renesas Electronics America. “Leveraging comprehensive knowledge of our touchscreen LCD solution, we’ve built a solution kit with an integrated development environment that can dramatically reduce development time from months to days for quick prototype solutions to support new and emerging market opportunities.”
MediaTek announces world's first 5-in-1 multi-GNSS receiver SoC solutions
TAIWAN: MediaTek Inc. has announced the availability of its MT3332/MT3333, the world's first 5-in-1 multi-GNSS (Global Navigation Satellite System) receiver SoC solutions that support the Beidou Satellite Navigation System.
The Beidou system has been commercially operational since the end of 2012, and is currently a constellation of 16 satellites providing positioning, navigation and timing services to the Asia-Pacific region. It can identify a user's location to 10m (33ft), their velocity to within 0.2 meters per second, and clock synchronization signals (one-way) to within 10 nanoseconds. Beidou will be one of the most important satellite navigation systems to eventually cover the entire globe by 2020.
The MediaTek MT3332/MT3333 can discover GPS, Beidou, GLONASS, Galileo and QZSS constellations. Featuring a multi-GNSS receiver design, the MT3332/MT3333 can reduce the cumulative distance and positioning error accumulated over time/multiple hops, and significantly improve navigation/positioning accuracy.
The MT3332/MT3333 also come with excellent signal acquisition and tracking sensitivity, which efficiently enhances signal quality within dense cities, tunnels and/or multi-storey car-parks, while delivering a better user experience. Moreover, thanks to its highly integrated, low-cost and ultra-compact system architecture, the MT3332/MT3333 enable multi-GNSS receivers with the same reference board for mobile, industrial and automotive navigation applications.
"The proliferation of LBS (location-based services) using mobile applications over wireless networks such as 'social check-in' or 'nearby service recommending' is driving demand for greater satellite navigation performance and coverage beyond existing technologies. This will also lead to the rapid adoption of multi-GNSS receiver solutions in smartphones, tablets and automotive vehicles because LBS is now an indispensable way for people to interact/communicate with each other on a daily basis," said SR Tsai, GM of the Wireless Connectivity and Networking Business Unit at MediaTek.
"We believe the market for Beidou-compatible multi-GNSS receivers in China will accelerate in the coming years. MediaTek will deliver new products that offer high value and are capable of meeting the evolving needs of our customers in the Beidou navigation system market through continuous product innovation. The MT3332/MT3333 are designed to accelerate the realization of satellite navigation services anytime, anywhere, in a seamless fashion."
The MT3332/MT3333 incorporates MediaTek's unique "AlwaysLocate" technology that can identify the state in which the user is (regardless of on-the-go or sleeping) and automatically adjust the satellite signal receiving modes for more accurate and reliable navigation services, and to save the battery power of the navigation system.
The MediaTek MT3332/MT3333 are currently in mass production stage and already being designed into major satellite navigation systems and mobile communication platforms worldwide.
The Beidou system has been commercially operational since the end of 2012, and is currently a constellation of 16 satellites providing positioning, navigation and timing services to the Asia-Pacific region. It can identify a user's location to 10m (33ft), their velocity to within 0.2 meters per second, and clock synchronization signals (one-way) to within 10 nanoseconds. Beidou will be one of the most important satellite navigation systems to eventually cover the entire globe by 2020.
The MediaTek MT3332/MT3333 can discover GPS, Beidou, GLONASS, Galileo and QZSS constellations. Featuring a multi-GNSS receiver design, the MT3332/MT3333 can reduce the cumulative distance and positioning error accumulated over time/multiple hops, and significantly improve navigation/positioning accuracy.
The MT3332/MT3333 also come with excellent signal acquisition and tracking sensitivity, which efficiently enhances signal quality within dense cities, tunnels and/or multi-storey car-parks, while delivering a better user experience. Moreover, thanks to its highly integrated, low-cost and ultra-compact system architecture, the MT3332/MT3333 enable multi-GNSS receivers with the same reference board for mobile, industrial and automotive navigation applications.
"The proliferation of LBS (location-based services) using mobile applications over wireless networks such as 'social check-in' or 'nearby service recommending' is driving demand for greater satellite navigation performance and coverage beyond existing technologies. This will also lead to the rapid adoption of multi-GNSS receiver solutions in smartphones, tablets and automotive vehicles because LBS is now an indispensable way for people to interact/communicate with each other on a daily basis," said SR Tsai, GM of the Wireless Connectivity and Networking Business Unit at MediaTek.
"We believe the market for Beidou-compatible multi-GNSS receivers in China will accelerate in the coming years. MediaTek will deliver new products that offer high value and are capable of meeting the evolving needs of our customers in the Beidou navigation system market through continuous product innovation. The MT3332/MT3333 are designed to accelerate the realization of satellite navigation services anytime, anywhere, in a seamless fashion."
The MT3332/MT3333 incorporates MediaTek's unique "AlwaysLocate" technology that can identify the state in which the user is (regardless of on-the-go or sleeping) and automatically adjust the satellite signal receiving modes for more accurate and reliable navigation services, and to save the battery power of the navigation system.
The MediaTek MT3332/MT3333 are currently in mass production stage and already being designed into major satellite navigation systems and mobile communication platforms worldwide.
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