MoSys demos bandwidth engine IC interoperability with Avago SerDes

SANTA CLARA, USA: MoSys, a leading provider of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, has successfully demonstrated interoperability of its Bandwidth Engine IC with the SerDes characterization and evaluation board from Avago Technologies.

MoSys’ Bandwidth Engine SerDes is compatible with the OIF CEI-11 specification allowing it to interface with high-performance network processing ASICs such as those available from Avago Technologies. The GigaChip Interface used by the Bandwidth Engine IC is a 90 percent efficient, no-cost, open transport protocol optimized for chip to chip communications. This demonstration shows the Bandwidth Engine IC communicating with the Avago SerDes at a full 10.3125 Gbps.

“Avago Technologies is well-known as one of the world’s leading providers of high-performance ASICs to networking customers and they are renowned for having one of the industry’s best SerDes technologies. Having interoperability between our Bandwidth Engine and network processing ASICs designed by Avago is important for our mutual customers,” stated David DeMaria, VP of Business Operations. “Our demonstration of interoperability with Avago is an important milestone.”

“As a leading provider to tier one networking companies, Avago Technologies is always looking for innovative solutions that complement our products,” stated Todd Metcalf, senior director of Marketing for Avago Technologies. “We view MoSys Bandwidth Engine as a powerful new technology and are pleased to be the first ASIC company proving interoperability.”