Duolog to present IP-XACT solution to increase IP quality through register management

DUBLIN, IRELAND: Duolog Technologies, the award-winning developer of IP and SoC integration products, has been selected to present a technical paper at ARM TechCon. The presentation highlights how Duolog’s Socrates integration applications interoperate with Cadence Incisive Enterprise Simulator products to demonstrate register management as a fully mature IP methodology. Duolog will present this solution during ARM TechCon in Santa Clara on Tuesday, 25th October at 11:00 a.m. PDT.

“Improving IP quality is essential, especially for streamlining hardware/software integration,” said David Murray, Duolog’s CTO and featured ARM TechCon speaker. “The presentation illustrates a sample flow that shows how IP-XACT can be used as an interoperable register specification to save development time and effort and increase design quality.”

The technical paper, titled “Increasing IP Quality through Register Management using Cadence Incisive” explores the types of quality issues that are typical on the HW/SW interface of an IP. A complete register management solution is presented with auto-generated outputs including VHDL, Verilog, SystemC and SystemVerilog, and supporting methodologies such as TLM2.0, UVM and CMSIS. The solution features Duolog’s industry-leading register and memory-map management tool, Socrates Bitwise.

Duolog will also be exhibiting at ARM TechCon on Tuesday, 25th October in Booth #25. The Duolog team will be demonstrating their industry-leading Socrates tool suite. In addition, Duolog have successfully collaborated with ARM to present, “Faster Fabric Integration using ARM CoreLink AMBA Designer & Duolog Socrates” at the Duolog booth. The presentation focuses on the complementary benefits of combining Socrates with ARM’s system IP and CoreLink AMBA Designer. This results in faster and more consistent IP integration and system assembly with fewer bugs and reduced verification times.