ARM and Mentor Graphics define comprehensive test methodology for ARM-based designs

International Test Conference 2011, ANAHEIM, USA: Mentor Graphics Corp. announced a comprehensive solution, jointly developed by Mentor and ARM, for manufacturing test of ARM processor-based designs.

The reference flow provides documentation, seamless interfaces, and scripts that accelerate the development of a complete test solution for ARM IP based on the Tessent test tools from the Mentor Graphics Corporation. The flow is optimized for high test quality, lower test cost and shortened design-for-test development schedules.

Today’s SoCs typically contain hundreds of memory subsystems consisting of several types of individual SRAMs, including single- and dual-port SRAM, register files and ROMs. Within each subsystem, the memories may range from high-speed SRAMs operating at higher voltages to power-optimized SRAMs operating at reduced voltage.

All such memories have different test and/or repair requirements, depending on the size of the individual memory instances, total SoC memory size, process defect level and maturity. The Tessent solution provides a completely automated memory test and repair solution including at speed testing with 100 percent accurate logical-to-physical mapping of ARM Artisan memories.

In addition to the many memory SoC subsystems, some of the memories are further embedded within processor cores which have been custom tailored to achieve the highest performance and lowest power in the smallest footprint. The additional complexity added by the need for proper test—and in some cases, repair of the memories contained in these optimized cores—mandates a test and repair solution that achieves the highest yield with minimal impact on SoC performance, power, footprint or cost.

ARM and Mentor have collaborated to enable Tessent support for the ARM MBIST core interface, which provides one or more interfaces for each embedded core, enabling full testing of every memory within each core with minimum impact on core power, performance or area.

“The new Tessent TestKompress reference flow provides our customers with a simple and verified test methodology for cost-effective, high quality test of processor cores and associated logic,” said Teresa McLaurin, DFT manager at ARM. “This builds on our previous collaboration on comprehensive, automated built-in self test (BIST) solutions for ARM physical memory IP using the Tessent MemoryBIST product.”

The ARM-Mentor test flow supports comprehensive testing of ARM cores and logic, and embedded memories used in customer SoCs. The solution employs the Mentor scan-based design-for-test and automatic test pattern generation (ATPG) tools with embedded compression, as well as memory BIST with self-repair technologies. The test flow defines all steps necessary for incorporating and verifying all test compression and memory BIST IP, as well as generating all necessary test patterns. The automation flow is further simplified through default scripting and configuration files.

“Our joint effort with ARM is extremely beneficial for our mutual customers because it enhances the time-to-market advantages of using ARM IP by helping them achieve their testing objectives in the least amount of time,” said Steve Pateras, product marketing director, Silicon Test Products, Mentor Graphics. “The Tessent solution also helps the bottom line with the most efficient testing available to reduce test time and overall manufacturing cost.”