Friday, August 12, 2011

Intel and Micron receive Most Innovative Flash Memory Technology award

2011 Flash Memory Summit, SANTA CLARA & BOISE, USA: Intel Corp. and Micron Technology Inc. received the Most Innovative Flash Memory Technology award Aug. 10 at the 2011 Flash Memory Summit for the companies' industry-leading 20 nanometer (nm) NAND Flash memory process technology.

The 20nm 8 gigabyte (GB) NAND device from Intel and Micron delivers the highest capacity in the smallest form factor. Manufactured by IM Flash Technologies, the NAND flash joint venture from Intel and Micron, the new device is a breakthrough in NAND process and technology design, further extending the companies' lithography leadership.

Shrinking NAND lithography to this technology node is the most cost-effective method for increasing NAND output to date, providing approximately 50 percent more gigabyte capacity than current technology. The new 20nm process technology also helps further the companies' dual goal to enable instant, affordable access to the world's information.

"The growth in storage all the way from the data center to full-featured smartphones and tablets is creating new demands for NAND flash technology, especially greater capacity in smaller designs," said Glen Hawk, VP of Micron's NAND Solutions Group. "Micron is proud of the industry-leading technology we have developed with Intel, and we're pleased to have this technology honored by the Flash Memory Summit."

"NAND silicon process and die level innovation is foundational for the flash memory industry to provide compelling end solutions like solid-state drives," said Tom Rampone, Intel VP and GM of the Intel Non-Volatile Memory Solutions Group. "We are pleased that the Flash Memory Summit continues to recognize the innovation and success that Intel and Micron are achieving together."

Additionally, the new 20nm 8GB device measures just 118mm2 and enables a 30 to 40 percent reduction in board space (depending on package type) compared to existing 25nm 8GB NAND devices. A reduction in the flash storage layout provides greater system level efficiency as it enables tablet and smartphone manufacturers to use the extra space for end-product improvements such as a bigger battery, larger screen or adding another chip to handle new features.

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