3D-IC opens new era of packaging and testing

TAIPEI, TAIWAN: Given the growing importance of packaging and testing in the global semiconductor supply chain, SEMI will hold the first-ever SiP Global Summit from September 7-9 with support from major international companies and research organizations.

Participants in the System in Package (SiP) summit will include ASE, Qualcomm, Sony, TSMC, Verigy; and R&D and market research organizations including Gartner, Fraunhofer IZM, IMEC, Yole Development and ITRI.

An ITRI recent forecast indicates that production value of 3D-ICs for mobile phone applications will hit US$ 3.65 billion by 2015. With the growing popularity of smart phones, e-book readers and other mobile devices, manufacturers have placed a stronger focus on heterogeneous integration through SiP to enhance user experience.

Topology Research Institute has pointed out 3D-ICs will be the mainstream in the post-PC era, a point validated by Powertech, Elpida and United Microelectronics, which recently joined forces to develop 3D-ICs targeting below 28-nm process nodes. Other packaging and testing houses such as ASE and SPIL are also focusing on 3D-stacked packaging. IC firms are bracing themselves for the “Era of 3D-ICs.”

Terry Tsao, president of SEMI Southeast Asia, said: “3D-IC production is a positive but challenging development for semiconductor testing and packaging operators, who are striving for mass production and looking for more cost-effective solutions to overcome current technology bottlenecks. SEMI’s SiP Global Summit helps move Taiwan manufacturers achieve further successes in this arena.”

Dr. Ho-Ming Tong, general manager and chief R&D officer of ASE, noted, “Despite progress in 3D-IC development over the past years, challenges remain in areas of cost control, design, mass production and testing in the lead-up to commercialization. Given that silicon interposer-based 2.5D-IC technology has become mature, its deployment will expedite migration from the 40-nm node to 28-nm. With computing and smart devices fueling growth of the market, commercialization of 2.5D- and 3D-ICs may take place in 2013.”

The three-day SiP Global Summit will consist of three major forums— 3D-IC Test Forum, 3D-IC Technology Forum and Embedded Substrate Forum— with representatives from 25 of the world’s best IT firms slated to share insights into the 3D-IC, TSV, silicon interposer and embedded substrate technologies.

3D-IC Test Forum: Finding Heterogeneous Integration Solutions: In the process of 3D-IC commercialization, many packaging and testing challenges must be overcome to help manufacturers achieve the anticipated yield rates. In this forum, executives from ASE, KYEC, and Qualcomm will discuss 3D TSV challenges and cost strategy from the operators’ perspective. In addition, FormFactor and Teradyne executives will discuss challenges facing testing operators from the equipment makers’ perspective and address cost control and technology development issues.

3D-IC Technology Forum: Ringing in the 2.5D- and 3D-IC Era: Just as PlayStation 3 is taking game consoles into the world of 3D, so will the packaging technology transition from 2D to 3D. Operators are looking to strike a balance between performance optimization, time-to-market expedition and cost reduction through the use of different materials, equipment, process nodes, and product standardization and commercialization methods. Organized by IMEC and SEMI, this forum is a comprehensive forum for IC testing and packaging operators, with presentations by ASE, IEEE-CPMT, IMEC and Xilinx, Inc.

Embedded Substrate Forum: Last Mile to a Heterogeneous Integration: Given 3D-ICs will have wide applications in mobile phones, the forum will feature R&D officials from Nokia, who will discuss the differences between packaging substrates, module substrates and motherboards. Also, the session features TechSearch International presenting on the embedded substrate developmental trend.