“Throughout this report, you will find everything you should know about flip-chip”, explains Jean-Marc Yannou, Project Manager, Yole Développement.
Source: Yole Développement, France.Yole Développement’s report provides an exhaustive presentation of the flip-chip markets, the applications served and their key drivers, the technologies used from substrates to underfilled materials to wafer bumping to assembly. Yole Développement’s team also describes the supply chain, a cost analysis section, the market and its value chain.
The Flip Chip report gives the complete set of market forecasts from 2010 to 2016 in billion units and in million wafers by application, by player type, by technology, by wafer size,… The list and ranking of the main substrate, underfilled materials and wafer bumping players is also detailed as of the end of 2010, including the detailed respective production capacities for wafer bumping.
Market and technology trends
Flip-Chip Packages accounted for 13 percent of all integrated circuit (IC) packages by the end of 2010, but this was worth over 29 percent of the global IC assembly, packaging and test market!
This first ever Yole Développement report on flip-chip technologies and markets sheds a new light on this complex and moving market, and makes it clear how it emerged almost from scratch 15 years ago and turned into a $16 billion market as of 2010.
Though it is a large market by the figures and looks mature at first sight, the analysts at Yole Développement think that it is still in its growth phase, with major technology and application and supply chain transformations looming ahead.
“Renewed interest in flip-chip technologies is motivated in many application areas concurrently by such factors as the rising cost of gold used for wire bonding, the need for low thickness devices, continued CMOS downscaling, higher currents and temperatures, and lower voltages”, says Christophe Zinck, Project Manager at Yole Développement.
Today, many sophisticated devices can no longer be packaged with wire bonding technology and the mobile applications are increasingly requiring footprint and weight reduction coupled with higher electrical performance (signal propagation and power distribution).
The emergence of the 28nm CMOS technology node in particular, poses new quality and reliability constraints on interconnect technologies so as to cope with the increasing fragility of the back end of line, which may disqualify wire bonding. Not to mention the ever increasing IO density, making it necessary to develop new bumping and substrate technologies.
It is not any longer only about higher performance and lower cost reliable interconnects or assembly and packaging technologies. If remained unresolved, the above constraints will prove to be bottlenecks if not obstacles to the continuation of Moore’s law.
Segmented market with diverse “realities”
Summarizing the flip-chip market and its dynamics with just a few words and figures can be misleading, as there is a wide diversity of flip-chip technologies and applications, with different drivers, levels of maturity and sometimes alternative technologies.
To some, flip-chip applies to large digital system-on-chip devices like microprocessors, graphical processor units or chipsets for personal computers and gaming stations. Yet, flip-chip applies to a number of different applications addressing different packaging forms. Flip-chip applies not only to packages but also to interconnection of bare integrated circuits, like the display drivers found around all LCD screens worldwide; and flip-chip packages can address devices with die sizes ranging from less than 1mm² up to the maximum die sizes (around 650mm²).
The flip-chip market is undergoing major technology and supply chain transformations which this report describes along with their impacts on the semiconductor industry for the coming five years.
Why are copper pillars becoming so popular? How will this affect the business? Who is investing in these technologies? How is the supply chain changing and how are new technologies reshaping the value chain?
Will CMOS foundries seize a significant stake in this business at the expense of assembly dedicated companies in the years to come? How will the high value of substrates in the overall flip-chip cost of ownership be challenged? And what will substrate manufacturers propose to maintain it?
These are some of the questions we addressed through our 360-degree analysis of the world’s highest value semiconductor packaging technology.
No comments:
Post a Comment
Note: Only a member of this blog may post a comment.