Synopsys, GLOBALFOUNDRIES to develop DesignWare interface PHY IP for 28nm technologies

MOUNTAIN VIEW, USA: Synopsys Inc. and GLOBALFOUNDRIES have announced an agreement to develop the Synopsys DesignWare SuperSpeed USB (3.0), USB 2.0, HDMI 1.4 Tx and Rx, DDR3/2, PCI Express 2.0 and 1.1, SATA 1.5/3 Gbps and 6 Gbps, and XAUI PHY IP for GLOBALFOUNDRIES' 28-nanometer (nm) "Gate First" High-k Metal Gate (HKMG) process technologies.

The collaboration will enable mutual customers to differentiate their 28-nm designs with a high-quality IP portfolio targeted at next-generation electronic system-on-chips (SoCs).

The long-standing relationship between the two companies has resulted in the successful development of DesignWare PHY IP from 180-nm to 32-nm process technologies. GLOBALFOUNDRIES and Synopsys are the first to announce the development of USB, PCI Express, DDR, HDMI, SATA and XAUI PHY IP targeting 28-nm process technologies with scalability to future generations.

GLOBALFOUNDRIES' 28-nm high performance (HP) and super low power (SLP) technologies are optimized for fast processing with minimal leakage, making them ideal for a wide variety of applications from high-performance graphics and wired networking to low-power wireless mobile applications that require high processing speeds, small feature sizes, and long battery lifetime.

"This is another demonstration of the value delivered by our close collaboration with members of the GLOBALSOLUTIONS ecosystem," said Walter Ng, vice president of the IP ecosystem at GLOBALFOUNDRIES. "Our 28 nanometer HKMG processes with 'Gate First' technology are aimed at delivering a new level of performance and power efficiency for the next generation of SoC designs. By combining our leading-edge manufacturing capabilities with Synopsys' established leadership in delivering high-quality IP for the most advanced processes, we will enable our mutual customers to quickly ramp into high volume and bring their innovations to the marketplace."

Synopsys provides complete solutions consisting of digital controllers, PHYs and verification IP for commonly used protocols such as USB, PCI Express and SATA. The DesignWare PHY IP solutions target a broad range of high-performance, ultra low-power mobile and consumer applications, where the key requirements include minimal area and low dynamic and leakage power consumption. The PHY IP is designed to tolerate process, voltage and temperature variations and supports multiple power management features.

"By collaborating with GLOBALFOUNDRIES to deliver our PHY IP in the 28 nanometer process, Synopsys enables designers to meet the growing demands of a new generation of lower power, higher performance SoCs," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "Our successful track record of providing proven solutions in the GLOBALFOUNDRIES processes gives designers confidence that they can quickly migrate to this advanced process technology with significantly less risk and improved time-to-market."

Front-end design views for the DesignWare PHY IP supporting GLOBALFOUNDRIES' 28-nm process technologies are available now. Initial design kits and DesignWare PHY IP are scheduled for availability in Q1 of 2011. Additional products will be released throughout 2011.