STARC, Calypto and Virage Logic break new ground with industry’s lowest power design flow

SANTA CLARA, USA: Calypto Design Systems Inc., a leader in sequential analysis technology, announced its collaboration with Virage Logic Corp. and the Semiconductor Technology Academic Research Center (STARC) to dramatically reduce on-chip SoC power.

Extending its ongoing, independent efforts with STARC and Virage Logic, the multi-technology collaboration resulted in the development of a seamless flow for designs with various functional modes that control multiple on-chip power domains to achieve dramatic power savings.

Initial results show up to 50 percent dynamic power reduction and up to 40 percent leakage power reduction in embedded SoC memories using Calypto’s PowerPro MG tool and Virage Logic’s SiWare Memory compilers.

“Design teams are confronted with constant pressure to reduce SoC power. Without an automated flow to reduce memory power, designers are forced to engage in time-consuming analysis and error-prone manual modifications to the design,” said Nobuyuki Nishiguchi, VP, GM, Development Department-1 at STARC.

“Incorporating Calypto’s PowerPro MG and Virage Logic’s SiWare Memory IP into our low-power flow will enable designers to meet their design power goals in order to focus resources on bringing new levels of innovation to their products.”

Using Calypto’s patented sequential analysis technology, PowerPro MG (for Memory Gating) constructs new memory gating logic that works in conjunction with the low-power memory modes in Virage Logic’s SiWare Memory compilers to produce the lowest power memory implementation possible.

The SiWare Memory compilers provide several different low power modes – light sleep, deep sleep and shut down to allow designers to reduce leakage power when the memory is not being accessed. The compilers automatically generate PowerPro MG models enabling STARC to easily integrate PowerPro MG into their low power design flow.

“STARC continues to contribute valuable, innovative design flows to the semiconductor industry,” said Lisa Minwell, director of technical marketing for Virage Logic. “As the semiconductor industry’s trusted IP partner and leading provider of embedded memories, we are pleased to collaborate with Calypto and STARC to enable mutual customers to deliver the most advanced, power-efficient designs possible.”

“Reducing power in all of the key components of an SoC is critical to meeting today’s competitive design goals,” said Tom Sandoval, chief executive officer of Calypto. “Collaboration, such as this one between Calypto, Virage Logic, and STARC, is the most efficient way to make dramatic methodology improvements that enable our customers to deliver the most advanced, power-efficient designs ahead of their competition.”