Sidense granted anti-fuse memory cell patent by USPTO

OTTAWA, CANADA: Sidense, a leading developer of Logic Non-Volatile Memory (LNVM) IP cores, announced that the United States Patent and Trademark Office (USPTO) has recently granted the company Patent Number 7,755,162, "Anti-fuse Memory Cell."

The '162 patent adds to the Company's fast growing patent portfolio covering its 1T-Fuse memory technology. Sidense's 1T-Fuse Split-Channel bit cell is at the heart of its secure, reliable and cost-effective non-volatile, one-time programmable (OTP) memory IP products, comprising the SiPROM, SLP and ULP families.

The '162 is one of five US patents covering various aspects of the Split-Channel 1T bit-cell technology and its usage in OTP memory products, adding to 18 patents worldwide, granted to Sidense. With several more US patents pending, plus others worldwide, Sidense is well positioned to dominate the 1T OTP market and, to its knowledge, is the only commercially available 1T-based OTP product.

"This new patent on our anti-fuse memory technology reflects our constant strive to innovate and improve performance of our high-density OTP IP for the advanced CMOS processes," said Wlodek Kurjanowicz, Sidense Founder and CTO. "Patents are very important to Sidense and reinforce the value and uniqueness of Sidense memory IP to our customers."

The new USPTO Certificate comes on the heels of the USPTO's recent grant of a request to re-examine Sidense's '855 Patent claims. Commenting, Wlodek Kurjanowicz said, "Sidense welcomes the re-examination with enthusiasm. It provides yet another opportunity to reaffirm the differences between Sidense's state-of-the-art "split-channel" cell technology and prior attempts to build "1T eNVM" through various unworkable process modifications. We are quite confident that '855 claims will emerge strengthened and reinforced, as Sidense's 1T technology becomes increasingly recognized as the industry-standard OTP."

Sidense has 75 patents issued and pending on the company's Split-Channel anti-fuse array architecture, anti-fuse memory cell, high-speed OTP sensing scheme, and other components and methodologies that go into Sidense's OTP macrocells.