RICOH achieves full test coverage with ultra-low pin count using Mentor Graphics Tessent TestKompress

WILSONVILLE, USA: Mentor Graphics Corp. announced that Ricoh Co. Ltd has employed the Tessent TestKompress solution for an RF product currently under development to achieve full coverage in final IC testing using only three I/O pins.

In addition, the solution reduces the number of pattern loads needed for complete testing from ten to only four, providing a 60 percent reduction in manufacturing test time.

“Previously we were unable to meet our objective of 100% scan test overage during final package test because we were severely limited in the number of I/O pins available for testing,” said Fumiaki Kadowaki, Manager in Ricoh’s Imaging System LSI Development Center, CAD Engineering Section.

“Tessent TestKompress provided an alternative that allowed us to continue to use our existing test equipment, reduce the SCAN test interface to only three pins, and still reduce our test time. In addition, the Mentor solution provides us with excellent test failure diagnosis capability based on normal production test data, without having to run special failure analysis runs on failed parts.”

The new test flow overcomes previous limitations of test equipment hardware, test pattern generation software and test pin availability by employing patented Embedded Deterministic Test (EDT) technology in the TestKompress tool.

This approach combines a small amount of on-chip circuitry (generated by TestKompress in RTL) and unique test pattern generation algorithms to load highly compressed test patterns onto the chip with only a few I/O channels. Using one pin for scan-in, one for scan-out, one for clock and two for test mode control, the low pin count solution still managed to reduce the number of pattern loads form ten to four due to the extremely high compression achieved using Tessent TestKompress.

With future refinements to further increase compression, Ricoh expects to eliminate additional pattern loads completely, further reducing test times and increasing test throughput.

“Our customers are realizing fundamental improvements in test coverage and test throughput, thus improving test quality and reducing cost at the same time,” said Greg Aldrich, director of Marketing for Mentor’s silicon test solutions.

“With the ability to operate from a single scan channel and still provide very high levels of test time and data compression, Tessent TestKompress offers the flexibility to effectively test the broad range of devices with varying requirements that exist in today’s markets.”