Juniper completes world’s first network instruction set processor design using Mentor's Calibre and Design-for-Test solutions

WILSONVILLE, USA: Mentor Graphics Corp. announced that Juniper Networks has completed the world’s first network instruction set processor IC using Mentor Graphics physical verification and silicon test tools.

Juniper’s new processor is part of Juniper’s latest Junos Trio chipset that enables the delivery of Juniper’s MX-3D platforms. “We went with the Calibre verification platform because it gives a high level of confidence in the manufacturability of our design,” said Debashis Basu, senior director of Foundation Technologies at Juniper Networks.

“With a design of this size, we needed a solution that could deliver fast turnaround time. The Calibre user interface environment and scripting capability helped us to find and debug problems quickly, and automate chip assembly.”

Juniper employed a combination of Mentor’s embedded deterministic test pattern generation and memory BIST products to meet demanding test requirements. With hundreds of separate embedded memories, Juniper’s design presented a real test challenge to minimize routing congestion, enable at-speed testing, and keep real estate required for BIST controllers to a minimum.

Juniper was able to achieve their objectives using Mentor’s modular test flow, embedded deterministic pattern compression, and efficient memory BIST technology.

“Mentor Graphics is focused on providing solutions that meet the newest challenges our customers are facing at advanced IC technology nodes,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics.

“For physical design verification, testing and DFM, our goal is to deliver best-in-class technology through integrated platforms that also provide maximum flexibility to adapt to each customer’s unique requirements and design flows.”