EVE integrates Xilinx ISE Design Suite into emulation platforms

SAN JOSE, USA: EVE, the leader in hardware/software co-verification, today announced that it has integrated the latest version of the Xilinx's ISE Design Suite to its ZeBu (for Zero Bugs) emulation platforms.

Working in close partnership with Xilinx over several months, EVE’s R&D team tested the ISE Design Suite 11.1 on large system-on-chip (SoC) and application specific integrated circuit (ASIC) designs. The team used designs of several billion transistors that required hundreds of interconnected Virtex devices to ensure a high degree of success when placing and routing high-density Xilinx field programmable gate arrays (FPGAs).

Notes Ludovic Larzul, EVE’s vice president of engineering: “The integration of ISE Design Suite 11 into the ZeBu compiler significantly accelerates long compilation runs. We are seeing runtime drop by as much as 2X, allowing more turns per day. This is a huge feat since design teams worldwide use ZeBu to compile thousands of Virtex FPGAs everyday.”

“The relationship developed between EVE and Xilinx to advance the compilation capabilities of ISE Design Suite 11 could be a case book study on how companies can work together on problem solving,” says Tom Feist, senior marketing director for ISE Design Suite at Xilinx. “We are pleased with the results achieved and appreciate the contributions brought to us by EVE’s R&D team.”

The ZeBu emulation platforms are used for SoC hardware verification and software development, to shorten time to tapeout, improve product quality and eliminate costly respins, while accelerating software development ahead of silicon. They leverage the same hardware, design models and engineering resources across the entire design cycle, making it cost effective for every design team.