Magma's Talus 1.1 RTL-to-GDSII chip implementation system

BANGALORE, INDIA: Magma Design Automation Inc., a provider of chip design software, today announced the release of Talus 1.1, a new RTL-to-GDSII chip implementation system that delivers the fastest timing closure on the largest and most complex semiconductor designs.

Talus 1.1 utilizes the new Talus COre technology, which leverages Magma’s unified data model to perform timing optimization concurrently during routing, thus providing faster overall design closure with better performance and predictability.

This greatly enhances designers’ ability to achieve optimal results across a wide variety of designs -– while minimizing the need for user intervention. Unlike existing routing systems that perform optimization sequentially before and after place and route, and which focus only on layout-oriented routing factors such as design for manufacturability (DFM) or design rule checking (DRC), Talus focuses concurrently on timing and layout-driven metrics during routing.

In addition to its ability to provide the fastest turnaround on large designs, Talus 1.1 introduces the Talus Flow Manager with “out-of-the-box” design flows. Included with the release are out-of-the-box reference flows for RTL-to-GDSII, multi-Vdd, low-power design and high-performance design -– engineers can easily tune the reference flows for specific applications. Talus Flow Manager also introduces a new visual analysis environment, Talus Visual Volcano, that integrates and presents all design and analysis data via a common display.

“For engineers creating ICs at advanced geometries, big chips, or chips where power management is important, Talus is superior to design systems from other EDA vendors,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.

“The first breakthrough at Magma occurred when we added concurrent optimization to placement in our initial product, Blast Fusion. Our new Talus Core technology raises the bar by adding concurrent optimization to routing, resulting in faster design closure and better timing performance. Unlike other approaches, Talus delivers a level of design speed and efficiency that is ideal for small-geometry designs -– this also makes it ideal for designers creating big chips, those with 5 million gates or more. This will take on greater commercial significance for our customers as an increased portion of their designs target applications such as netbooks, smartphones and embedded devices that require bigger and more complex chips but also must be designed for low power.”

Talus 1.1 was created to deliver optimal quality of results out of the box at advanced process nodes. It has already been used to tape out numerous production chips at 40 nm, and is presently ready for designs at 32 nm and 28 nm. Such technology is commonly found in System-on-a-Chip (SoC) designs, which integrate computing capabilities on a single chip.

Talus COre technology
The heart of the improvements in Talus 1.1 is its Concurrent Optimizing Routing Engine (COre) technology. At advanced geometries, complex resistance effects, increased via resistance and crosstalk can create a large timing disconnect between placed gates and final routing. Dealing with optimization and routing sequentially results in a suboptimal solution with unpredictable results.

Traditional solutions must spend time optimizing the design after routing to get the necessary accuracy, but at the cost of long runtimes. Talus COre focuses on applying the full scope of timing optimization incrementally during routing. Every aspect of the routing algorithms -– from topology generation to layer assignment, track assignment and DRC cleanup -– is timing and crosstalk aware. This allows the design to converge faster and eliminate post-route timing surprises.

Talus COre is coupled with Talus’ SDF-based optimization to remove the need for manual engineering change orders (ECOs) to close timing.

The addition of the Talus COre technology allows Talus 1.1 to deliver optimal quality of results out of the box on advanced process node design challenges. It has already been used to complete production designs where it provided a better than 5 times runtime improvement over competitive solutions and previous Talus versions. In customer beta testing on 40-nm designs ranging from 2 million to 4 million gates, with frequencies from 400 MHz to 800 MHz, Talus 1.1 produced 75 percent better timing with 10 percent fewer vias than the competitive results.

Talus Flow Manager and Visual Volcano
Talus 1.1 also introduces the new Talus Flow Manager that provides an out-of-the-box Talus RTL-to-GDSII design flow tuned to deliver optimal results. Designers can easily customize the reference flow and tailor it to their own needs, developing specific flows for various projects or applications.

Additional reference flows include templates for the implementation of multiple-voltage (MVdd), multiple-mode and multiple-corner (MMMC) designs, as well as low-power and high-performance designs. Ease of use and cost of adoption is dramatically improved through the use of these pre-qualified flows.

The Talus Flow Manager includes the new Talus Visual Volcano, a new technology designed to help designers make better decisions faster. The Talus Visual Volcano analysis environment offers an integrated information display that allows an engineer to quickly track many parameters of the design, including run times, timing, power and area.

MMMC design management is made easier by simplifying the control over active versus reported scenarios, and displaying results for all scenarios concurrently. By consolidating this data into charts and graphs, the Talus Visual Volcano saves time and improves efficiency by removing the need for tedious analysis of log files and textual reports.

Production shipments of Talus 1.1 will begin in June 2009.