NVIDIA deploys Magma Talus 1.1 into production

BANGALORE, INDIA: Magma Design Automation Inc. announced that NVIDIA Corp. deployed Magma’s Talus 1.1 IC implementation system into full production.

Talus 1.1 offers significant improvements in routing, optimization and runtime as well as enhanced usability features. NVIDIA had been participating in the beta testing of the latest Talus release and, based on the positive results of the testing and improved flow performance, made the decision to start using Talus 1.1 for NVIDIA’s production design projects.

“We have recently upgraded to Talus 1.1 in our production environment based on significant improvements in the core algorithms, flow convergence and the overall usability,” said Patrick Sproule, manager of VLSI Design for NVIDIA. “In particular, the improvements in runtime, timing convergence and ECO routing have improved our throughput and quality of results.”

Magma’s unified data model is a key factor in the performance of the Talus chip implementation system. All the implementation and analysis engines in the Talus flow are built around, and have access to, the same data, and as a result flow convergence and turnaround times are shortened and optimization steps can be applied across the flow.

“We made a significant R&D investment in Talus 1.1 with the focus on improving overall performance and convergence while also improving the ease-of-use and efficiency of the system,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.

“Our customers are implementing very complex chips and need the combination of a powerful, fast, high-quality chip design system that is also easy to drive. We made a specific effort in Talus 1.1 to develop simplified flows that reduce the number of commands required, but still deliver superior results in the finished design. We are very pleased with the fact that Talus 1.1 performed so well for NVIDIA that they have moved it onto their production chip design projects.”

Talus platform
Talus is a completely unified RTL-to-GDSII system for design implementation, with advanced capabilities for nanometer design. To address shorter time-to-market windows, Talus is the first implementation solution to multi-process the entire IC design flow. Its front-end design system provides logic designers with a fast, high-capacity, physically aware synthesis capability.

Its physical design system addresses variability and multimode/multicorner complexity with new optimization, place and route, and clock tree synthesis technology. To reduce leakage and dynamic power, Talus also provides a complete low-power design system. To improve manufacturability and reliability, Talus provides built-in design-for-manufacturing (DFM) features such as redundant via insertion, recommended end-of-line extension, and wire spreading & widening.