Fujitsu Microelectronics adopts Mentor's Calibre design-to-silicon platform

WILSONVILLE, USA: Mentor Graphics Corp. announced that Fujitsu Microelectronics Ltd has qualified and adopted the Calibre design-to-silicon platform for physical verification and design-for-manufacturing (DFM) of advanced IC products.

Fujitsu Microelectronics’ Mentor-based flow includes the sign-off standard Calibre verification platform with Calibre nmDRC, LVS, and xRC tools, and Mentor’s comprehensive DFM solution for manufacturing variability, an integrated tool suite for critical area analysis, litho-friendly design, and 3D variability.

The 3D variability solution provides improved planarity by enabling highly optimized fill based on either complex geometry-based rules, or full thickness (CMP) simulation.

“Fujitsu Microelectronics' leading-edge technologies require tight control over thickness variation. Density-based fill is a starting point and an improvement over traditional dummy fill, but at smaller features sizes our analysis shows that we need to consider more than just density,” said Noboru Yokota, General Manager of the Technology Development Division at Fujitsu Microelectronics. “The Mentor solution is unique because it can handle complex equations combining all the factors required to compute an optimum fill that achieves our planarity goals with as few added shapes as possible.”

“Our long-term partnership with Fujitsu Microelectronics has resulted in a complete solution that meets Fujitsu Microelectronics’ verification and DFM requirements for their latest IC designs regardless of which process offering is being targeted,” said Joseph Sawicki, Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics.

“Our customers are moving to all-Mentor flows because we offer both the best-in-class technology for each design task, as well as the ease of integration and use that can only be achieved with a single integrated platform and tools built from the ground up to work together seamlessly,” he added.

Mentor’s DFM solution
The Calibre nm platform, with the Calibre nmDRC and Calibre LVS tools, has become the golden standard for verification of advanced ICs. Mentor’s comprehensive DFM solution is tightly integrated with the Calibre platform and supports the highest performance designs at advanced nodes with better control of manufacturing variability for cell libraries as well as full-chip layouts.

The Calibre DFM solution includes the Calibre LFDproduct, which provides accurate modeling of lithographic process and etch characteristics, and is the standard sign-off flow for litho hotspot and variability analysis for IP and full-chip applications.

It is fully integrated with the Calibre nmDRC, Calibre LVS (Layout vs. Schematic) and Calibre xRC products, allowing critical device and interconnect characteristics to be extracted based on accurately-modeled, “as-built” contour geometries. The resulting physical data can be plugged into a SPICE simulator to produce an accurate timing simulation of how physical blocks will actually perform.

The Calibre DFM solution includes the Calibre YieldAnalyzer and Calibre YieldEnhancer products for automated CAA analysis and fixing. The YieldEnhancer tool includes a SmartFill intelligent fill capability, which performs metal fills based on metal density and density gradients.

The Calibre CMPAnalyzer tool enables CMP planarity analysis and fill enhancement based on comprehensive, foundry-specific thickness models. Together, these products comprehensively address the variability issues of manufacturing at 65nm and below by making the physical design flow more process-aware and robust, reducing yield surprises late in the development cycle.