SANTA CLARA, USA: SiliconBlue Technologies, the leading supplier of ultra-low power, single-chip SRAM FPGAs, recently announced that Siltrontech Electronics Corp. has been selected as a distributor for mainland China and Taiwan.
Established in 1992, Siltrontech will provide sales and technical support for SiliconBlue’s ultra-low power, single-chip iCE65 mobileFPGAs targeted at the rapidly-growing consumer handheld market.
"Siltrontech’s experience selling and supporting products for the mobile communications market is a great benefit to SiliconBlue as we expand our sales force in mainland China and Taiwan," said Kapil Shankar, CEO of SiliconBlue. "We are delighted to have a world class distributor selling and supporting our ultra-low power FPGAs in such an important market."
"SiliconBlue offers the most innovative FPGAs perfectly suited to our customer’s requirements," said Tony Chou, President at Siltrontech. "The iCE65 FPGA is an excellent addition to our product line, and provides an exciting new alternative to consumer hand-held designers who need the benefits of ultra-low power, single-chip, low-cost, constrained space and fast time-to-market for applications such as mobile phones, MIDs, eBooks, netbooks and digital picture frames."
iCE65 family of FPGAs
iCE65 ultra-low power FPGAs are the premier programmable logic solution for consumer, battery-based applications such as smart phones, eBooks/ePaper, netbooks, digital picture frames, mobile internet devices, portable media players, handheld POS, medical instruments, digital still cameras and flash camcorders.
These applications have an extremely short development and product life cycle; therefore, by combining the reprogramming flexibility benefit of FPGAs with the low cost, low power and single-chip benefits of ASICs, iCE65 FPGAs offer the “best of both worlds” solution for handheld consumer system designers.
Sunday, May 31, 2009
TES reinforces position in telematics device market
LANGON, FRANCE:TES Electronic Solutions, a leader in electronic design and manufacturing services, recently unveiled its latest initiative in the telematics market; a reference device called TITAN that can be quickly customised and tailored to address the majority of Telematics Service Providers requirements.
TES is leveraging its complete service breadth of electronic design and manufacturing together with its vast experience in RF and positioning technologies to the specific segment of telematics devices. The TITAN platform is the first of a range of reference platforms.
It is available in two configurations; a thin client device running Linux or Windows CE or as a low cost M2M platform. All reference designs and devices provide GPS, GSM/GPRS and basic but highly configurable I/O, while the thin client device offers an ARM 9 processor in addition to enable application deployment on the device.
The reference platform strategy is complemented with TES Electronic Solutions’ extensive design team to provide tailored telematics hardware and software solutions which can be rapidly moved into volume manufacturing in TES factories. Once in volume supply, customers can further benefit from TES’ logistics platform for device configuration and distribution to installation centres.
“In addition to applications that track vehicles and capital equipment, we are seeing new areas emerging such Pay As You Drive, Pay How You Drive and Pay When You Drive”, said Nick Walker, Senior Vice President of Business Development at TES. “Every application is different and needs optimised hardware and software in this rapidly growing and competitive market”, continued Walker.
“TES Electronic Solutions have all the skills and expertise to create, design, manufacture and distribute optimised telematics devices for every application. It’s a custom business where one size does not fit all, but all require a common set of basic functions. Our approach to the business is geared to allow the telematics service providers to focus on building out the applications based on the device while we take care of the device delivery”, he concluded.
Available now, the TITAN reference device is fitted with a Telit quad band modem including SiRF StarIII GPS that provides the communications and positioning technology, which can operate standalone for simple cost optimised applications. In the top end configuration, TITAN also includes an ARM 9 processor module for the OS and application for the more sophisticated telematics application.
The TITAN device is the first step in an emerging telematics strategy from TES. Further announcements will be made in the coming weeks.
TES is leveraging its complete service breadth of electronic design and manufacturing together with its vast experience in RF and positioning technologies to the specific segment of telematics devices. The TITAN platform is the first of a range of reference platforms.
It is available in two configurations; a thin client device running Linux or Windows CE or as a low cost M2M platform. All reference designs and devices provide GPS, GSM/GPRS and basic but highly configurable I/O, while the thin client device offers an ARM 9 processor in addition to enable application deployment on the device.
The reference platform strategy is complemented with TES Electronic Solutions’ extensive design team to provide tailored telematics hardware and software solutions which can be rapidly moved into volume manufacturing in TES factories. Once in volume supply, customers can further benefit from TES’ logistics platform for device configuration and distribution to installation centres.
“In addition to applications that track vehicles and capital equipment, we are seeing new areas emerging such Pay As You Drive, Pay How You Drive and Pay When You Drive”, said Nick Walker, Senior Vice President of Business Development at TES. “Every application is different and needs optimised hardware and software in this rapidly growing and competitive market”, continued Walker.
“TES Electronic Solutions have all the skills and expertise to create, design, manufacture and distribute optimised telematics devices for every application. It’s a custom business where one size does not fit all, but all require a common set of basic functions. Our approach to the business is geared to allow the telematics service providers to focus on building out the applications based on the device while we take care of the device delivery”, he concluded.
Available now, the TITAN reference device is fitted with a Telit quad band modem including SiRF StarIII GPS that provides the communications and positioning technology, which can operate standalone for simple cost optimised applications. In the top end configuration, TITAN also includes an ARM 9 processor module for the OS and application for the more sophisticated telematics application.
The TITAN device is the first step in an emerging telematics strategy from TES. Further announcements will be made in the coming weeks.
Saturday, May 30, 2009
Accelerometers set to become leading MEMS device in 2013
EL SEGUNDO, USA: When you turn your iPhone to the side and the screen automatically adjusts from portrait to landscape view, there’s an accelerometer at work. When you swing your Wii controller and bowl a virtual strike, there’s an accelerometer at work.
Indeed, accelerometers in recent years have emerged as a critical input device for some of the world’s hottest electronic products, causing shipments to boom. This will make accelerometers the top-selling Microelectromechanical System (MEMS) device by 2013, according to iSuppli Corp.
The global MEMS accelerometer market will expand to $1.7 billion in 2013, up from $947.7 million in 2007, as presented in the figure.
Source: iSuppli
“Due to this rapid sales growth, accelerometers by 2013 will displace the current leading MEMS products—inkjet heads and Digital Light Processing (DLP) chips—to become the dominant type of MEMS device sold worldwide in 2013,” said Jérémie Bouchaud, principal analyst, MEMS, for iSuppli. “Consumers’ desire for motion-sensing in smart phones and video game systems will boost demand for accelerometers.”
The boom in accelerometer demand will come as a boon to the health of the overall MEMS market. Although global MEMS revenue will decline by 8 percent in 2009—the second decline in market history following a 7 percent decrease in 2008—accelerometers will still manage 1.8 percent growth. Accelerometer revenue will rise by 14.1 percent in 2010 and will maintain double-digit percentage growth in 2011 and 2012.
“A major catalyst for the rise in accelerometer sales is pricing,” Bouchaud noted. “Accelerometers broke the magic $1 barrier in 2008, making them attractive in a larger number of products. Their prices will continue to decline in the coming years, widening their appeal beyond smart phones to reach the wider mobile handset market.”
In 2009, revenue from consumer and mobile applications for accelerometers is expected to exceed that of automotive applications. Until now, Automotive has been the biggest application by far for accelerometers, but this area now is suffering from the global collapse of car production.
Automotive applications accounted for 40 percent of global accelerometer revenue in 2008, down from 78 percent in 2006. In contrast, consumer electronics and wireless accelerometer revenue rose from 22 percent to 58 percent during the same period.
STMicroelectronics rides consumer wave to top of accelerometer market
In 2006, the top five accelerometer suppliers -- Freescale, Analog Devices, Bosch, VTI and Denso -- almost exclusively served the automotive market. However, by the end of 2008, STMicroelectronics had taken the lead in accelerometers based on its significant success in supplying the burgeoning consumer and wireless communications markets.
STMicroelectronics’ global accelerometer revenue rose to $220 million in 2008, up by nearly a factor of eight from $29 million in 2007. The company’s accelerometer market share rose to 20 percent in 2008, up from 4 percent in 2006.
Indeed, accelerometers in recent years have emerged as a critical input device for some of the world’s hottest electronic products, causing shipments to boom. This will make accelerometers the top-selling Microelectromechanical System (MEMS) device by 2013, according to iSuppli Corp.
The global MEMS accelerometer market will expand to $1.7 billion in 2013, up from $947.7 million in 2007, as presented in the figure.
Source: iSuppli“Due to this rapid sales growth, accelerometers by 2013 will displace the current leading MEMS products—inkjet heads and Digital Light Processing (DLP) chips—to become the dominant type of MEMS device sold worldwide in 2013,” said Jérémie Bouchaud, principal analyst, MEMS, for iSuppli. “Consumers’ desire for motion-sensing in smart phones and video game systems will boost demand for accelerometers.”
The boom in accelerometer demand will come as a boon to the health of the overall MEMS market. Although global MEMS revenue will decline by 8 percent in 2009—the second decline in market history following a 7 percent decrease in 2008—accelerometers will still manage 1.8 percent growth. Accelerometer revenue will rise by 14.1 percent in 2010 and will maintain double-digit percentage growth in 2011 and 2012.
“A major catalyst for the rise in accelerometer sales is pricing,” Bouchaud noted. “Accelerometers broke the magic $1 barrier in 2008, making them attractive in a larger number of products. Their prices will continue to decline in the coming years, widening their appeal beyond smart phones to reach the wider mobile handset market.”
In 2009, revenue from consumer and mobile applications for accelerometers is expected to exceed that of automotive applications. Until now, Automotive has been the biggest application by far for accelerometers, but this area now is suffering from the global collapse of car production.
Automotive applications accounted for 40 percent of global accelerometer revenue in 2008, down from 78 percent in 2006. In contrast, consumer electronics and wireless accelerometer revenue rose from 22 percent to 58 percent during the same period.
STMicroelectronics rides consumer wave to top of accelerometer market
In 2006, the top five accelerometer suppliers -- Freescale, Analog Devices, Bosch, VTI and Denso -- almost exclusively served the automotive market. However, by the end of 2008, STMicroelectronics had taken the lead in accelerometers based on its significant success in supplying the burgeoning consumer and wireless communications markets.
STMicroelectronics’ global accelerometer revenue rose to $220 million in 2008, up by nearly a factor of eight from $29 million in 2007. The company’s accelerometer market share rose to 20 percent in 2008, up from 4 percent in 2006.
GSA appoints Neil Kim as new director
SAN JOSE, USA: Global Semiconductor Alliance (GSA), the platform for global collaboration, announces its most recent addition to the board of directors, Neil Kim, Senior Vice President of Operations and Central Engineering at Broadcom Corporation.
At Broadcom, Kim is responsible for all global manufacturing activities, including foundry operation, packaging and test engineering as well as setting the process technology direction. Additionally, he is responsible for engineering activities that include the development of analog mixed-signal and radio frequency (RF) products and building Broadcom's library of core technologies.
He joined Broadcom as director of engineering in January 2000 and became vice president of central engineering in October 2001.
Prior to joining Broadcom, Kim held a series of progressively senior technical and management positions at Western Digital Corporation, where his last position was vice president of engineering. He received a B.S.E.E. from the University of California, Berkeley.
In his position at Broadcom, Kim manages the company’s vital relationships with its foundries and assembly and test suppliers.
Moreover, his extensive knowledge in analog mixed-signal and RF products brings value to GSA by enabling a better understanding of the complexity involved in managing the analog mixed-signal and RF product deliverables. His addition to the GSA board of directors will enhance its diversity and improve the Alliance’s ability to service the global supply-chain.
“I appreciate this appointment by the board and look forward to working with my peers, partners and competitors to bring about a more efficient ecosystem so that we all benefit. GSA is an exceptional organization in that it identifies challenges and opportunities and achieves maximum value for the industry,” stated Neil Kim.
Broadcom, a GSA member since 1998, is a major technology innovator and global leader in semiconductors for wired and wireless communications. Broadcom products enable the delivery of voice, video, data and multimedia to and throughout the home, the office and the mobile environment. “Broadcom has been a great supporter of GSA over the life of the Alliance. They have established themselves as a role and success model for the semiconductor community. We are pleased that Neil Kim will represent them on our board of directors,” said Jodi Shelton, president of GSA.
“Neil’s broad knowledge and experience provides an additional perspective of managing a multifaceted supply chain and understanding the challenges that companies face. This will further develop our ability to facilitate and drive solutions to the industry. It is our ambition to learn and grow from experts like Kim. His contribution will be of great benefit to GSA’s continued success,” Shelton further commented.
The GSA board of directors is comprised of 25 industry executives representing all sectors of the semiconductor industry and includes all geographies and representatives from critical supply partners.
At Broadcom, Kim is responsible for all global manufacturing activities, including foundry operation, packaging and test engineering as well as setting the process technology direction. Additionally, he is responsible for engineering activities that include the development of analog mixed-signal and radio frequency (RF) products and building Broadcom's library of core technologies.
He joined Broadcom as director of engineering in January 2000 and became vice president of central engineering in October 2001.
Prior to joining Broadcom, Kim held a series of progressively senior technical and management positions at Western Digital Corporation, where his last position was vice president of engineering. He received a B.S.E.E. from the University of California, Berkeley.
In his position at Broadcom, Kim manages the company’s vital relationships with its foundries and assembly and test suppliers.
Moreover, his extensive knowledge in analog mixed-signal and RF products brings value to GSA by enabling a better understanding of the complexity involved in managing the analog mixed-signal and RF product deliverables. His addition to the GSA board of directors will enhance its diversity and improve the Alliance’s ability to service the global supply-chain.
“I appreciate this appointment by the board and look forward to working with my peers, partners and competitors to bring about a more efficient ecosystem so that we all benefit. GSA is an exceptional organization in that it identifies challenges and opportunities and achieves maximum value for the industry,” stated Neil Kim.
Broadcom, a GSA member since 1998, is a major technology innovator and global leader in semiconductors for wired and wireless communications. Broadcom products enable the delivery of voice, video, data and multimedia to and throughout the home, the office and the mobile environment. “Broadcom has been a great supporter of GSA over the life of the Alliance. They have established themselves as a role and success model for the semiconductor community. We are pleased that Neil Kim will represent them on our board of directors,” said Jodi Shelton, president of GSA.
“Neil’s broad knowledge and experience provides an additional perspective of managing a multifaceted supply chain and understanding the challenges that companies face. This will further develop our ability to facilitate and drive solutions to the industry. It is our ambition to learn and grow from experts like Kim. His contribution will be of great benefit to GSA’s continued success,” Shelton further commented.
The GSA board of directors is comprised of 25 industry executives representing all sectors of the semiconductor industry and includes all geographies and representatives from critical supply partners.
Friday, May 29, 2009
IC Validator offers step up in physical designer's productivity
Recently, Synopsys Inc. introduced an IC Validator design rule checking/layout verification signoff (DRC/LVS) for in-design physical verification and signoff for advanced designs at 45nm and below.
Said to provide a step up in physical designer productivity, it is architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use.
What does IC Validator do?
According to Sanjay Bali, Director of Marketing, Physical Verification & DFM, Synopsys, the IC Validator is a complete physical verification tool, performing increasingly complex DRC and LVS sign-off checks.
It has been specifically architected for in-design physical verification. This means: the place-and-route engineers can run DRC and practical DFM steps alongside place and route within the familiar IC Compiler physical design environment.
And, why need for such a solution? He added that three key summary challenges are driving the need for a new approach and hence the new tool. These are:
a) Increase in complexity and count of manufacturing rules.
b) Unabated growth on design complexity.
c) Increasing DFM challenges, which just cannot be handled in a post processing approach.
Currently, the solution is aimed at 45nm and below as these nodes largely represent the challenges listed above.
Enhancing physical designer's productivity
Three key tenants of the IC Validator that offer improved physical designer productivity are:
a) High accuracy necessary for leading-edge process nodes.
b) Superior scalability for efficient utilization of available hardware. And,
c) Ease of use with seamless integration of IC Validator and IC Compiler
Bali said: "The IC Validator has been architected from the ground up for in-design physical verification. In-design physical verification enables place-and-route engineers to accelerate the time to tapeout by enabling sign-off quality physical verification from within implementation or physical design. Physical designers designing with IC Compiler can now benefit from the in-design physical verification approach with the push of a button, incurring minimal overhead cost to eliminate surprises late in the design.
"With the verify-as-you-go approach replacing the implement-then-verify approach, physical designers can significantly reduce iteration count, eliminate streamouts and streamins, and accelerate time to tapeout. In addition, the integration enables several productivity enhancing flows like incremental DRC verification, incremental metal fill flows and ECO flows -- all leading to significant reduction in time to tapeout."
It would be interesting to determine or know by approximately what percent is the total physical verification time reduced, and what all does it cover in the process?
Bali added that in extreme cases, finding and fixing DRC violations can easily impact the schedules by a few weeks! The key here is that physical designers typically wait until the final stages of the tapeout to run physical verification. Inevitably, the schedule at this point is squeezed and the cost of fixing the error is high.
"With a sign-off quality physical verification tool integrated into the physical design environment, place-and-route engineers can verify as they implement and eliminate late surprises while speeding up the total physical verification turnaround time. In addition, the outcome of this process is a sign-off clean design.
Production ready!
The Synopsys IC Validator is also said to 'production ready!" What exactly does that mean?
The IC Validator has been successfully used to tapeout designs at several chip manufacturers, said Bali. In addition, it is currently being used for production designs at Nvidia and Toshiba. Besides other leading foundry's and chip manufactures it is also qualified by TSMC for 40nm and 28nm process nodes.
For those interested, Toshiba already has Synopsys as its key EDA partner, and NVIDIA adopted the IC Validator for sign-off physical verification, within days of its launch! More are bound to follow!
Saving design spins!
Will the IC Validator approach be able to save design spins? How much is the physical design cycle time reduced?
With the in-design physical verification, place-and-route engineers will be able to run sign-off quality DRC checks, timing aware and sign-off quality metal fill, all within the familiar IC Compiler environment. Linear scalability for efficient use of hardware, sign-off accuracy and integration with IC Compiler will enable productivity enhancing flows like auto detect and autofix, incremental verification flows -- all can significantly reduce time to tapeout.
How can it help in avoiding the painful sign-off failure-to-physical-redesign iterations that are increasingly common below 90nm?
With the seamless integration of the IC Validator with the IC Compiler, physical designers can now verify the design as they implement for manufacturing sign-off accuracy.
Incremental DRC's strength
How good is the incremental design-rule checker (DRC)? Is it really parallelized for the multicore servers?
According to Bali, incremental flows are one of the strongest tenants of IC Validator. To improve physical designer productivity, rule-based only or layer-based only incremental verification runs can be initiated from within IC Compiler.
He said: "For ECO validation, the IC Validator supports window or an area-based incremental verification approach to speed up surgical checks. The incremental flows are meant to be quick, but the IC Validator has multicore capability to further speed up the process."
The IC Validator discovers and fixes design rule violations within the global context of the design as well. How is this made possible?
With the in-design physical verification, the IC Validator can accurately and automatically identify DRC violation and automatically provide fix guidance to IC Compiler to fix the violation and then re-verify it again.
Handling metal fills and design changes
Operations typically performed during physical verification, such as metal fills, may trigger additional design changes to achieve timing closure. How is this handled by the IC Validator?
Bali said that the prevailing post-processing oriented DFM flows introduce excessive and lengthy discover-fix iterations. Metal fill insertion, a mandatory DFM step at the advanced nodes, exemplifies this issue.
"Physical designers stream out the timing closed post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This multi-hour discover-fix loop is typically repeated per block till the post-fill design is both signoff qualified and timing clean.
"With in-design physical verification, the IC Validator and IC Compiler address the challenges of DFM, within the place-and-route environment. The seamless integration enables a single pass metal fill flow that is timing aware and of signoff quality and is void of expensive streamouts and streamins," he added.
Said to provide a step up in physical designer productivity, it is architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use.
What does IC Validator do?
According to Sanjay Bali, Director of Marketing, Physical Verification & DFM, Synopsys, the IC Validator is a complete physical verification tool, performing increasingly complex DRC and LVS sign-off checks.
It has been specifically architected for in-design physical verification. This means: the place-and-route engineers can run DRC and practical DFM steps alongside place and route within the familiar IC Compiler physical design environment.
And, why need for such a solution? He added that three key summary challenges are driving the need for a new approach and hence the new tool. These are:
a) Increase in complexity and count of manufacturing rules.
b) Unabated growth on design complexity.
c) Increasing DFM challenges, which just cannot be handled in a post processing approach.
Currently, the solution is aimed at 45nm and below as these nodes largely represent the challenges listed above.
Enhancing physical designer's productivity
Three key tenants of the IC Validator that offer improved physical designer productivity are:
a) High accuracy necessary for leading-edge process nodes.
b) Superior scalability for efficient utilization of available hardware. And,
c) Ease of use with seamless integration of IC Validator and IC Compiler
Bali said: "The IC Validator has been architected from the ground up for in-design physical verification. In-design physical verification enables place-and-route engineers to accelerate the time to tapeout by enabling sign-off quality physical verification from within implementation or physical design. Physical designers designing with IC Compiler can now benefit from the in-design physical verification approach with the push of a button, incurring minimal overhead cost to eliminate surprises late in the design.
"With the verify-as-you-go approach replacing the implement-then-verify approach, physical designers can significantly reduce iteration count, eliminate streamouts and streamins, and accelerate time to tapeout. In addition, the integration enables several productivity enhancing flows like incremental DRC verification, incremental metal fill flows and ECO flows -- all leading to significant reduction in time to tapeout."
It would be interesting to determine or know by approximately what percent is the total physical verification time reduced, and what all does it cover in the process?
Bali added that in extreme cases, finding and fixing DRC violations can easily impact the schedules by a few weeks! The key here is that physical designers typically wait until the final stages of the tapeout to run physical verification. Inevitably, the schedule at this point is squeezed and the cost of fixing the error is high.
"With a sign-off quality physical verification tool integrated into the physical design environment, place-and-route engineers can verify as they implement and eliminate late surprises while speeding up the total physical verification turnaround time. In addition, the outcome of this process is a sign-off clean design.
Production ready!
The Synopsys IC Validator is also said to 'production ready!" What exactly does that mean?
The IC Validator has been successfully used to tapeout designs at several chip manufacturers, said Bali. In addition, it is currently being used for production designs at Nvidia and Toshiba. Besides other leading foundry's and chip manufactures it is also qualified by TSMC for 40nm and 28nm process nodes.
For those interested, Toshiba already has Synopsys as its key EDA partner, and NVIDIA adopted the IC Validator for sign-off physical verification, within days of its launch! More are bound to follow!
Saving design spins!
Will the IC Validator approach be able to save design spins? How much is the physical design cycle time reduced?
With the in-design physical verification, place-and-route engineers will be able to run sign-off quality DRC checks, timing aware and sign-off quality metal fill, all within the familiar IC Compiler environment. Linear scalability for efficient use of hardware, sign-off accuracy and integration with IC Compiler will enable productivity enhancing flows like auto detect and autofix, incremental verification flows -- all can significantly reduce time to tapeout.
How can it help in avoiding the painful sign-off failure-to-physical-redesign iterations that are increasingly common below 90nm?
With the seamless integration of the IC Validator with the IC Compiler, physical designers can now verify the design as they implement for manufacturing sign-off accuracy.
Incremental DRC's strength
How good is the incremental design-rule checker (DRC)? Is it really parallelized for the multicore servers?
According to Bali, incremental flows are one of the strongest tenants of IC Validator. To improve physical designer productivity, rule-based only or layer-based only incremental verification runs can be initiated from within IC Compiler.
He said: "For ECO validation, the IC Validator supports window or an area-based incremental verification approach to speed up surgical checks. The incremental flows are meant to be quick, but the IC Validator has multicore capability to further speed up the process."
The IC Validator discovers and fixes design rule violations within the global context of the design as well. How is this made possible?
With the in-design physical verification, the IC Validator can accurately and automatically identify DRC violation and automatically provide fix guidance to IC Compiler to fix the violation and then re-verify it again.
Handling metal fills and design changes
Operations typically performed during physical verification, such as metal fills, may trigger additional design changes to achieve timing closure. How is this handled by the IC Validator?
Bali said that the prevailing post-processing oriented DFM flows introduce excessive and lengthy discover-fix iterations. Metal fill insertion, a mandatory DFM step at the advanced nodes, exemplifies this issue.
"Physical designers stream out the timing closed post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This multi-hour discover-fix loop is typically repeated per block till the post-fill design is both signoff qualified and timing clean.
"With in-design physical verification, the IC Validator and IC Compiler address the challenges of DFM, within the place-and-route environment. The seamless integration enables a single pass metal fill flow that is timing aware and of signoff quality and is void of expensive streamouts and streamins," he added.
NVIDIA deploys Magma Talus 1.1 into production
BANGALORE, INDIA: Magma Design Automation Inc. announced that NVIDIA Corp. deployed Magma’s Talus 1.1 IC implementation system into full production.
Talus 1.1 offers significant improvements in routing, optimization and runtime as well as enhanced usability features. NVIDIA had been participating in the beta testing of the latest Talus release and, based on the positive results of the testing and improved flow performance, made the decision to start using Talus 1.1 for NVIDIA’s production design projects.
“We have recently upgraded to Talus 1.1 in our production environment based on significant improvements in the core algorithms, flow convergence and the overall usability,” said Patrick Sproule, manager of VLSI Design for NVIDIA. “In particular, the improvements in runtime, timing convergence and ECO routing have improved our throughput and quality of results.”
Magma’s unified data model is a key factor in the performance of the Talus chip implementation system. All the implementation and analysis engines in the Talus flow are built around, and have access to, the same data, and as a result flow convergence and turnaround times are shortened and optimization steps can be applied across the flow.
“We made a significant R&D investment in Talus 1.1 with the focus on improving overall performance and convergence while also improving the ease-of-use and efficiency of the system,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.
“Our customers are implementing very complex chips and need the combination of a powerful, fast, high-quality chip design system that is also easy to drive. We made a specific effort in Talus 1.1 to develop simplified flows that reduce the number of commands required, but still deliver superior results in the finished design. We are very pleased with the fact that Talus 1.1 performed so well for NVIDIA that they have moved it onto their production chip design projects.”
Talus platform
Talus is a completely unified RTL-to-GDSII system for design implementation, with advanced capabilities for nanometer design. To address shorter time-to-market windows, Talus is the first implementation solution to multi-process the entire IC design flow. Its front-end design system provides logic designers with a fast, high-capacity, physically aware synthesis capability.
Its physical design system addresses variability and multimode/multicorner complexity with new optimization, place and route, and clock tree synthesis technology. To reduce leakage and dynamic power, Talus also provides a complete low-power design system. To improve manufacturability and reliability, Talus provides built-in design-for-manufacturing (DFM) features such as redundant via insertion, recommended end-of-line extension, and wire spreading & widening.
Talus 1.1 offers significant improvements in routing, optimization and runtime as well as enhanced usability features. NVIDIA had been participating in the beta testing of the latest Talus release and, based on the positive results of the testing and improved flow performance, made the decision to start using Talus 1.1 for NVIDIA’s production design projects.
“We have recently upgraded to Talus 1.1 in our production environment based on significant improvements in the core algorithms, flow convergence and the overall usability,” said Patrick Sproule, manager of VLSI Design for NVIDIA. “In particular, the improvements in runtime, timing convergence and ECO routing have improved our throughput and quality of results.”
Magma’s unified data model is a key factor in the performance of the Talus chip implementation system. All the implementation and analysis engines in the Talus flow are built around, and have access to, the same data, and as a result flow convergence and turnaround times are shortened and optimization steps can be applied across the flow.
“We made a significant R&D investment in Talus 1.1 with the focus on improving overall performance and convergence while also improving the ease-of-use and efficiency of the system,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.
“Our customers are implementing very complex chips and need the combination of a powerful, fast, high-quality chip design system that is also easy to drive. We made a specific effort in Talus 1.1 to develop simplified flows that reduce the number of commands required, but still deliver superior results in the finished design. We are very pleased with the fact that Talus 1.1 performed so well for NVIDIA that they have moved it onto their production chip design projects.”
Talus platform
Talus is a completely unified RTL-to-GDSII system for design implementation, with advanced capabilities for nanometer design. To address shorter time-to-market windows, Talus is the first implementation solution to multi-process the entire IC design flow. Its front-end design system provides logic designers with a fast, high-capacity, physically aware synthesis capability.
Its physical design system addresses variability and multimode/multicorner complexity with new optimization, place and route, and clock tree synthesis technology. To reduce leakage and dynamic power, Talus also provides a complete low-power design system. To improve manufacturability and reliability, Talus provides built-in design-for-manufacturing (DFM) features such as redundant via insertion, recommended end-of-line extension, and wire spreading & widening.
LG selects Cypress' CapSense for LCD monitors
SAN JOSE, USA: Cypress Semiconductor Corp. today announced that LG Electronics has selected its CapSense touch-sensing solution to implement the stylish user interface in the new W53 and W54 LCD monitors.
Using CapSense proximity-sensing, the monitors feature a clean, black bezel with control buttons that only illuminate when a user’s finger approaches. LG designers leveraged the flexibility of the PSoC programmable SoC architecture to implement LED animation control, I2C sensitivity control and other functions beyond touch sensing - a capability called CapSense Plus -- in the W53, W54 and other LCD monitors, as well as in the Scarlet II LCD TV line.
Cypress is the industry touch-sensing leader, with over 3 billion mechanical buttons replaced in mobile handsets, laptops, consumer electronics, white goods, automotive applications and more. LG has selected the CapSense solution for mobile handsets, air cleaners and other products in addition to LCD monitors and televisions.
LG’s W53 and W54 SMART Monitor Series offer top picture quality while greatly reducing eyestrain during extended use. These monitors include an Auto Brightness feature that allows them to automatically optimize their brightness and other picture settings based on the ambient light in the room and the content being viewed. The W53 and W54 monitors are available in sizes from 18.5 to 27 inches.
“CapSense enables compelling touch-sensing interfaces, and the integration of proximity sensing contributes to the unique design of our LCD Monitors,” said JunHo Shin, engineer for Business Solutions R&D at LG. “Equally as important, CapSense delivers well-established quality from the industry leader in touch-sensing technology.”
“Winning an initial design with a leading provider of elegant consumer electronics such as LG points to the innovative touch-sensing interfaces the CapSense solution enables,” said Dhwani Vyas, vice president of the User Interface Business Unit at Cypress. “Having LG select CapSense across multiple product lines is excellent validation of its flexibility, ease-of-use and reliability.”
Using CapSense proximity-sensing, the monitors feature a clean, black bezel with control buttons that only illuminate when a user’s finger approaches. LG designers leveraged the flexibility of the PSoC programmable SoC architecture to implement LED animation control, I2C sensitivity control and other functions beyond touch sensing - a capability called CapSense Plus -- in the W53, W54 and other LCD monitors, as well as in the Scarlet II LCD TV line.Cypress is the industry touch-sensing leader, with over 3 billion mechanical buttons replaced in mobile handsets, laptops, consumer electronics, white goods, automotive applications and more. LG has selected the CapSense solution for mobile handsets, air cleaners and other products in addition to LCD monitors and televisions.
LG’s W53 and W54 SMART Monitor Series offer top picture quality while greatly reducing eyestrain during extended use. These monitors include an Auto Brightness feature that allows them to automatically optimize their brightness and other picture settings based on the ambient light in the room and the content being viewed. The W53 and W54 monitors are available in sizes from 18.5 to 27 inches.
“CapSense enables compelling touch-sensing interfaces, and the integration of proximity sensing contributes to the unique design of our LCD Monitors,” said JunHo Shin, engineer for Business Solutions R&D at LG. “Equally as important, CapSense delivers well-established quality from the industry leader in touch-sensing technology.”
“Winning an initial design with a leading provider of elegant consumer electronics such as LG points to the innovative touch-sensing interfaces the CapSense solution enables,” said Dhwani Vyas, vice president of the User Interface Business Unit at Cypress. “Having LG select CapSense across multiple product lines is excellent validation of its flexibility, ease-of-use and reliability.”
MEMS inertial sensors market: Business potential and key challenges
LYON, FRANCE: Yole Développement has released its new report dedicated to MEMS accelerometers, gyroscopes and IMU Market from 2008 to 2013. The French consulting company has presented its marketing and technological analysis on MEMS inertial market with a strong focus on the consumer market.
How is the consumer electronics changing the MEMS motion sensor industry? Does the Automotive market affect the MEMS Inertial suppliers? Yole updated its figures, marketing and technological trends. And for the second time, the market analysts are giving today its expertise on the market, which is the one of the most important in the MEMS industry.
Motion sensing devices are not new. They have been used since the 50s in aerospace and defense fields for navigation functions. MEMS versions of accelerometers and gyroscopes have only been developed more recently, bringing two key advantages: cost and size reduction.
While not as accurate as the devices used for military applications, MEMS‐type accelerometers and gyroscopes are well adapted to be integrated into cars and many consumer electronic products. MEMS accelerometers have been extensively used since the 90s in light vehicle airbags, as crash sensors.
Since then many other devices have benefited from the use of motion sensors. The latest and most striking examples are their use in Nintendo Wii game controllers and in Apple iPhone and iPod devices.
Source: Yole Développement
MEMS accelerometers and gyroscopes: already a 1.80B$ market in 2008
MEMS inertial sensors now represent a serious business: “752M units of MEMS accelerometers and gyroscopes were produced worldwide in 2008, corresponding to a 1.80B$ market already”, says Laurent Robin, MEMS Market Analyst at Yole. “The major part of this market still comes from automotive applications; however consumer applications should overtake this by 2011”, explains Laurent.
This is not only due to the current downturn which is impacting the automotive world: massive use of accelerometer and gyroscope is likely to stay limited to current established applications such as airbag, ESC and TPMS.
The annual growth rate will be limited to 3.6 percent up to 2013, compared to 21.1 percent for the consumer area. Indeed, the adoption rate of motion sensors on many consumer electronics products is rising faster than ever.
For example, Bosch (including its Sensortec division) and ST Microelectronics are leading the global MEMS accelerometer market with about 35 percent of market share together. Indeed, STM has recently benefited from key contracts such as the one with Apple. Its main challengers are ADI, Freescale, VTI and Infineon, and new players continue to enter the market.
From the gyroscope side, three players dominated the market in 2008: Bosch, Systron Donner and Panasonic had, on average, 20 percent market share each. However the automotive part of Systron Donner shut down in the beginning of 2009, which is greatly impacting the automotive electronics field.
Cost and intelligence are driving development of future product generations
Successful MEMS providers will be the ones able to deal with this changing economic landscape.
Some devices now integrate MEMS sensors as a commodity product. In other cases, integration of MEMS is driven by regulation and the user is not willing to pay a price premium for additional sensors. Pressure on cost is thus enormous in the last two cases. Successful players are the ones able to decrease manufacturing costs.
One strategy is to produce on 8” infrastructure. This has been chosen by several players: ST Microelectronics, Bosch Sensortec (Fab is ready, but not in use yet), Freescale, TSMC (foundry service).
Other players have moved to a technology renowned to be more able to handle cost reduction. A nice example is Panasonic which has successfully moved its gyroscope production from quartz to silicon substrates.
When it comes to very high volumes, big IC players are often preferred. Besides been able to sustain high price pressure, they are used to delivering very reliable products, to managing efficiently the supply chain and to ramping up production easily.
Being able to add intelligence to the sensor is also a means to offer strong product differentiators. From supplying only a component, many players are now supplying a solution. Algorithms are commonly integrated at the chip level: for screen rotation, drop detection… This is why a company such as Kionix has been successful in the HDD protection market: notebook free‐fall scenarios have been successfully implemented.
Providing software and system development around the sensor is also essential. It is thus not surprising that in many companies today, more people are working on the software side than on the process side!
MEMS Inertial Sensors Market 2009 Report will be available in June 2009, The catalog price: EURO 3,990 (single user license).
How is the consumer electronics changing the MEMS motion sensor industry? Does the Automotive market affect the MEMS Inertial suppliers? Yole updated its figures, marketing and technological trends. And for the second time, the market analysts are giving today its expertise on the market, which is the one of the most important in the MEMS industry.
Motion sensing devices are not new. They have been used since the 50s in aerospace and defense fields for navigation functions. MEMS versions of accelerometers and gyroscopes have only been developed more recently, bringing two key advantages: cost and size reduction.
While not as accurate as the devices used for military applications, MEMS‐type accelerometers and gyroscopes are well adapted to be integrated into cars and many consumer electronic products. MEMS accelerometers have been extensively used since the 90s in light vehicle airbags, as crash sensors.
Since then many other devices have benefited from the use of motion sensors. The latest and most striking examples are their use in Nintendo Wii game controllers and in Apple iPhone and iPod devices.
Source: Yole DéveloppementMEMS accelerometers and gyroscopes: already a 1.80B$ market in 2008
MEMS inertial sensors now represent a serious business: “752M units of MEMS accelerometers and gyroscopes were produced worldwide in 2008, corresponding to a 1.80B$ market already”, says Laurent Robin, MEMS Market Analyst at Yole. “The major part of this market still comes from automotive applications; however consumer applications should overtake this by 2011”, explains Laurent.
This is not only due to the current downturn which is impacting the automotive world: massive use of accelerometer and gyroscope is likely to stay limited to current established applications such as airbag, ESC and TPMS.
The annual growth rate will be limited to 3.6 percent up to 2013, compared to 21.1 percent for the consumer area. Indeed, the adoption rate of motion sensors on many consumer electronics products is rising faster than ever.
For example, Bosch (including its Sensortec division) and ST Microelectronics are leading the global MEMS accelerometer market with about 35 percent of market share together. Indeed, STM has recently benefited from key contracts such as the one with Apple. Its main challengers are ADI, Freescale, VTI and Infineon, and new players continue to enter the market.
From the gyroscope side, three players dominated the market in 2008: Bosch, Systron Donner and Panasonic had, on average, 20 percent market share each. However the automotive part of Systron Donner shut down in the beginning of 2009, which is greatly impacting the automotive electronics field.
Cost and intelligence are driving development of future product generations
Successful MEMS providers will be the ones able to deal with this changing economic landscape.
Some devices now integrate MEMS sensors as a commodity product. In other cases, integration of MEMS is driven by regulation and the user is not willing to pay a price premium for additional sensors. Pressure on cost is thus enormous in the last two cases. Successful players are the ones able to decrease manufacturing costs.
One strategy is to produce on 8” infrastructure. This has been chosen by several players: ST Microelectronics, Bosch Sensortec (Fab is ready, but not in use yet), Freescale, TSMC (foundry service).
Other players have moved to a technology renowned to be more able to handle cost reduction. A nice example is Panasonic which has successfully moved its gyroscope production from quartz to silicon substrates.
When it comes to very high volumes, big IC players are often preferred. Besides been able to sustain high price pressure, they are used to delivering very reliable products, to managing efficiently the supply chain and to ramping up production easily.
Being able to add intelligence to the sensor is also a means to offer strong product differentiators. From supplying only a component, many players are now supplying a solution. Algorithms are commonly integrated at the chip level: for screen rotation, drop detection… This is why a company such as Kionix has been successful in the HDD protection market: notebook free‐fall scenarios have been successfully implemented.
Providing software and system development around the sensor is also essential. It is thus not surprising that in many companies today, more people are working on the software side than on the process side!
MEMS Inertial Sensors Market 2009 Report will be available in June 2009, The catalog price: EURO 3,990 (single user license).
Investment in Taiwan will help fix Mainland China's broken IC industry
NEW TRIPOLI, USA: Mainland China’s cross-straits investment in Taiwan will help the island country to survive the global crisis and at the same time help fix its own IC market, according to the report “Mainland China’s Semiconductor and Equipment Markets,” recently published by The Information Network.
“China’s chip industry is broken, a combination of the recession and too little money being spent by the government. Only $7 billion was spent on fabs in the past five years, enough to build only two 300mm fabs,” says Dr. Robert Castellano, President of The Information Network. “Investments by China into Taiwan will not only enable the country to endure its deepest recession, which was down 10.24% last quarter, but will catalyze a change in the Taiwanese government’s attitude toward semiconductor technology transfer.”
For years, rigid regulations controlled technology and monetary outflows from Taiwanese chip makers to China. Several factors played a role, such as concerns about China stealing and copying IP, fear that the technology would strengthen China’s military capabilities, and loss of jobs.
“Macroeconomic forces have changed the landscape. Taiwan needs money, and although the government may be reticent to give up its advanced technology, China’s massive economic stimulus package to Taiwan will serve to lessen regulations,” added Dr. Castellano. “This move will strengthen China’s semiconductor companies, minimizing the need to import the vast number of chips it currently does to manufacture consumer electronic products.”
China's IC industry is expanding rapidly. In 2008 Mainland China produced 42.5 billion ICs, which accounted for 24.3 percent of domestic demand as a result of massive building programs and the weak economy. In comparison, Mainland China produced only 20.9 percent five years ago.
However, in 2008, consumption of ICs in Mainland China is outpaced production in domestically made ICs. Consumption grew 6.8 percent to 174.7 billion chips while production decreased 0.4 percent to 42.5 billion chips.
These issues are resulting in consolidation as the mainly foundry-based Chinese industry (SMIC, Grace, HeJian, ASMC, and CR Micro) competes with TSMC, UMC, and other entrenched Asian foundries. Hua Hong NEC Electronics will soon acquire Grace Semiconductor.
Things are also changing internally in China. As much as $25 billion is earmarked over the next five years to prop up the industry, including $5 billion for the joint venture between Elpida and Suzhou Venture Group and $5 billion for Sino-chip.
“Areas propelling the Chinese IC industry are part of the government stimulus program such as projects to supply subsidized electronic goods to rural areas of China. The construction of 3G networks, the expansion of mobile TV operations are big areas of opportunity,” added Dr. Castellano. “The Chinese government has realized internal stimulus was not enough without the advanced technology needed from Taiwan to make these programs successful.”
“China’s chip industry is broken, a combination of the recession and too little money being spent by the government. Only $7 billion was spent on fabs in the past five years, enough to build only two 300mm fabs,” says Dr. Robert Castellano, President of The Information Network. “Investments by China into Taiwan will not only enable the country to endure its deepest recession, which was down 10.24% last quarter, but will catalyze a change in the Taiwanese government’s attitude toward semiconductor technology transfer.”
For years, rigid regulations controlled technology and monetary outflows from Taiwanese chip makers to China. Several factors played a role, such as concerns about China stealing and copying IP, fear that the technology would strengthen China’s military capabilities, and loss of jobs.
“Macroeconomic forces have changed the landscape. Taiwan needs money, and although the government may be reticent to give up its advanced technology, China’s massive economic stimulus package to Taiwan will serve to lessen regulations,” added Dr. Castellano. “This move will strengthen China’s semiconductor companies, minimizing the need to import the vast number of chips it currently does to manufacture consumer electronic products.”
China's IC industry is expanding rapidly. In 2008 Mainland China produced 42.5 billion ICs, which accounted for 24.3 percent of domestic demand as a result of massive building programs and the weak economy. In comparison, Mainland China produced only 20.9 percent five years ago.
However, in 2008, consumption of ICs in Mainland China is outpaced production in domestically made ICs. Consumption grew 6.8 percent to 174.7 billion chips while production decreased 0.4 percent to 42.5 billion chips.These issues are resulting in consolidation as the mainly foundry-based Chinese industry (SMIC, Grace, HeJian, ASMC, and CR Micro) competes with TSMC, UMC, and other entrenched Asian foundries. Hua Hong NEC Electronics will soon acquire Grace Semiconductor.
Things are also changing internally in China. As much as $25 billion is earmarked over the next five years to prop up the industry, including $5 billion for the joint venture between Elpida and Suzhou Venture Group and $5 billion for Sino-chip.
“Areas propelling the Chinese IC industry are part of the government stimulus program such as projects to supply subsidized electronic goods to rural areas of China. The construction of 3G networks, the expansion of mobile TV operations are big areas of opportunity,” added Dr. Castellano. “The Chinese government has realized internal stimulus was not enough without the advanced technology needed from Taiwan to make these programs successful.”
Novellus HCM IONX XL Ta(N) barrier technology enables 3X/2Xnm memory transition to copper
SAN JOSE: Ten years after the introduction of copper metallization for logic device manufacturing, Physical Vapor Deposition (PVD) copper barrier-seed and copper electrochemical deposition (ECD) are now being used for the production of DRAM and Flash memory chips. The memory transition from aluminum metallization to copper interconnects is being driven by the technological challenges associated with device scaling and the need to reduce memory chip manufacturing cost.
One of the key components of a copper memory interconnect is the PVD tantalum nitride (Ta(N)) barrier layer that provides the necessary copper diffusion resistance, as well as wettability for the subsequent copper seed layer. For memory manufacturers, the challenge comes with depositing this barrier film in advanced device structures that can possess up to 30 percent smaller critical dimensions (CD) than those found in logic applications.
For these aggressive geometries, planar PVD is limited by shadowing effects that can cause incomplete film coverage due to overhang at the top corner of the trench or via, in turn leading to inadequate copper fill and yield loss. Some planar PVD barrier solutions are investigating the incorporation of more expensive CVD layers to mitigate these effects. Compounding these challenges is the fact that Ta(N) barriers also need to be very thin (less than 120Å in the field) in order to minimize the volume fraction of high resistivity Ta(N) relative to low resistivity copper within the feature.
To address the challenges discussed above, Novellus has developed the IONX XL (eXtended Life) Ta(N) barrier process for the 3x/2xnm memory node, based on Novellus' PVD Hollow Cathode Magnetron (HCM) deposition technology. This PVD-only barrier process deposits high quality films with excellent step coverage for high aspect ratio memory structures.
The conformal Ta(N) films deposited with this technology are the result of an increased plasma density and more effective control of the ionized flux that reaches the wafer surface. A thin, highly conformal IONX XL Ta(N) barrier layer is deposited into a 3xnm memory device trench with no top corner overhang.
Not only does this robust copper barrier process meet the technical challenges of advanced memory, but it also results in a 40 percent reduction in the tantalum Cost of Consumables (CoC) compared to competitive market offerings. A 100,000 wafer-starts-per-month memory megafab using two levels of metal can save approximately $1M a year in consumable costs through more efficient utilization of the tantalum target material.
"As memory technology transitions to copper interconnects, the 3x/2xnm device dimensions are placing stringent technical and cost requirements on the Ta(N) barrier layer," said Dr. Wai-Fan Yau, general manager for Novellus' Integrated Metals Business Unit. "The new IONX XL barrier film meets these advanced technical demands and also provides a significant reduction in consumable costs."
One of the key components of a copper memory interconnect is the PVD tantalum nitride (Ta(N)) barrier layer that provides the necessary copper diffusion resistance, as well as wettability for the subsequent copper seed layer. For memory manufacturers, the challenge comes with depositing this barrier film in advanced device structures that can possess up to 30 percent smaller critical dimensions (CD) than those found in logic applications.
For these aggressive geometries, planar PVD is limited by shadowing effects that can cause incomplete film coverage due to overhang at the top corner of the trench or via, in turn leading to inadequate copper fill and yield loss. Some planar PVD barrier solutions are investigating the incorporation of more expensive CVD layers to mitigate these effects. Compounding these challenges is the fact that Ta(N) barriers also need to be very thin (less than 120Å in the field) in order to minimize the volume fraction of high resistivity Ta(N) relative to low resistivity copper within the feature.
To address the challenges discussed above, Novellus has developed the IONX XL (eXtended Life) Ta(N) barrier process for the 3x/2xnm memory node, based on Novellus' PVD Hollow Cathode Magnetron (HCM) deposition technology. This PVD-only barrier process deposits high quality films with excellent step coverage for high aspect ratio memory structures.
The conformal Ta(N) films deposited with this technology are the result of an increased plasma density and more effective control of the ionized flux that reaches the wafer surface. A thin, highly conformal IONX XL Ta(N) barrier layer is deposited into a 3xnm memory device trench with no top corner overhang.
Not only does this robust copper barrier process meet the technical challenges of advanced memory, but it also results in a 40 percent reduction in the tantalum Cost of Consumables (CoC) compared to competitive market offerings. A 100,000 wafer-starts-per-month memory megafab using two levels of metal can save approximately $1M a year in consumable costs through more efficient utilization of the tantalum target material.
"As memory technology transitions to copper interconnects, the 3x/2xnm device dimensions are placing stringent technical and cost requirements on the Ta(N) barrier layer," said Dr. Wai-Fan Yau, general manager for Novellus' Integrated Metals Business Unit. "The new IONX XL barrier film meets these advanced technical demands and also provides a significant reduction in consumable costs."
Global semicon revenue to decline 22 percent in 2009
STAMFORD, USA: Worldwide semiconductor revenue is forecast to reach $198 billion in 2009, a 22.4 percent decline from 2008 revenue of $255 billion, according to the latest projections by Gartner Inc.
This outlook is slightly better than the first quarter projections, when Gartner forecast semiconductor revenue to decline 24.1 percent in 2009.
"First quarter PC shipments came in better than expected, which led to an improved outlook for microprocessors, but we believe most of this improvement was due to the fact that inventories had been run down too far, rather than true demand returning," said Bryan Lewis, research vice president at Gartner.
"We are expecting 4.9 percent growth in second quarter semiconductor sales based on recent semiconductor company guidance, and this positive movement has caused us to move away from our 1Q09 worst-case scenario of a record down year in 2009. While this is positive news, the semiconductor industry is clearly not out of the woods, as there is minimal evidence that demand is returning, except in China," Lewis said.
Inventory burn in the PC market in the fourth quarter of 2008 and in January and February 2009 pushed component demand significantly below PC demand, driving down prices across the board.
Gartner analysts said PC vendors that started cutting inventory early were able to achieve significant savings on bill of materials. As the inventory correction swings in the opposite direction, Gartner expects component prices to stabilize through the year.
Application-specific standard product (ASSP) will continue to lead semiconductor revenue, as it is forecast to total $51.9 billion in 2009, a 24.2 percent decline from 2008. The memory market will be the No. 2 segment for the semiconductor industry, as it totals $39.4 billion, a 16.8 percent decline from 2008.
The microcomponents segment (microprocessors, micro controller units, digital signal processors) will drop from the No. 2 spot in 2008 to the No. 3 spot in 2009. Microcomponents are projected to reach $37.3 billion, a 23.6 percent decline from 2008.
"Consumer spending will remain somewhat depressed due to high unemployment, low housing pricing, and relatively low consumer confidence," Lewis said. "IT budgets are modestly down in 2009, but companies are not spending at the rate of their budgets."
Gartner has removed solar revenue from its semiconductor forecast because solar cells are not traditional semiconductor devices (solar cells focus on energy generation and are not components in an electronic system), and their high growth rates were distorting the true growth of the semiconductor industry. Gartner is expanding its coverage in solar and will provide detailed technology forecast breakouts in separate reports.
This outlook is slightly better than the first quarter projections, when Gartner forecast semiconductor revenue to decline 24.1 percent in 2009.
"First quarter PC shipments came in better than expected, which led to an improved outlook for microprocessors, but we believe most of this improvement was due to the fact that inventories had been run down too far, rather than true demand returning," said Bryan Lewis, research vice president at Gartner.
"We are expecting 4.9 percent growth in second quarter semiconductor sales based on recent semiconductor company guidance, and this positive movement has caused us to move away from our 1Q09 worst-case scenario of a record down year in 2009. While this is positive news, the semiconductor industry is clearly not out of the woods, as there is minimal evidence that demand is returning, except in China," Lewis said.
Inventory burn in the PC market in the fourth quarter of 2008 and in January and February 2009 pushed component demand significantly below PC demand, driving down prices across the board.
Gartner analysts said PC vendors that started cutting inventory early were able to achieve significant savings on bill of materials. As the inventory correction swings in the opposite direction, Gartner expects component prices to stabilize through the year.
Application-specific standard product (ASSP) will continue to lead semiconductor revenue, as it is forecast to total $51.9 billion in 2009, a 24.2 percent decline from 2008. The memory market will be the No. 2 segment for the semiconductor industry, as it totals $39.4 billion, a 16.8 percent decline from 2008.
The microcomponents segment (microprocessors, micro controller units, digital signal processors) will drop from the No. 2 spot in 2008 to the No. 3 spot in 2009. Microcomponents are projected to reach $37.3 billion, a 23.6 percent decline from 2008.
"Consumer spending will remain somewhat depressed due to high unemployment, low housing pricing, and relatively low consumer confidence," Lewis said. "IT budgets are modestly down in 2009, but companies are not spending at the rate of their budgets."
Gartner has removed solar revenue from its semiconductor forecast because solar cells are not traditional semiconductor devices (solar cells focus on energy generation and are not components in an electronic system), and their high growth rates were distorting the true growth of the semiconductor industry. Gartner is expanding its coverage in solar and will provide detailed technology forecast breakouts in separate reports.
2H May mainstream NAND Flash MLC average contract price slightly declined 2-6pc
TAIPEI, TAIWAN: NAND Flash contract price remains flat in 2H May. Some mainstream MLC average contract price has slightly declined 2 percent to 6 percent due to the high density products promotion by some vendors in Mid-May,says DRAMeXchange.
Fig.1: 32Gb MLC NAND Flash Contract Price trend
With the coming quarter end, some vendors already initiated the promotion programs to lower their inventory level. High density NAND Flash MLC chips under new process technology have comparably favor discount than those low density chips under more mature process technology.
Therefore, the decline degree of the contract price “Low” for 32Gb MLC NAND Flash is larger than other NAND Flash chips in 2HMay. Meanwhile, some vendors keep making effort on the contract price stabilization to improve profitability since they still treat system maker customers as the shipment priority and result in the flat contract price “High” of 32Gb MLC NAND Flash in 2HMay.According to DRAMeXchange.
As for the demand side, DRAMeXchange states that May and June are perceived as the slow seasons for NAND Flash end products such as memory card and UFD. Some downstream clients are expecting for lower chip price for the sake of promotion in summer break.
Fig. 2: 32Gb MLC NAND Flash Spot Price trend
However, the 2Q09 profitability has turned to the first priority of the suppliers and stable chip price in June is the clearly intension. The mindset difference toward future price between buyers and suppliers has resulted in the recent fluctuation and consolidation in spot market.
The June contract price is likely to remain flat or might slightly soften due to the tug-of-war status between both sides.
Fig.1: 32Gb MLC NAND Flash Contract Price trend
With the coming quarter end, some vendors already initiated the promotion programs to lower their inventory level. High density NAND Flash MLC chips under new process technology have comparably favor discount than those low density chips under more mature process technology.Therefore, the decline degree of the contract price “Low” for 32Gb MLC NAND Flash is larger than other NAND Flash chips in 2HMay. Meanwhile, some vendors keep making effort on the contract price stabilization to improve profitability since they still treat system maker customers as the shipment priority and result in the flat contract price “High” of 32Gb MLC NAND Flash in 2HMay.According to DRAMeXchange.
As for the demand side, DRAMeXchange states that May and June are perceived as the slow seasons for NAND Flash end products such as memory card and UFD. Some downstream clients are expecting for lower chip price for the sake of promotion in summer break.
Fig. 2: 32Gb MLC NAND Flash Spot Price trend
However, the 2Q09 profitability has turned to the first priority of the suppliers and stable chip price in June is the clearly intension. The mindset difference toward future price between buyers and suppliers has resulted in the recent fluctuation and consolidation in spot market. The June contract price is likely to remain flat or might slightly soften due to the tug-of-war status between both sides.
Netronome licenses ARM multicore processor for next-gen network flow processors
CAMBRIDGE, UK: ARM announced that Netronome, a leading developer of highly programmable semiconductor products that provide intelligent and secure flow processing for virtualized servers and network equipment, has licensed the ARM11 MPCore multicore processor and a portfolio of ARM Physical IP for incorporation into its NFP-32xx family of Network Flow Processors.
Netronome’s network flow processors (NFPs) incorporate a high-performance, parallel processing architecture to enable wire-speed processing of complex Layer 2-7 algorithms, security processing, deep packet inspection and filtering, traffic management and forwarding applications.
By integrating capabilities that have typically required multiple specialized processors, Netronome NFPs provide a cost-effective, low power platform for a broad range of emerging applications requiring high-performance packet and content processing with robust security features, including switching and routing, network security, broadband access, test and measurement and wireless markets.
The NFP-32xx family of devices extends the performance and application reach of the family of Intel® IXP28xx products licensed by Netronome in November 2007, while preserving the software compatibility with existing IXP28xx devices.
Appropriate telecom and enterprise applications include line cards and standalone communications appliances that perform tasks such as protocol interworking, MAC emulation, Ethernet switching and IPv4/IPv6 forwarding. This is critical in enabling OEMs to deliver new line card functionality and services, while minimizing development time and cost.
In designs based on the NFP, the ARM11 MPCore processor can be used to process complex algorithms, maintain route tables, manage system level functions and perform control plane tasks.
Devices containing the ARM11 MPCore processor can be configured to contain between one and four processors delivering up to an aggregate 5000 Dhrystone MIPS of performance at 1GHz. By providing a scalable solution, the ARM11 MPCore processor enables existing software portability across single CPU and multi-CPU designs.
In addition to the ARM11 MPCore processor, Netronome incorporated ARM High Speed Interface IP in their design. ARM High Speed Interface IP delivers physical interface and analog timing solutions for a broad range of SDRAM DDR (double-data rate) applications ranging from high-speed mission critical applications to low-power memory sub-systems.
These silicon-proven solutions have been optimized for high data bandwidth, lowest power and enhanced signaling integrity features to enable support for a wide range of applications from high-end graphics, high-speed communications to low-power handheld devices.
ARM’s ability to deliver processor IP and physical IP in parallel ensures complete integration of complementary IP enabling the development of performance driven consumer devices requiring advanced functionality without increasing power consumption.
“Our analysis has shown that the use of multicore technology is the most power efficient way to scale wire-speed performance,” said Jim Finnegan, senior vice president of silicon engineering at Netronome. “Having a range of network processor solution options, with architecture compatibility across the entire family of Netronome devices enables our customers to maximize their software investment.”
“The efforts of Partners such as Netronome have helped to increase the ARM architecture’s presence in the networking market. This in turn has driven an ecosystem of optimized software and tools to enable innovative new applications,” said Ian Ferguson, director, Enterprise Solutions, ARM. “With current concerns about energy efficiency and utilization, the ability to perform wire-speed processing inside the power envelope associated with mobile platforms offers significant opportunities for OEM differentiation.”
Netronome’s network flow processors (NFPs) incorporate a high-performance, parallel processing architecture to enable wire-speed processing of complex Layer 2-7 algorithms, security processing, deep packet inspection and filtering, traffic management and forwarding applications.
By integrating capabilities that have typically required multiple specialized processors, Netronome NFPs provide a cost-effective, low power platform for a broad range of emerging applications requiring high-performance packet and content processing with robust security features, including switching and routing, network security, broadband access, test and measurement and wireless markets.
The NFP-32xx family of devices extends the performance and application reach of the family of Intel® IXP28xx products licensed by Netronome in November 2007, while preserving the software compatibility with existing IXP28xx devices.
Appropriate telecom and enterprise applications include line cards and standalone communications appliances that perform tasks such as protocol interworking, MAC emulation, Ethernet switching and IPv4/IPv6 forwarding. This is critical in enabling OEMs to deliver new line card functionality and services, while minimizing development time and cost.
In designs based on the NFP, the ARM11 MPCore processor can be used to process complex algorithms, maintain route tables, manage system level functions and perform control plane tasks.
Devices containing the ARM11 MPCore processor can be configured to contain between one and four processors delivering up to an aggregate 5000 Dhrystone MIPS of performance at 1GHz. By providing a scalable solution, the ARM11 MPCore processor enables existing software portability across single CPU and multi-CPU designs.
In addition to the ARM11 MPCore processor, Netronome incorporated ARM High Speed Interface IP in their design. ARM High Speed Interface IP delivers physical interface and analog timing solutions for a broad range of SDRAM DDR (double-data rate) applications ranging from high-speed mission critical applications to low-power memory sub-systems.
These silicon-proven solutions have been optimized for high data bandwidth, lowest power and enhanced signaling integrity features to enable support for a wide range of applications from high-end graphics, high-speed communications to low-power handheld devices.
ARM’s ability to deliver processor IP and physical IP in parallel ensures complete integration of complementary IP enabling the development of performance driven consumer devices requiring advanced functionality without increasing power consumption.
“Our analysis has shown that the use of multicore technology is the most power efficient way to scale wire-speed performance,” said Jim Finnegan, senior vice president of silicon engineering at Netronome. “Having a range of network processor solution options, with architecture compatibility across the entire family of Netronome devices enables our customers to maximize their software investment.”
“The efforts of Partners such as Netronome have helped to increase the ARM architecture’s presence in the networking market. This in turn has driven an ecosystem of optimized software and tools to enable innovative new applications,” said Ian Ferguson, director, Enterprise Solutions, ARM. “With current concerns about energy efficiency and utilization, the ability to perform wire-speed processing inside the power envelope associated with mobile platforms offers significant opportunities for OEM differentiation.”
Intel India unveils 'Sponsors of Tomorrow' Global Campaign
MUMBAI, INDIA:Sandboxes, rock stars and clean rooms mean something entirely different at Intel Corp., and a new integrated branding campaign by the leading silicon innovator will tell the world how.
Representing Intel’s biggest marketing campaign in nearly three years and the first that spotlights the promotion of the Intel brand and not a processor product, “Sponsors of Tomorrow” launched on May 27 in India. The ambitious campaign conveys the message that gigantic advances of the digital age have been made possible by silicon – the key ingredient in microprocessors -– and the vast majority of this silicon has come from Intel.
For more than 40 years Intel has been delivering tomorrow’s ‘normal’ and our new marketing campaign is a way for the world to be made aware of this fact,” said Tim Bailey, marketing director, Intel Asia Pacific. “We’re hoping to convey that we’re not just a microprocessor company, but a move-society-forward-by-quantum-leaps company. What Intel develops today leads the path towards a better tomorrow.”
Apart from TV commercials and advertisements in newspapers across the country, special glow signs will be unmasked in retail stores across Mumbai, Delhi, Bangalore, Pune, Ahmedabad, Kolkata, Chennai and Hyderabad to bring in the new campaign. The multi-million-dollar marketing campaign is the largest for Intel since “Multiply,” the September 2006 campaign that supported the then-new Intel CoreTM 2 Duo.
“Sponsors of Tomorrow” is expected to have a lifespan of three to five years, and was created by Venables Bell & Partners in San Francisco. It is the first campaign for Intel by the agency since being awarded Intel’s master brand account in January. Media planning and buying in India has been done by Omnicom Media Division (OMD).
Our research tells us consumers find the computer market space complex and want a simpler way to buy. They want to buy from a company and a brand that they trust in. The Indian consumer has an enormous amount of confidence in Intel. The technology Intel develops goes beyond just the microprocessor when, in fact, the greatest strength of the Intel brand will always be what is still to come. Keeping that in mind we launched the “Sponsors of Tomorrow” campaign,” said Prakash Bagri, marketing director, Intel South Asia.
“In India, the campaign will focus on strengthening Intel’s connection with consumers. We have also rolled out a series of new badge designs and a simple processor rating system which will help consumers make the best decision when buying a new computing device,” he added.
According to Jasmin Sohrabji, managing director, OMD India: “With two fairly distinct target audiences to address –- one in the form of a tech-savvy consumer, the other of an emerging market –- we developed a media strategy that first built an optimum reach base through conventional media. We then took key targeted platforms like digital media, cricket, tech programs and print to create high-impact innovative executions of “Sponsors of Tomorrow”. This approach allowed us to not only effectively reach both our audiences, but we also did it in a tone and manner that was relevant and engaging.”
“Sponsors of Tomorrow” includes print, online, outdoor and other advertisement placements, plus additional marketing efforts like in-store and online retail campaigns, all focused on helping consumers choose the best Intel processor that meets their needs. Global media planning was handled by OMD.
An example of a print ad in India is driven by the line, “Your superstars are a little different from our superstars.” The two-picture visual is, at left, Indian film actors and, in the photo at right, two bespectacled computer engineers are sporting white lab coats in their techy environment. But these aren’t just any engineers. As the ad copy explains, they are the designers of technologies which transform lives.
Another video, titled “Oops,” is set at a technology convention, where Intel is about to reveal a new microprocessor to a packed auditorium. As the dramatic unveiling is about to happen onstage, Intel employees and reporters struggle to find the tiny chip on the floor, and have the impossible task of finding it. The tagline: “Our big ideas are a little different from your big ideas.”
The phased launch began on May 11 in the United States, Germany and the United Kingdom. The campaign is also scheduled to be introduced in the following countries: Australia, Canada, France, Indonesia, Italy, Korea, Malaysia, Mexico, Netherlands, Poland, Russia, Spain, Sweden, Taiwan, Thailand, Turkey and Vietnam. Additional parts of Latin America and Africa are scheduled for June introductions, and Brazil and Japan are slated for August and September respectively.
Retail campaigns encompass a range of executions, from merchandising materials and in-store demos to online ads and training for retail salespeople. The essence of “Sponsors of Tomorrow” will also be incorporated into Intel’s online materials developed to assist consumers researching PC purchases. A heavy internal campaign is already underway at Intel campuses throughout the world.
For India, the message copy has been kept very clear and crisp to focus on why Intel inside in larger form factors as well as outdoors. As you go deeper inside the store, closer to the PCs, messaging becomes more direct.
New Processor Rating System
As another step towards simplifying purchase for consumers, Intel also announced a new Intel processor rating system using stars and based on features available in each processor. More stars indicate greater features and increased capabilities compared to other Intel processors.
For example, a single star for Intel Celeron based PCs denotes value and reliability. Two stars for Intel Pentium based PCs stand for dependability and is proven to handle most mainstream applications. Three stars mean smart, fast and energy-efficient technology for PCs that are powered by some of the mainstream Intel Core 2 Duo processors.
Four stars mean advanced processor intelligence, premium technologies and speed to do more for PCs based on the high-end Intel Core 2 Duo processors. Five stars denote the ultimate processor intelligence and breakthrough technologies to maximize computing speed and possibilities for PCs based on the top-range Intel processors such as the Intel Core i7 processors.
OEMs across the world have started following this system to give consumers a quick overview of the processor's most important user benefits.
New ‘Intel Inside’ logo design
The “Intel Inside” logos which are integral to any PC’s list of features have been given a makeover aimed at reinforcing Intel's image as a premium brand. The new stickers have been rolling out to OEMs and channel partners since the beginning of April and are seen on new computers in showrooms and retail outlets around the world.
The most imaginative new element is in the upper right corner, where the badge is "peeled" back to reveal a bit of glittering etched gold substrate that looks like it could have come right off a processor die.
The stickers are now horizontally-oriented (replacing the old vertical badge topped with the rounded Intel logo) with the Intel logo remaining on top. Underneath the product brand there's room for additional modifiers, like "Extreme" or "Quad." Overall the color scheme is much richer, with more gradients and shading.
Representing Intel’s biggest marketing campaign in nearly three years and the first that spotlights the promotion of the Intel brand and not a processor product, “Sponsors of Tomorrow” launched on May 27 in India. The ambitious campaign conveys the message that gigantic advances of the digital age have been made possible by silicon – the key ingredient in microprocessors -– and the vast majority of this silicon has come from Intel.
For more than 40 years Intel has been delivering tomorrow’s ‘normal’ and our new marketing campaign is a way for the world to be made aware of this fact,” said Tim Bailey, marketing director, Intel Asia Pacific. “We’re hoping to convey that we’re not just a microprocessor company, but a move-society-forward-by-quantum-leaps company. What Intel develops today leads the path towards a better tomorrow.”
Apart from TV commercials and advertisements in newspapers across the country, special glow signs will be unmasked in retail stores across Mumbai, Delhi, Bangalore, Pune, Ahmedabad, Kolkata, Chennai and Hyderabad to bring in the new campaign. The multi-million-dollar marketing campaign is the largest for Intel since “Multiply,” the September 2006 campaign that supported the then-new Intel CoreTM 2 Duo.
“Sponsors of Tomorrow” is expected to have a lifespan of three to five years, and was created by Venables Bell & Partners in San Francisco. It is the first campaign for Intel by the agency since being awarded Intel’s master brand account in January. Media planning and buying in India has been done by Omnicom Media Division (OMD).
Our research tells us consumers find the computer market space complex and want a simpler way to buy. They want to buy from a company and a brand that they trust in. The Indian consumer has an enormous amount of confidence in Intel. The technology Intel develops goes beyond just the microprocessor when, in fact, the greatest strength of the Intel brand will always be what is still to come. Keeping that in mind we launched the “Sponsors of Tomorrow” campaign,” said Prakash Bagri, marketing director, Intel South Asia.
“In India, the campaign will focus on strengthening Intel’s connection with consumers. We have also rolled out a series of new badge designs and a simple processor rating system which will help consumers make the best decision when buying a new computing device,” he added.
According to Jasmin Sohrabji, managing director, OMD India: “With two fairly distinct target audiences to address –- one in the form of a tech-savvy consumer, the other of an emerging market –- we developed a media strategy that first built an optimum reach base through conventional media. We then took key targeted platforms like digital media, cricket, tech programs and print to create high-impact innovative executions of “Sponsors of Tomorrow”. This approach allowed us to not only effectively reach both our audiences, but we also did it in a tone and manner that was relevant and engaging.”
“Sponsors of Tomorrow” includes print, online, outdoor and other advertisement placements, plus additional marketing efforts like in-store and online retail campaigns, all focused on helping consumers choose the best Intel processor that meets their needs. Global media planning was handled by OMD.
An example of a print ad in India is driven by the line, “Your superstars are a little different from our superstars.” The two-picture visual is, at left, Indian film actors and, in the photo at right, two bespectacled computer engineers are sporting white lab coats in their techy environment. But these aren’t just any engineers. As the ad copy explains, they are the designers of technologies which transform lives.
Another video, titled “Oops,” is set at a technology convention, where Intel is about to reveal a new microprocessor to a packed auditorium. As the dramatic unveiling is about to happen onstage, Intel employees and reporters struggle to find the tiny chip on the floor, and have the impossible task of finding it. The tagline: “Our big ideas are a little different from your big ideas.”
The phased launch began on May 11 in the United States, Germany and the United Kingdom. The campaign is also scheduled to be introduced in the following countries: Australia, Canada, France, Indonesia, Italy, Korea, Malaysia, Mexico, Netherlands, Poland, Russia, Spain, Sweden, Taiwan, Thailand, Turkey and Vietnam. Additional parts of Latin America and Africa are scheduled for June introductions, and Brazil and Japan are slated for August and September respectively.
Retail campaigns encompass a range of executions, from merchandising materials and in-store demos to online ads and training for retail salespeople. The essence of “Sponsors of Tomorrow” will also be incorporated into Intel’s online materials developed to assist consumers researching PC purchases. A heavy internal campaign is already underway at Intel campuses throughout the world.
For India, the message copy has been kept very clear and crisp to focus on why Intel inside in larger form factors as well as outdoors. As you go deeper inside the store, closer to the PCs, messaging becomes more direct.
New Processor Rating System
As another step towards simplifying purchase for consumers, Intel also announced a new Intel processor rating system using stars and based on features available in each processor. More stars indicate greater features and increased capabilities compared to other Intel processors.
For example, a single star for Intel Celeron based PCs denotes value and reliability. Two stars for Intel Pentium based PCs stand for dependability and is proven to handle most mainstream applications. Three stars mean smart, fast and energy-efficient technology for PCs that are powered by some of the mainstream Intel Core 2 Duo processors.
Four stars mean advanced processor intelligence, premium technologies and speed to do more for PCs based on the high-end Intel Core 2 Duo processors. Five stars denote the ultimate processor intelligence and breakthrough technologies to maximize computing speed and possibilities for PCs based on the top-range Intel processors such as the Intel Core i7 processors.
OEMs across the world have started following this system to give consumers a quick overview of the processor's most important user benefits.
New ‘Intel Inside’ logo design
The “Intel Inside” logos which are integral to any PC’s list of features have been given a makeover aimed at reinforcing Intel's image as a premium brand. The new stickers have been rolling out to OEMs and channel partners since the beginning of April and are seen on new computers in showrooms and retail outlets around the world.
The most imaginative new element is in the upper right corner, where the badge is "peeled" back to reveal a bit of glittering etched gold substrate that looks like it could have come right off a processor die.
The stickers are now horizontally-oriented (replacing the old vertical badge topped with the rounded Intel logo) with the Intel logo remaining on top. Underneath the product brand there's room for additional modifiers, like "Extreme" or "Quad." Overall the color scheme is much richer, with more gradients and shading.
Thursday, May 28, 2009
Magma's Talus 1.1 RTL-to-GDSII chip implementation system
BANGALORE, INDIA: Magma Design Automation Inc., a provider of chip design software, today announced the release of Talus 1.1, a new RTL-to-GDSII chip implementation system that delivers the fastest timing closure on the largest and most complex semiconductor designs.
Talus 1.1 utilizes the new Talus COre technology, which leverages Magma’s unified data model to perform timing optimization concurrently during routing, thus providing faster overall design closure with better performance and predictability.
This greatly enhances designers’ ability to achieve optimal results across a wide variety of designs -– while minimizing the need for user intervention. Unlike existing routing systems that perform optimization sequentially before and after place and route, and which focus only on layout-oriented routing factors such as design for manufacturability (DFM) or design rule checking (DRC), Talus focuses concurrently on timing and layout-driven metrics during routing.
In addition to its ability to provide the fastest turnaround on large designs, Talus 1.1 introduces the Talus Flow Manager with “out-of-the-box” design flows. Included with the release are out-of-the-box reference flows for RTL-to-GDSII, multi-Vdd, low-power design and high-performance design -– engineers can easily tune the reference flows for specific applications. Talus Flow Manager also introduces a new visual analysis environment, Talus Visual Volcano, that integrates and presents all design and analysis data via a common display.
“For engineers creating ICs at advanced geometries, big chips, or chips where power management is important, Talus is superior to design systems from other EDA vendors,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.
“The first breakthrough at Magma occurred when we added concurrent optimization to placement in our initial product, Blast Fusion. Our new Talus Core technology raises the bar by adding concurrent optimization to routing, resulting in faster design closure and better timing performance. Unlike other approaches, Talus delivers a level of design speed and efficiency that is ideal for small-geometry designs -– this also makes it ideal for designers creating big chips, those with 5 million gates or more. This will take on greater commercial significance for our customers as an increased portion of their designs target applications such as netbooks, smartphones and embedded devices that require bigger and more complex chips but also must be designed for low power.”
Talus 1.1 was created to deliver optimal quality of results out of the box at advanced process nodes. It has already been used to tape out numerous production chips at 40 nm, and is presently ready for designs at 32 nm and 28 nm. Such technology is commonly found in System-on-a-Chip (SoC) designs, which integrate computing capabilities on a single chip.
Talus COre technology
The heart of the improvements in Talus 1.1 is its Concurrent Optimizing Routing Engine (COre) technology. At advanced geometries, complex resistance effects, increased via resistance and crosstalk can create a large timing disconnect between placed gates and final routing. Dealing with optimization and routing sequentially results in a suboptimal solution with unpredictable results.
Traditional solutions must spend time optimizing the design after routing to get the necessary accuracy, but at the cost of long runtimes. Talus COre focuses on applying the full scope of timing optimization incrementally during routing. Every aspect of the routing algorithms -– from topology generation to layer assignment, track assignment and DRC cleanup -– is timing and crosstalk aware. This allows the design to converge faster and eliminate post-route timing surprises.
Talus COre is coupled with Talus’ SDF-based optimization to remove the need for manual engineering change orders (ECOs) to close timing.
The addition of the Talus COre technology allows Talus 1.1 to deliver optimal quality of results out of the box on advanced process node design challenges. It has already been used to complete production designs where it provided a better than 5 times runtime improvement over competitive solutions and previous Talus versions. In customer beta testing on 40-nm designs ranging from 2 million to 4 million gates, with frequencies from 400 MHz to 800 MHz, Talus 1.1 produced 75 percent better timing with 10 percent fewer vias than the competitive results.
Talus Flow Manager and Visual Volcano
Talus 1.1 also introduces the new Talus Flow Manager that provides an out-of-the-box Talus RTL-to-GDSII design flow tuned to deliver optimal results. Designers can easily customize the reference flow and tailor it to their own needs, developing specific flows for various projects or applications.
Additional reference flows include templates for the implementation of multiple-voltage (MVdd), multiple-mode and multiple-corner (MMMC) designs, as well as low-power and high-performance designs. Ease of use and cost of adoption is dramatically improved through the use of these pre-qualified flows.
The Talus Flow Manager includes the new Talus Visual Volcano, a new technology designed to help designers make better decisions faster. The Talus Visual Volcano analysis environment offers an integrated information display that allows an engineer to quickly track many parameters of the design, including run times, timing, power and area.
MMMC design management is made easier by simplifying the control over active versus reported scenarios, and displaying results for all scenarios concurrently. By consolidating this data into charts and graphs, the Talus Visual Volcano saves time and improves efficiency by removing the need for tedious analysis of log files and textual reports.
Production shipments of Talus 1.1 will begin in June 2009.
Talus 1.1 utilizes the new Talus COre technology, which leverages Magma’s unified data model to perform timing optimization concurrently during routing, thus providing faster overall design closure with better performance and predictability.
This greatly enhances designers’ ability to achieve optimal results across a wide variety of designs -– while minimizing the need for user intervention. Unlike existing routing systems that perform optimization sequentially before and after place and route, and which focus only on layout-oriented routing factors such as design for manufacturability (DFM) or design rule checking (DRC), Talus focuses concurrently on timing and layout-driven metrics during routing.
In addition to its ability to provide the fastest turnaround on large designs, Talus 1.1 introduces the Talus Flow Manager with “out-of-the-box” design flows. Included with the release are out-of-the-box reference flows for RTL-to-GDSII, multi-Vdd, low-power design and high-performance design -– engineers can easily tune the reference flows for specific applications. Talus Flow Manager also introduces a new visual analysis environment, Talus Visual Volcano, that integrates and presents all design and analysis data via a common display.
“For engineers creating ICs at advanced geometries, big chips, or chips where power management is important, Talus is superior to design systems from other EDA vendors,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.
“The first breakthrough at Magma occurred when we added concurrent optimization to placement in our initial product, Blast Fusion. Our new Talus Core technology raises the bar by adding concurrent optimization to routing, resulting in faster design closure and better timing performance. Unlike other approaches, Talus delivers a level of design speed and efficiency that is ideal for small-geometry designs -– this also makes it ideal for designers creating big chips, those with 5 million gates or more. This will take on greater commercial significance for our customers as an increased portion of their designs target applications such as netbooks, smartphones and embedded devices that require bigger and more complex chips but also must be designed for low power.”
Talus 1.1 was created to deliver optimal quality of results out of the box at advanced process nodes. It has already been used to tape out numerous production chips at 40 nm, and is presently ready for designs at 32 nm and 28 nm. Such technology is commonly found in System-on-a-Chip (SoC) designs, which integrate computing capabilities on a single chip.
Talus COre technology
The heart of the improvements in Talus 1.1 is its Concurrent Optimizing Routing Engine (COre) technology. At advanced geometries, complex resistance effects, increased via resistance and crosstalk can create a large timing disconnect between placed gates and final routing. Dealing with optimization and routing sequentially results in a suboptimal solution with unpredictable results.
Traditional solutions must spend time optimizing the design after routing to get the necessary accuracy, but at the cost of long runtimes. Talus COre focuses on applying the full scope of timing optimization incrementally during routing. Every aspect of the routing algorithms -– from topology generation to layer assignment, track assignment and DRC cleanup -– is timing and crosstalk aware. This allows the design to converge faster and eliminate post-route timing surprises.
Talus COre is coupled with Talus’ SDF-based optimization to remove the need for manual engineering change orders (ECOs) to close timing.
The addition of the Talus COre technology allows Talus 1.1 to deliver optimal quality of results out of the box on advanced process node design challenges. It has already been used to complete production designs where it provided a better than 5 times runtime improvement over competitive solutions and previous Talus versions. In customer beta testing on 40-nm designs ranging from 2 million to 4 million gates, with frequencies from 400 MHz to 800 MHz, Talus 1.1 produced 75 percent better timing with 10 percent fewer vias than the competitive results.
Talus Flow Manager and Visual Volcano
Talus 1.1 also introduces the new Talus Flow Manager that provides an out-of-the-box Talus RTL-to-GDSII design flow tuned to deliver optimal results. Designers can easily customize the reference flow and tailor it to their own needs, developing specific flows for various projects or applications.
Additional reference flows include templates for the implementation of multiple-voltage (MVdd), multiple-mode and multiple-corner (MMMC) designs, as well as low-power and high-performance designs. Ease of use and cost of adoption is dramatically improved through the use of these pre-qualified flows.
The Talus Flow Manager includes the new Talus Visual Volcano, a new technology designed to help designers make better decisions faster. The Talus Visual Volcano analysis environment offers an integrated information display that allows an engineer to quickly track many parameters of the design, including run times, timing, power and area.
MMMC design management is made easier by simplifying the control over active versus reported scenarios, and displaying results for all scenarios concurrently. By consolidating this data into charts and graphs, the Talus Visual Volcano saves time and improves efficiency by removing the need for tedious analysis of log files and textual reports.
Production shipments of Talus 1.1 will begin in June 2009.
TriQuint selects Synopsys' TCAD Sentaurus for compound semicon development
MOUNTAIN VIEW, USA: Synopsys Inc. announced that TriQuint Semiconductor has adopted Synopsys' TCAD Sentaurus device simulation software to support its research and development of high-frequency and high-power semiconductor devices targeting mobile handsets, 3G and 4G base stations, Wi-Fi, WiMAX, and defense and aerospace applications.
TCAD Sentaurus' accurate modeling and other advanced capabilities enable TriQuint to speed up the development of heterojunction field-effect transistors (HFETs), heterojunction bipolar transistors (HBTs), and other devices fabricated with compound semiconductors. TCAD Sentaurus accomplishes this by supporting wafer experiments with detailed simulations of the electrical and thermal behavior of these devices.
Compound semiconductor devices are critical components in high-frequency applications where silicon-based devices cannot meet frequency, power generation or efficiency requirements. As a leader in radio frequency (RF) components and solutions, TriQuint develops a wide range of III-V and III-Nitride devices tailored to specific RF applications.
"Many of our products at TriQuint combine high-frequency and high-efficiency requirements which can only be met with compound semiconductor transistor technology. TCAD Sentaurus helps us tailor and optimize the design of these transistors to specific applications, and to deliver truly innovative solutions to our customers," said Otto Berger, director Advanced Technology at TriQuint.
The TCAD Sentaurus product family comprises 2D and 3D process and device simulation tools used for exploring and optimizing silicon and compound semiconductor technologies.
"Compound semiconductors play a vital role in today's and tomorrow's wireless world. We've seen a rising interest in the application of our simulation tools to the design of these devices as companies continue to push against the envelope of high-frequency and high-efficiency to meet stringent wireless requirements," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "TriQuint is a leader in the compound semiconductor segment, and its adoption of TCAD Sentaurus is a testament to the value Synopsys TCAD simulation brings to the market."
TCAD Sentaurus' accurate modeling and other advanced capabilities enable TriQuint to speed up the development of heterojunction field-effect transistors (HFETs), heterojunction bipolar transistors (HBTs), and other devices fabricated with compound semiconductors. TCAD Sentaurus accomplishes this by supporting wafer experiments with detailed simulations of the electrical and thermal behavior of these devices.
Compound semiconductor devices are critical components in high-frequency applications where silicon-based devices cannot meet frequency, power generation or efficiency requirements. As a leader in radio frequency (RF) components and solutions, TriQuint develops a wide range of III-V and III-Nitride devices tailored to specific RF applications.
"Many of our products at TriQuint combine high-frequency and high-efficiency requirements which can only be met with compound semiconductor transistor technology. TCAD Sentaurus helps us tailor and optimize the design of these transistors to specific applications, and to deliver truly innovative solutions to our customers," said Otto Berger, director Advanced Technology at TriQuint.
The TCAD Sentaurus product family comprises 2D and 3D process and device simulation tools used for exploring and optimizing silicon and compound semiconductor technologies.
"Compound semiconductors play a vital role in today's and tomorrow's wireless world. We've seen a rising interest in the application of our simulation tools to the design of these devices as companies continue to push against the envelope of high-frequency and high-efficiency to meet stringent wireless requirements," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "TriQuint is a leader in the compound semiconductor segment, and its adoption of TCAD Sentaurus is a testament to the value Synopsys TCAD simulation brings to the market."
Raja retains Telecom and IT, Dr Farooq Abdullah gets MNRE
Folks, these are portfolios of the key ministries in the government of India related to IT, telecommunications, semiconductors and solar energy, announced this evening by the Government of India.
* A. Raja: Minister of Communications and Information Technology
* Dr. Farooq Abdullah: Minister of New and Renewable Energy
* Gurdas Kamat: Minister of State in the Ministry of Communications and Information Technology
* Sachin Pilot: Minister of State in the Ministry of Communications and Information Technology
The fact the A. Raja continues with the telecom and IT ministry is a welcome sign of continuity! As per published reports, the auction for 3G networks is said to be a top priority for India's telecom minister. About time that a date was set for 3G auction without delay!
What to expect from telecom, semicon and solar/PV
First, telecom, since it has been India's success story for over a decade now! As at this point in time, India would stand to make revenues from the 3G auction.
According to a Times of India report: The interim budget has already factored in revenues of Rs 20,000 crore from 3G auctions, just half telecom minister A Raja's projections of Rs 40,000 crore in August 2008. Average pan-India 3G spectrum is expected to rake in over Rs 4,000 crore. The government plans to auction 2x5 MHz of spectrum in varying proportions except Rajasthan and the North East.
The key focus should simultaneously be on semiconductors, solar photovoltaics and new and renewable energy. With a new minister coming in for NRE (new and renewable energy), there are going to be a lot of expectations.
The opportunities in the Indian solar/PV landscape simply cannot be overlooked at any cost or any further!
Don't look further folks! Just read the US President, Barack Obama's, remarks on renewable energy! That's the kind of focus India needs as well!!
A recent SEMI India meet this April called for more action from the government of India, a more closer industry-government collaboration, as well as the need for financial institutions to pay more attention to the solar/PV segment in India.
All of these need to be addressed at top priority! Perhaps, the Union Ministry for Power should be part of this exercise as well. All it needs to do is to look at the benefits of solar/PV in off-grid applications, such as basic lighting and electrification of rural homes, irrigation pump sets running on solar, and urban applications -- such as street lighting, etc.
The Telecom ministry should also consider solar for power back-up for cellular base station towers. Approximately, there will be 2.9 lakh base station towers by the end of 2009. Maybe, having solar in some place, will surely go a long way in saving some power for the country!
Therefore, these ministries would need to work hand in hand!
Finally, semiconductors! What's really happening with the semiconductor policy? If there are proposals that need to be cleared and passed, and projects need to be started thereafter, those should be cleared and implemented at the earliest possible instance. I believe there are several such proposals. India cannot afford to lose time, now that it has a stable Central government in place.
Next, do look at how the governments of China and Taiwan, as two examples, back their home grown semiconductor industries. A similar effort would be needed here. And let's not get involved in the fabs vs. fabless debate. There is a definite need to rethink on India's semiconductor fab strategy -- whatever that is going to be in future!
S. Janakiraman, former chairman, India Semiconductor Association (ISA), had told me a few months ago that a fab will be fundamental for India to gain leadership and self reliance. "It cannot be ignored totally, although we can take our own time to reach there. We don't have a choice other than paying a price to reach there, now or later!"
Yet another aspect that needs to be looked into is to find a way to incubate semiconductor product development companies in India.
Am sure that, besides these points, there are several other things that the leaders of the Indian semiconductor, solar/PV and telecom sectors have in mind. For now, let us welcome our new Union ministers and wish them the best of luck!
* A. Raja: Minister of Communications and Information Technology
* Dr. Farooq Abdullah: Minister of New and Renewable Energy
* Gurdas Kamat: Minister of State in the Ministry of Communications and Information Technology
* Sachin Pilot: Minister of State in the Ministry of Communications and Information Technology
The fact the A. Raja continues with the telecom and IT ministry is a welcome sign of continuity! As per published reports, the auction for 3G networks is said to be a top priority for India's telecom minister. About time that a date was set for 3G auction without delay!
What to expect from telecom, semicon and solar/PV
First, telecom, since it has been India's success story for over a decade now! As at this point in time, India would stand to make revenues from the 3G auction.
According to a Times of India report: The interim budget has already factored in revenues of Rs 20,000 crore from 3G auctions, just half telecom minister A Raja's projections of Rs 40,000 crore in August 2008. Average pan-India 3G spectrum is expected to rake in over Rs 4,000 crore. The government plans to auction 2x5 MHz of spectrum in varying proportions except Rajasthan and the North East.
The key focus should simultaneously be on semiconductors, solar photovoltaics and new and renewable energy. With a new minister coming in for NRE (new and renewable energy), there are going to be a lot of expectations.
The opportunities in the Indian solar/PV landscape simply cannot be overlooked at any cost or any further!
Don't look further folks! Just read the US President, Barack Obama's, remarks on renewable energy! That's the kind of focus India needs as well!!
A recent SEMI India meet this April called for more action from the government of India, a more closer industry-government collaboration, as well as the need for financial institutions to pay more attention to the solar/PV segment in India.
All of these need to be addressed at top priority! Perhaps, the Union Ministry for Power should be part of this exercise as well. All it needs to do is to look at the benefits of solar/PV in off-grid applications, such as basic lighting and electrification of rural homes, irrigation pump sets running on solar, and urban applications -- such as street lighting, etc.
The Telecom ministry should also consider solar for power back-up for cellular base station towers. Approximately, there will be 2.9 lakh base station towers by the end of 2009. Maybe, having solar in some place, will surely go a long way in saving some power for the country!
Therefore, these ministries would need to work hand in hand!
Finally, semiconductors! What's really happening with the semiconductor policy? If there are proposals that need to be cleared and passed, and projects need to be started thereafter, those should be cleared and implemented at the earliest possible instance. I believe there are several such proposals. India cannot afford to lose time, now that it has a stable Central government in place.
Next, do look at how the governments of China and Taiwan, as two examples, back their home grown semiconductor industries. A similar effort would be needed here. And let's not get involved in the fabs vs. fabless debate. There is a definite need to rethink on India's semiconductor fab strategy -- whatever that is going to be in future!
S. Janakiraman, former chairman, India Semiconductor Association (ISA), had told me a few months ago that a fab will be fundamental for India to gain leadership and self reliance. "It cannot be ignored totally, although we can take our own time to reach there. We don't have a choice other than paying a price to reach there, now or later!"
Yet another aspect that needs to be looked into is to find a way to incubate semiconductor product development companies in India.
Am sure that, besides these points, there are several other things that the leaders of the Indian semiconductor, solar/PV and telecom sectors have in mind. For now, let us welcome our new Union ministers and wish them the best of luck!
Synopsys releases DesignWare SATA IP
MOUNTAIN VIEW, USA: Synopsys Inc. announced the availability of DesignWare SATA AHCI host and device digital controller IP for the latest SATA 6 Gigabit per second (Gbps) data transfer rate as defined in the Serial ATA (SATA) Revision 3.0 specification.
This doubles the data rate of the previous (version 2.6) specification. DesignWare SATA IP significantly speeds the deployment of the 6Gbps interface into solid state drives and enterprise class storage system SoCs. Synopsys will be demonstrating its SATA 6Gbps capabilities in the SATA-IO booth at the upcoming Computex exhibition in Taiwan, from June 2-6.
The DesignWare SATA digital controllers for the SATA 6Gbps data transfer rate support numerous features available in the SATA Revision 3.0 Specification including new streaming Native Command Queuing (NCQ) and power management states. Streaming NCQ introduces isochrononous priority to help improve the quality of service for audio/video streaming.
For more power efficient systems, the DesignWare SATA controllers implement power mode states that allow a direct transition from partial to full slumber mode, bypassing the active state. Furthermore, the inclusion of a well-defined embedded DMA engine enables designers to achieve optimal system performance while maintaining low latency and minimal CPU overhead. The included VMM-enabled DesignWare SATA Verification IP speeds the development of powerful SystemVerilog testbenches.
The SATA interface has evolved to address the growing demand for higher performance, greater storage capacity and longer battery life in mass storage devices such as solid state drives, hard disk drives and host storage controllers. As devices saturate the current SATA 3Gbps data transfer rate, the SATA 6Gbps interface, with 600 MB/s of read/write speed, addresses high bandwidth needs.
Furthermore, the latest specification is backward compatible with the SATA 1.5Gbps and SATA 3Gbps interfaces, allowing designers to easily migrate to the faster data transfer rate while maintaining interoperability with existing SATA products.
"By providing IP that supports the SATA 3.0 specification, Synopsys is enabling the design community to quickly adopt the SATA interface and benefit from the fast 6Gbps data transfer rate," said Marc Noblitt, SATA-IO board representative. "We look forward to seeing our members continue to drive advancements that help make SATA the storage interface of choice."
"As a leading provider of SATA IP, Synopsys employs a comprehensive validation process to deliver DesignWare IP that is of high quality and functions to the SATA 3.0 specification," said Kevin Kearney, PSG director of Storage Protocol Products at LeCroy. "By utilizing LeCroy's protocol analyzer as an additional element in their verification process, Synopsys gives designers further confidence that the DesignWare SATA IP has met the full range of protocol requirements at the new higher 6Gbps speeds."
"Next generation SSD's and Enterprise Storage Controllers are driving significant advancements into the storage market such as higher bandwidth, enhanced power efficiency and increased reliability," said John Koeter, vice president of the Solutions Group at Synopsys. "As companies incorporate the new SATA 6Gbps interface in their high-performance SoCs, Synopsys is there with a high-quality, silicon-proven IP solution that will help designers quickly implement the latest SATA functionality with less risk and improved time-to-market."
Synopsys provides designers with a complete DesignWare SATA IP solution consisting of the device and host digital controllers, PHY and verification IP, which are silicon-proven and shipping in volume production. The complete solution has passed the latest SATA-IO Building Block interoperability testing at the SATA 3Gbps data transfer rate.
Synopsys will participate in the SATA 6Gbps interoperability testing as it becomes available. Synopsys will be attending the upcoming SATA-IO Plugfest and Interoperability Workshop in June 2009 with its DesignWare SATA IP solution.
The DesignWare SATA AHCI host and device digital controllers and verification IP for SATA 6Gbps are available now.
This doubles the data rate of the previous (version 2.6) specification. DesignWare SATA IP significantly speeds the deployment of the 6Gbps interface into solid state drives and enterprise class storage system SoCs. Synopsys will be demonstrating its SATA 6Gbps capabilities in the SATA-IO booth at the upcoming Computex exhibition in Taiwan, from June 2-6.
The DesignWare SATA digital controllers for the SATA 6Gbps data transfer rate support numerous features available in the SATA Revision 3.0 Specification including new streaming Native Command Queuing (NCQ) and power management states. Streaming NCQ introduces isochrononous priority to help improve the quality of service for audio/video streaming.
For more power efficient systems, the DesignWare SATA controllers implement power mode states that allow a direct transition from partial to full slumber mode, bypassing the active state. Furthermore, the inclusion of a well-defined embedded DMA engine enables designers to achieve optimal system performance while maintaining low latency and minimal CPU overhead. The included VMM-enabled DesignWare SATA Verification IP speeds the development of powerful SystemVerilog testbenches.
The SATA interface has evolved to address the growing demand for higher performance, greater storage capacity and longer battery life in mass storage devices such as solid state drives, hard disk drives and host storage controllers. As devices saturate the current SATA 3Gbps data transfer rate, the SATA 6Gbps interface, with 600 MB/s of read/write speed, addresses high bandwidth needs.
Furthermore, the latest specification is backward compatible with the SATA 1.5Gbps and SATA 3Gbps interfaces, allowing designers to easily migrate to the faster data transfer rate while maintaining interoperability with existing SATA products.
"By providing IP that supports the SATA 3.0 specification, Synopsys is enabling the design community to quickly adopt the SATA interface and benefit from the fast 6Gbps data transfer rate," said Marc Noblitt, SATA-IO board representative. "We look forward to seeing our members continue to drive advancements that help make SATA the storage interface of choice."
"As a leading provider of SATA IP, Synopsys employs a comprehensive validation process to deliver DesignWare IP that is of high quality and functions to the SATA 3.0 specification," said Kevin Kearney, PSG director of Storage Protocol Products at LeCroy. "By utilizing LeCroy's protocol analyzer as an additional element in their verification process, Synopsys gives designers further confidence that the DesignWare SATA IP has met the full range of protocol requirements at the new higher 6Gbps speeds."
"Next generation SSD's and Enterprise Storage Controllers are driving significant advancements into the storage market such as higher bandwidth, enhanced power efficiency and increased reliability," said John Koeter, vice president of the Solutions Group at Synopsys. "As companies incorporate the new SATA 6Gbps interface in their high-performance SoCs, Synopsys is there with a high-quality, silicon-proven IP solution that will help designers quickly implement the latest SATA functionality with less risk and improved time-to-market."
Synopsys provides designers with a complete DesignWare SATA IP solution consisting of the device and host digital controllers, PHY and verification IP, which are silicon-proven and shipping in volume production. The complete solution has passed the latest SATA-IO Building Block interoperability testing at the SATA 3Gbps data transfer rate.
Synopsys will participate in the SATA 6Gbps interoperability testing as it becomes available. Synopsys will be attending the upcoming SATA-IO Plugfest and Interoperability Workshop in June 2009 with its DesignWare SATA IP solution.
The DesignWare SATA AHCI host and device digital controllers and verification IP for SATA 6Gbps are available now.
NXP unveils lowest power Cortex-M3 based microcontrollers
EINDHOVEN, THE NETHERLANDS: NXP has introduced the industry’s lowest power 32-bit Cortex-M3 based microcontrollers, maintaining its commitment to innovation in energy-efficiency and further extending the world’s broadest range of ARM-based processors.
The new NXP LPC1300 series, based on the Cortex-M3 Rev2 core and designed for embedded 16 and 32-bit applications, operates at 70MHz and consumes approximately 200 µA per MHz, delivering advanced energy management alongside superior levels of integration.
Designed to provide a smooth transition path to 16- and 32-bit applications, the new LPC1311/13/42/43 microcontrollers are pin-compatible with NXP’s Cortex-M0 based LPC1100 series and deliver up to 32kB of flash memory, 8kB of SRAM memory, low-cost USB and up to 42 general purpose I/O pins.
With a built-in Nested Vectored Interrupt Controller (NVIC) and requiring a single 3.3V power supply, the new NXP LPC1300 features an integrated power management unit to minimize power consumption in Sleep, Deep-Sleep and Deep-power-down modes.
The LPC1300 also enables in-system programming and in-application programming via on-chip bootloader software and offer a range of serial interfaces including high speed USB 2.0 with on-chip PHY, UART, SSP/SPI controller and I2C-bus interface.
For ease of use, USB Mass Storage and HID class drivers are included on-chip enabling USB communication to be set up in minutes. Furthermore, these drivers are incorporated in ROM, leaving 100% of the user Flash space for the application.
“Having introduced the fastest Cortex-M3 based LPC1700 just weeks ago, we are now broadening our Cortex-M3 microcontroller portfolio to include the easy to use, low-cost and low-power LPC1300 series,” said Geoff Lees, vice president and general manager, microcontroller product line, NXP Semiconductors. “The new LPC1300 series has the tightest integration and the most advanced power management in this class of products while offering unbeatable value.”
NXP will be demonstrating the new family of LPC1300 microcontrollers at Computex, Taipei, from June 26 2009, and they will be widely available from September 2009. Devices without USB start at $0.99 in 10,000 unit volumes. Those with USB 2.0 will be priced starting at $1.49 in 10,000 unit volumes.
The new NXP LPC1300 series, based on the Cortex-M3 Rev2 core and designed for embedded 16 and 32-bit applications, operates at 70MHz and consumes approximately 200 µA per MHz, delivering advanced energy management alongside superior levels of integration.
Designed to provide a smooth transition path to 16- and 32-bit applications, the new LPC1311/13/42/43 microcontrollers are pin-compatible with NXP’s Cortex-M0 based LPC1100 series and deliver up to 32kB of flash memory, 8kB of SRAM memory, low-cost USB and up to 42 general purpose I/O pins.
With a built-in Nested Vectored Interrupt Controller (NVIC) and requiring a single 3.3V power supply, the new NXP LPC1300 features an integrated power management unit to minimize power consumption in Sleep, Deep-Sleep and Deep-power-down modes.
The LPC1300 also enables in-system programming and in-application programming via on-chip bootloader software and offer a range of serial interfaces including high speed USB 2.0 with on-chip PHY, UART, SSP/SPI controller and I2C-bus interface.
For ease of use, USB Mass Storage and HID class drivers are included on-chip enabling USB communication to be set up in minutes. Furthermore, these drivers are incorporated in ROM, leaving 100% of the user Flash space for the application.
“Having introduced the fastest Cortex-M3 based LPC1700 just weeks ago, we are now broadening our Cortex-M3 microcontroller portfolio to include the easy to use, low-cost and low-power LPC1300 series,” said Geoff Lees, vice president and general manager, microcontroller product line, NXP Semiconductors. “The new LPC1300 series has the tightest integration and the most advanced power management in this class of products while offering unbeatable value.”
NXP will be demonstrating the new family of LPC1300 microcontrollers at Computex, Taipei, from June 26 2009, and they will be widely available from September 2009. Devices without USB start at $0.99 in 10,000 unit volumes. Those with USB 2.0 will be priced starting at $1.49 in 10,000 unit volumes.
SanDisk, Samsung renew patent cross license and flash supply agreements
MILPITAS, USA & SEOUL, KOREA: SanDisk and Samsung Electronics Co. Ltd. have signed a definitive agreement to renew the cross license of their semiconductor patent portfolios.
In addition, the companies signed a flash memory supply agreement under which Samsung will continue to make available to SanDisk a guaranteed portion of its flash memory production output. The new agreements become effective when the current cross license and supply agreements expire on August 14, 2009, and will run for seven years from that date.
The new patent cross-license agreement includes rights to each party’s patents broadly covering multi-level cell flash memory and flash storage systems, but does not license either party’s patent claims specific to 3-D memory technology.
Over the life of the new license, the estimated effective rate of the fixed payments and royalties is expected to be approximately half of the effective rate in recent years under the current license. Financial terms of the agreements were not disclosed.
“We are very pleased with the agreements announced today. We believe that they represent good value for our stockholders and enable both parties to focus on the growth markets at hand. We are excited about our opportunities in mobile, computing and consumer flash storage markets.
Further, continued access to Samsung’s flash capacity under competitive terms gives us greater flexibility in managing our future capital expenditures for captive capacity. We look forward to a constructive relationship with Samsung in the years ahead.” said Dr. Eli Harari, chairman and chief executive officer, SanDisk.
“The renewal agreements enable Samsung and SanDisk to each focus their energies on restoring flash market growth. It is clear that these renewal agreements are aimed at strengthening the on-going business relationship between Samsung and SanDisk, and we are pleased that the two companies have worked hard to achieve a significantly improved balance on the patent license.” said Dr. Oh-Hyun Kwon, president of the Semiconductor Business, Samsung Electronics.
In addition, the companies signed a flash memory supply agreement under which Samsung will continue to make available to SanDisk a guaranteed portion of its flash memory production output. The new agreements become effective when the current cross license and supply agreements expire on August 14, 2009, and will run for seven years from that date.
The new patent cross-license agreement includes rights to each party’s patents broadly covering multi-level cell flash memory and flash storage systems, but does not license either party’s patent claims specific to 3-D memory technology.
Over the life of the new license, the estimated effective rate of the fixed payments and royalties is expected to be approximately half of the effective rate in recent years under the current license. Financial terms of the agreements were not disclosed.
“We are very pleased with the agreements announced today. We believe that they represent good value for our stockholders and enable both parties to focus on the growth markets at hand. We are excited about our opportunities in mobile, computing and consumer flash storage markets.
Further, continued access to Samsung’s flash capacity under competitive terms gives us greater flexibility in managing our future capital expenditures for captive capacity. We look forward to a constructive relationship with Samsung in the years ahead.” said Dr. Eli Harari, chairman and chief executive officer, SanDisk.
“The renewal agreements enable Samsung and SanDisk to each focus their energies on restoring flash market growth. It is clear that these renewal agreements are aimed at strengthening the on-going business relationship between Samsung and SanDisk, and we are pleased that the two companies have worked hard to achieve a significantly improved balance on the patent license.” said Dr. Oh-Hyun Kwon, president of the Semiconductor Business, Samsung Electronics.
AgigA Tech intros first high-speed, high-density, battery-free NVS
POWAY, USA: AgigA Tech Inc., a subsidiary of Cypress Semiconductor Corp., introduced the industry’s first high-speed, high-density non-volatile RAM system. The new AGIGARAM non-volatile system (NVS) technology delivers densities between 4 megabytes (32 megabits) and 2 gigabytes (16 gigabits) and peak transfer rates equivalent to DRAMs.
The AGIGARAM is ideal for a wide range of systems, including storage, networking, communications, industrial computing and controls, medical equipment, gaming systems, ATMs and point-of-sale terminals, printers, scanners, copiers, automotive and military systems.
Until now, high-speed, non-volatile memory choices have been limited, especially when the performance of a RAM is desired. Complementing the nvSRAM offerings from Cypress, the AGIGARAM system scales and extends nonvolatile solutions to much higher densities. The next best high-density alternative, battery-backed memories, can offer high speeds, but are subject to numerous problems, such as hazardous material issues, increased design complexity, long charge times, limited operating life, and a high total cost of ownership.
The AGIGARAM system solves these problems with a novel use of a battery free power sub-system, teamed with high-speed synchronous DRAM, NAND Flash, intelligent power management and a proprietary system controller. During normal operation the AGIGARAM functions exactly like a synchronous DRAM (SDRAM).
When power is lost, however, it automatically saves the data to NAND Flash using the energy stored in the power subsystem. When power is restored, the data is transferred back into the SDRAM. This functionality can be used for power interruption/loss immunity, instant-on recovery, write caching and posting, data logging and journaling, and service and maintenance processing.
“Today's memory technologies all have a problem. DRAM is volatile, flash is slow, SRAM with batteries is unreliable, and alternative technologies are too costly to use in large densities," said Jim Handy, Director of Objective Analysis. "Products like AgigA Tech's that combine the best attributes of DRAM and NAND are likely to meet with broad acceptance."
“AgigA Tech’s unique technology and expertise have yielded a superior solution for high-speed, high-density non-volatile RAM,” said Ron Sartore, CEO of AgigA Tech. “And our relationship with Cypress enables us to work with customers through a world-class sales and distribution network.”
AGIGARAM products and features -- AgigA Tech announced two distinct AGIGARAM product families; BALI and CAPRI.
BALI Product Features: Targeted at general purposes, embedded, and industrial applications:
4-MB to 64-MB densities
High-speed 100 MHz SDRAM
200 MB/sec peak transfers
I2C command/control bus
3.3V VCC for 4 MB to 32 MB, 5.0V VCC for 64 MB
Package: 200-pin SO-DIMM or Mezzanine card
0-70 degrees C operating range
3 year, 5 year and 10 year operating life options
Integrated battery-free power pack
CAPRI Product Features: Targeted at higher end storage, industrial, networking, and communications applications, this product comes in sizes ranging from 256 MB to 2 GB and uses a much higher speed DDR-800 interface. It also integrates a battery-free power pack. Future versions will extend these sizes even further.
Availability
The AGIGARAM BALI product is available now in production. Evaluation kits are also available now. The higher-end DDR2 based CAPRI product will be sampling in July of this year, with production quantities available in September 2009.
The AGIGARAM is ideal for a wide range of systems, including storage, networking, communications, industrial computing and controls, medical equipment, gaming systems, ATMs and point-of-sale terminals, printers, scanners, copiers, automotive and military systems.Until now, high-speed, non-volatile memory choices have been limited, especially when the performance of a RAM is desired. Complementing the nvSRAM offerings from Cypress, the AGIGARAM system scales and extends nonvolatile solutions to much higher densities. The next best high-density alternative, battery-backed memories, can offer high speeds, but are subject to numerous problems, such as hazardous material issues, increased design complexity, long charge times, limited operating life, and a high total cost of ownership.
The AGIGARAM system solves these problems with a novel use of a battery free power sub-system, teamed with high-speed synchronous DRAM, NAND Flash, intelligent power management and a proprietary system controller. During normal operation the AGIGARAM functions exactly like a synchronous DRAM (SDRAM).
When power is lost, however, it automatically saves the data to NAND Flash using the energy stored in the power subsystem. When power is restored, the data is transferred back into the SDRAM. This functionality can be used for power interruption/loss immunity, instant-on recovery, write caching and posting, data logging and journaling, and service and maintenance processing.
“Today's memory technologies all have a problem. DRAM is volatile, flash is slow, SRAM with batteries is unreliable, and alternative technologies are too costly to use in large densities," said Jim Handy, Director of Objective Analysis. "Products like AgigA Tech's that combine the best attributes of DRAM and NAND are likely to meet with broad acceptance."
“AgigA Tech’s unique technology and expertise have yielded a superior solution for high-speed, high-density non-volatile RAM,” said Ron Sartore, CEO of AgigA Tech. “And our relationship with Cypress enables us to work with customers through a world-class sales and distribution network.”
AGIGARAM products and features -- AgigA Tech announced two distinct AGIGARAM product families; BALI and CAPRI.
BALI Product Features: Targeted at general purposes, embedded, and industrial applications:
4-MB to 64-MB densities
High-speed 100 MHz SDRAM
200 MB/sec peak transfers
I2C command/control bus
3.3V VCC for 4 MB to 32 MB, 5.0V VCC for 64 MB
Package: 200-pin SO-DIMM or Mezzanine card
0-70 degrees C operating range
3 year, 5 year and 10 year operating life options
Integrated battery-free power pack
CAPRI Product Features: Targeted at higher end storage, industrial, networking, and communications applications, this product comes in sizes ranging from 256 MB to 2 GB and uses a much higher speed DDR-800 interface. It also integrates a battery-free power pack. Future versions will extend these sizes even further.
Availability
The AGIGARAM BALI product is available now in production. Evaluation kits are also available now. The higher-end DDR2 based CAPRI product will be sampling in July of this year, with production quantities available in September 2009.
Wednesday, May 27, 2009
Silicon results validate design for eBeam methodology at 65nm
SAN JOSE, USA: The eBeam Initiative, a forum dedicated to the education and promotion of a new design-to-manufacturing approach known as design for e-beam (DFEB), announced that steering group members D2S, Inc., e-Shuttle, Inc. and Fujitsu Microelectronics have validated the DFEB methodology for low-volume, 65-nm system-on-chip applications, without sacrificing performance, area or power.
DFEB combines software and design technologies that enable today’s most advanced character projection (CP) e-beam direct-write (EbDW) equipment to reduce shot count, thus making EbDW throughput feasible for low-volume designs. The announcement marks a significant milestone as it demonstrates early progress on the three-year roadmap.
The final estimated shot count for the test chip using DFEB represented a more than 10X reduction over conventional EbDW technologies, while also meeting the required performance, power and area goals. The collaborative effort drew from a number of companies involved in the eBeam Initiative.
Specifically, D2S and Fujitsu Microelectronics worked on the design while e-Shuttle manufactured the test chip to confirm the DFEB technology for the 65-nm node. D2S designed the DFEB library overlay with Fujitsu Microelectronics and also partnered closely with e-Shuttle and Advantest Corporation on the stencil mask used in the fab’s EbDW machine. Prototyping is a target application for DFEB, and with e-Shuttle’s experience in these services, they were able to validate the applicability of DFEB for prototyping.
According to Yoji Hino, corporate executive vice president of Fujitsu Microelectronics Limited and member of the eBeam Initiative steering group, “With this test chip, we now have tangible results that DFEB is enabling us to meet the necessary shot count requirements without sacrificing the quality of design results. DFEB makes maskless prototypes practical now.”
A related paper jointly authored by Advantest, D2S, e-Shuttle and Fujitsu Microelectronics Limited will be presented by e-Shuttle at the session of Electron Beam Lithography Tools during the 53rd International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), taking place May 26-29 in Marco Island, Fla.
The article, titled: “DFEB, a novel approach to EbDW throughput enhancement for volume production,” will be available online after May 29 at www.ebeam.org.
DFEB combines software and design technologies that enable today’s most advanced character projection (CP) e-beam direct-write (EbDW) equipment to reduce shot count, thus making EbDW throughput feasible for low-volume designs. The announcement marks a significant milestone as it demonstrates early progress on the three-year roadmap.
The final estimated shot count for the test chip using DFEB represented a more than 10X reduction over conventional EbDW technologies, while also meeting the required performance, power and area goals. The collaborative effort drew from a number of companies involved in the eBeam Initiative.
Specifically, D2S and Fujitsu Microelectronics worked on the design while e-Shuttle manufactured the test chip to confirm the DFEB technology for the 65-nm node. D2S designed the DFEB library overlay with Fujitsu Microelectronics and also partnered closely with e-Shuttle and Advantest Corporation on the stencil mask used in the fab’s EbDW machine. Prototyping is a target application for DFEB, and with e-Shuttle’s experience in these services, they were able to validate the applicability of DFEB for prototyping.
According to Yoji Hino, corporate executive vice president of Fujitsu Microelectronics Limited and member of the eBeam Initiative steering group, “With this test chip, we now have tangible results that DFEB is enabling us to meet the necessary shot count requirements without sacrificing the quality of design results. DFEB makes maskless prototypes practical now.”
A related paper jointly authored by Advantest, D2S, e-Shuttle and Fujitsu Microelectronics Limited will be presented by e-Shuttle at the session of Electron Beam Lithography Tools during the 53rd International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), taking place May 26-29 in Marco Island, Fla.
The article, titled: “DFEB, a novel approach to EbDW throughput enhancement for volume production,” will be available online after May 29 at www.ebeam.org.
ARC, Realtek to extend reach of ARC Sonic Focus audio technology into PCs, laptops
COMPUTEX TAIPEI 2009, SAN JOSE, USA & ST. ALBANS, UK: ARC International and Realtek Semiconductor, the premier silicon supplier for PCs and laptops, have agreed to bundle the ARC Sonic Focus suite of audio enrichment software with Realtek codecs shipped to its OEM and ODM customers globally.
In return, ARC has optimized its Sonic Focus software technology for the Realtek codec for PC and laptop applications. The companies’ efforts already have resulted in a major win with a tier one PC OEM, in which the Sonic Focus software suite on a Realtek codec will enhance the multimedia experience for consumers using music, movies, and games.
“ARC’s Sonic Focus audio enrichment software is generating significant attention among key players in the PC and consumer electronics industry as a means of reducing bill-of-materials costs,” said Wayne Lin, vice president of Computer Peripherals Business Unit at Realtek Semiconductor Corp. “Sonic Focus technology also can be tailored to a specific device so it delivers a unique, signature sound experience. This creates differentiation for the OEM and ODM customer and is a key reason we chose to partner with ARC for the PC and laptop market.”
“The agreement with Realtek is a significant endorsement of ARC’s audio quality strategy by a renowned industry leader in the PC and embedded markets. Working in partnership, ARC and Realtek will extend the benefits of Sonic Focus audio technology to a broader range of OEMs and ODMs developing PC and laptop applications,” said Michael Franzi, worldwide vice president of marketing at ARC International.
“In the highly competitive consumer electronics market, the key to winning is providing OEM and ODM companies with fast development and cost-effective solutions that improve the multimedia experience for consumers. Sonic Focus technology is unique in its ability to achieve these goals, while improving the consumer audio experience. It was developed over years of partnerships with music and movie industry icons and now delivers a powerful audio experience to worldwide consumers using a variety of electronics products.”
The ARC-Realtek agreement marks another milestone in ARC’s new direction of offering complete Sound-to-Silicon solutions to chip manufacturers and OEMs and ODMs customers.
In return, ARC has optimized its Sonic Focus software technology for the Realtek codec for PC and laptop applications. The companies’ efforts already have resulted in a major win with a tier one PC OEM, in which the Sonic Focus software suite on a Realtek codec will enhance the multimedia experience for consumers using music, movies, and games.
“ARC’s Sonic Focus audio enrichment software is generating significant attention among key players in the PC and consumer electronics industry as a means of reducing bill-of-materials costs,” said Wayne Lin, vice president of Computer Peripherals Business Unit at Realtek Semiconductor Corp. “Sonic Focus technology also can be tailored to a specific device so it delivers a unique, signature sound experience. This creates differentiation for the OEM and ODM customer and is a key reason we chose to partner with ARC for the PC and laptop market.”
“The agreement with Realtek is a significant endorsement of ARC’s audio quality strategy by a renowned industry leader in the PC and embedded markets. Working in partnership, ARC and Realtek will extend the benefits of Sonic Focus audio technology to a broader range of OEMs and ODMs developing PC and laptop applications,” said Michael Franzi, worldwide vice president of marketing at ARC International.
“In the highly competitive consumer electronics market, the key to winning is providing OEM and ODM companies with fast development and cost-effective solutions that improve the multimedia experience for consumers. Sonic Focus technology is unique in its ability to achieve these goals, while improving the consumer audio experience. It was developed over years of partnerships with music and movie industry icons and now delivers a powerful audio experience to worldwide consumers using a variety of electronics products.”
The ARC-Realtek agreement marks another milestone in ARC’s new direction of offering complete Sound-to-Silicon solutions to chip manufacturers and OEMs and ODMs customers.
Rambus unveils new innovations for main memory
LOS ALTOS, USA: Rambus Inc., one of the world's premier technology licensing companies specializing in high-speed memory architectures, has unveiled a set of innovations that can advance computing main memory beyond current DDR3 data rate limits to 3200Mbps.
These innovations, available for licensing, build on Rambus’ award-winning designs and include patented and patent pending technologies. Through this collection of innovations, designers can achieve higher memory data rates, higher effective throughput, better power efficiency and the increased capacity necessary for future computing applications.
"Product advancements in multi-core computing, virtualization and chip integration put ever-increasing demands on the memory sub-system, a key performance limiter in today’s performance computing systems," said Craig Hampel, Rambus Fellow. "This collection of breakthrough innovations from Rambus allows for memory systems that are better suited for the bandwidth and workloads of these throughput-oriented multi-core processors, increasing the design and solution space for future main memory to enable a new generation of computing platforms."
The Rambus key innovations to advance the main memory roadmap include:
* FlexPhase Technology -- introduced in the XDR memory architecture, can enable higher data rates compared to direct strobing technology used in DDR3;
* Near Ground Signaling -- supports high performance at greatly reduced IO power, allowing operation at 0.5V while still maintaining robust signal integrity;
* FlexClocking Architecture -- introduced in Rambus’ Mobile Memory Initiative, reduces clocking power by eliminating the need for a DLL or PLL on the DRAM;
* Module Threading -- increases memory efficiency and reduces DRAM core power, and when combined with Near Ground Signaling and FlexClocking technology, can cut total memory system power by over 40 percent;
* Dynamic Point-to-Point (DPP) -- provides a path for capacity upgrades without compromising performance through robust point-to-point signaling.
These innovations, available for licensing, build on Rambus’ award-winning designs and include patented and patent pending technologies. Through this collection of innovations, designers can achieve higher memory data rates, higher effective throughput, better power efficiency and the increased capacity necessary for future computing applications.
"Product advancements in multi-core computing, virtualization and chip integration put ever-increasing demands on the memory sub-system, a key performance limiter in today’s performance computing systems," said Craig Hampel, Rambus Fellow. "This collection of breakthrough innovations from Rambus allows for memory systems that are better suited for the bandwidth and workloads of these throughput-oriented multi-core processors, increasing the design and solution space for future main memory to enable a new generation of computing platforms."
The Rambus key innovations to advance the main memory roadmap include:
* FlexPhase Technology -- introduced in the XDR memory architecture, can enable higher data rates compared to direct strobing technology used in DDR3;
* Near Ground Signaling -- supports high performance at greatly reduced IO power, allowing operation at 0.5V while still maintaining robust signal integrity;
* FlexClocking Architecture -- introduced in Rambus’ Mobile Memory Initiative, reduces clocking power by eliminating the need for a DLL or PLL on the DRAM;
* Module Threading -- increases memory efficiency and reduces DRAM core power, and when combined with Near Ground Signaling and FlexClocking technology, can cut total memory system power by over 40 percent;
* Dynamic Point-to-Point (DPP) -- provides a path for capacity upgrades without compromising performance through robust point-to-point signaling.
ST-Ericsson, China Mobile to bring TD-SCDMA to mass market
GENEVA, SWITZERLAND: China Mobile has selected ST-Ericsson’s company in China, T3G, as a major technology partner for the development of its high-end and low-cost handsets, based on the 3G standard TD-SCDMA. ST-Ericsson will also support four of its customers to commercialize their mobile phones during 2009-2010.
Under the agreement, ST-Ericsson, the 50/50 joint venture between Ericsson and STMicroelectronics, will develop a new low-cost platform to support its customers to offer affordable TD-SCDMA devices to the China consumers.
ST-Ericsson will also support customers to develop high-end mobile phones, based on existing and new platforms such as the T7210, which will allow consumers to enjoy high-speed broadband and multimedia services.
“Although ST-Ericsson is a recent joint venture, our subsidiary T3G has been actively developing platforms for the mobile standard for more than six years, achieving an impressive record of world firsts in bringing innovation to China,” said Alain Dutheil, President and CEO of ST-Ericsson. “Our dedicated local R&D team, as well as our strong commitment to continuous innovation and close cooperation with customers, will enable China Mobile to offer a broad range of handsets for the mass market as well as for the high-end segment.”
ST-Ericsson’s T7210 mobile platform supports TD-SCDMA dual-band in 2010-2025MHz/1880-1920MHz frequencies, and has successfully completed handovers of voice and high-speed data services in order to operate optimally in Chinese dual-band network environments.
Under the agreement, ST-Ericsson, the 50/50 joint venture between Ericsson and STMicroelectronics, will develop a new low-cost platform to support its customers to offer affordable TD-SCDMA devices to the China consumers.
ST-Ericsson will also support customers to develop high-end mobile phones, based on existing and new platforms such as the T7210, which will allow consumers to enjoy high-speed broadband and multimedia services.
“Although ST-Ericsson is a recent joint venture, our subsidiary T3G has been actively developing platforms for the mobile standard for more than six years, achieving an impressive record of world firsts in bringing innovation to China,” said Alain Dutheil, President and CEO of ST-Ericsson. “Our dedicated local R&D team, as well as our strong commitment to continuous innovation and close cooperation with customers, will enable China Mobile to offer a broad range of handsets for the mass market as well as for the high-end segment.”
ST-Ericsson’s T7210 mobile platform supports TD-SCDMA dual-band in 2010-2025MHz/1880-1920MHz frequencies, and has successfully completed handovers of voice and high-speed data services in order to operate optimally in Chinese dual-band network environments.
Exar selects Synopsys as leading EDA partner
MOUNTAIN VIEW, USA: Synopsys Inc. announced that Exar Corp., a leading provider of analog and mixed-signal solutions for connectivity and power management, has signed an expanded business agreement to establish Synopsys as its leading EDA partner.
As a result of the new multi-year agreement, the Synopsys' Galaxy Implementation and Discovery Verification platforms will be Exar's key design environment for designs at 65nm and below.
"We conducted an extensive evaluation process to select an EDA partner to not only support our current project needs, but our future design horizon as well, and Synopsys was the clear choice," said George Apostol, senior vice president and CTO, Exar.
"Over the years, Synopsys has demonstrated the technology leadership and outstanding technical support that is vital to helping us deliver highly differentiated silicon solutions to our customers. Synopsys tools, especially for mixed-signal designs, are ideal for our forthcoming data communications, storage, interface and power management products."
With the most recent agreement, Exar has chosen products that span Synopsys' broad portfolio. These products include Synopsys' Galaxy implementation platform featuring IC Compiler place-and-route technology, Design Compiler Graphical synthesis, PrimeTime PX timing and power analysis, PrimeRail power network analysis, Star-RCXT parasitic extraction, Hercules physical verification, TetraMAX automatic test pattern generation, and DFT MAX adaptive scan compression; Synopsys' Discovery verification platform featuring the VCS, HSPICE, HSPICE RF and CustomSim simulators for analog and digital verification, MVRC static voltage-aware verification, and MVSIM voltage-aware simulation; and DesignWare Library IP.
"Companies like Exar succeed through their ability to create highly differentiated designs and are justifiably selective when it comes to the partners with whom they entrust their design flows," said John Chilton, senior vice president of Marketing and Strategic Development at Synopsys. "Synopsys welcomes the opportunity for a long-term partnership with Exar, and we look forward to helping them further distinguish their products through technical innovation and rapid market introduction."
As a result of the new multi-year agreement, the Synopsys' Galaxy Implementation and Discovery Verification platforms will be Exar's key design environment for designs at 65nm and below.
"We conducted an extensive evaluation process to select an EDA partner to not only support our current project needs, but our future design horizon as well, and Synopsys was the clear choice," said George Apostol, senior vice president and CTO, Exar.
"Over the years, Synopsys has demonstrated the technology leadership and outstanding technical support that is vital to helping us deliver highly differentiated silicon solutions to our customers. Synopsys tools, especially for mixed-signal designs, are ideal for our forthcoming data communications, storage, interface and power management products."
With the most recent agreement, Exar has chosen products that span Synopsys' broad portfolio. These products include Synopsys' Galaxy implementation platform featuring IC Compiler place-and-route technology, Design Compiler Graphical synthesis, PrimeTime PX timing and power analysis, PrimeRail power network analysis, Star-RCXT parasitic extraction, Hercules physical verification, TetraMAX automatic test pattern generation, and DFT MAX adaptive scan compression; Synopsys' Discovery verification platform featuring the VCS, HSPICE, HSPICE RF and CustomSim simulators for analog and digital verification, MVRC static voltage-aware verification, and MVSIM voltage-aware simulation; and DesignWare Library IP.
"Companies like Exar succeed through their ability to create highly differentiated designs and are justifiably selective when it comes to the partners with whom they entrust their design flows," said John Chilton, senior vice president of Marketing and Strategic Development at Synopsys. "Synopsys welcomes the opportunity for a long-term partnership with Exar, and we look forward to helping them further distinguish their products through technical innovation and rapid market introduction."
Hynix to post $397 million for infringing Rambus patents
LOS ALTOS, USA: Rambus Inc. announced that the US District Court for the Northern District of California has ordered Hynix Semiconductor to secure the judgment amount of approximately $397 million through a combination of a bond and a lien on a Hynix property in South Korea for infringing Rambus patents.
The bonded amount of $250 million is required to be posted within 45 days of the order. The lien will only serve as security if a new appraisal of the Hynix property shows a fair market value of at least double the amount of the judgment not secured by the bond. If the appraisal is inadequate, Rambus may ask the Court to substitute other security.
Final judgment in this matter was entered against Hynix on March 10, 2009 in the amount of approximately $134 million for infringement through December 31, 2005 and approximately $215 million for its infringement from January 1, 2006 through January 31, 2009. In addition, the Court awarded about $48M in pre-judgment interest to Rambus.
“We fully expect the judgment against Hynix to be upheld on appeal, and that we will be entitled to collect the entire amount of the judgment,” said Thomas Lavelle, senior vice president and general counsel at Rambus. “We appreciate the Court’s thoughtful consideration in this case, however, we believe Hynix should have been required to post a bond for the entire amount of the judgment. If Hynix’s proposed lien fails to show value of roughly $300 million, we will ask the Court for other security in order to protect Rambus’ interests.”
In addition, the Court ordered Hynix to pay compulsory license fees into escrow pending the outcome of the appeal Hynix filed in this matter. The Court ordered Hynix to pay Rambus royalties on net sales after January 31, 2009 and before April 18, 2010 of 1 percent for SDR SDRAM and 4.25 percent for DDR SDRAM memory devices.
The latter rate applies to DDR, DDR2, DDR3, GDDR, gDDR2 and GDDR3 SDRAM devices, as well as DDR SGRAM devices. Damages and the compulsory license apply to US infringements of the patent claims in suit.
Background of the case
This case was originally filed by Hynix against Rambus in August 2000. The Honorable Ronald M. Whyte of the U.S. District Court for the Northern District of California split the case into three separate phases with Rambus subsequently prevailing in all three phases.
During the first phase, Hynix alleged that Rambus’ patents were invalid based on the doctrine of unclean hands. The Court issued its Findings of Fact and Conclusions of Law in Rambus’ favor in January 2006. The Court reaffirmed its finding of no spoliation when it denied Hynix’s motion for reconsideration in February 2009.
The second phase dealt with Rambus’ allegations that Hynix memory products infringed its patents. In April 2006, a jury unanimously found that all 10 Rambus patent claims at issue in that trial are valid and infringed by Hynix memory products. The jury award of approximately $307 million in damages for US sales of infringing Hynix products through December 31, 2005, was subsequently reduced by the Court to approximately $134 million.
In the third and final phase of the case, Hynix (together with Micron and Nanya) tried its remaining claims and defenses against Rambus including antitrust and fraud claims based on Rambus’ participation in a standard-setting organization called JEDEC. In March 2008, a jury found Rambus had acted properly during its participation in JEDEC in the early 1990s. The Court similarly found in Rambus’ favor in a decision issued on March 3, 2009.
The bonded amount of $250 million is required to be posted within 45 days of the order. The lien will only serve as security if a new appraisal of the Hynix property shows a fair market value of at least double the amount of the judgment not secured by the bond. If the appraisal is inadequate, Rambus may ask the Court to substitute other security.
Final judgment in this matter was entered against Hynix on March 10, 2009 in the amount of approximately $134 million for infringement through December 31, 2005 and approximately $215 million for its infringement from January 1, 2006 through January 31, 2009. In addition, the Court awarded about $48M in pre-judgment interest to Rambus.
“We fully expect the judgment against Hynix to be upheld on appeal, and that we will be entitled to collect the entire amount of the judgment,” said Thomas Lavelle, senior vice president and general counsel at Rambus. “We appreciate the Court’s thoughtful consideration in this case, however, we believe Hynix should have been required to post a bond for the entire amount of the judgment. If Hynix’s proposed lien fails to show value of roughly $300 million, we will ask the Court for other security in order to protect Rambus’ interests.”
In addition, the Court ordered Hynix to pay compulsory license fees into escrow pending the outcome of the appeal Hynix filed in this matter. The Court ordered Hynix to pay Rambus royalties on net sales after January 31, 2009 and before April 18, 2010 of 1 percent for SDR SDRAM and 4.25 percent for DDR SDRAM memory devices.
The latter rate applies to DDR, DDR2, DDR3, GDDR, gDDR2 and GDDR3 SDRAM devices, as well as DDR SGRAM devices. Damages and the compulsory license apply to US infringements of the patent claims in suit.
Background of the case
This case was originally filed by Hynix against Rambus in August 2000. The Honorable Ronald M. Whyte of the U.S. District Court for the Northern District of California split the case into three separate phases with Rambus subsequently prevailing in all three phases.
During the first phase, Hynix alleged that Rambus’ patents were invalid based on the doctrine of unclean hands. The Court issued its Findings of Fact and Conclusions of Law in Rambus’ favor in January 2006. The Court reaffirmed its finding of no spoliation when it denied Hynix’s motion for reconsideration in February 2009.
The second phase dealt with Rambus’ allegations that Hynix memory products infringed its patents. In April 2006, a jury unanimously found that all 10 Rambus patent claims at issue in that trial are valid and infringed by Hynix memory products. The jury award of approximately $307 million in damages for US sales of infringing Hynix products through December 31, 2005, was subsequently reduced by the Court to approximately $134 million.
In the third and final phase of the case, Hynix (together with Micron and Nanya) tried its remaining claims and defenses against Rambus including antitrust and fraud claims based on Rambus’ participation in a standard-setting organization called JEDEC. In March 2008, a jury found Rambus had acted properly during its participation in JEDEC in the early 1990s. The Court similarly found in Rambus’ favor in a decision issued on March 3, 2009.
Fujitsu Microelectronics adopts Mentor's Calibre design-to-silicon platform
WILSONVILLE, USA: Mentor Graphics Corp. announced that Fujitsu Microelectronics Ltd has qualified and adopted the Calibre design-to-silicon platform for physical verification and design-for-manufacturing (DFM) of advanced IC products.
Fujitsu Microelectronics’ Mentor-based flow includes the sign-off standard Calibre verification platform with Calibre nmDRC, LVS, and xRC tools, and Mentor’s comprehensive DFM solution for manufacturing variability, an integrated tool suite for critical area analysis, litho-friendly design, and 3D variability.
The 3D variability solution provides improved planarity by enabling highly optimized fill based on either complex geometry-based rules, or full thickness (CMP) simulation.
“Fujitsu Microelectronics' leading-edge technologies require tight control over thickness variation. Density-based fill is a starting point and an improvement over traditional dummy fill, but at smaller features sizes our analysis shows that we need to consider more than just density,” said Noboru Yokota, General Manager of the Technology Development Division at Fujitsu Microelectronics. “The Mentor solution is unique because it can handle complex equations combining all the factors required to compute an optimum fill that achieves our planarity goals with as few added shapes as possible.”
“Our long-term partnership with Fujitsu Microelectronics has resulted in a complete solution that meets Fujitsu Microelectronics’ verification and DFM requirements for their latest IC designs regardless of which process offering is being targeted,” said Joseph Sawicki, Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics.
“Our customers are moving to all-Mentor flows because we offer both the best-in-class technology for each design task, as well as the ease of integration and use that can only be achieved with a single integrated platform and tools built from the ground up to work together seamlessly,” he added.
Mentor’s DFM solution
The Calibre nm platform, with the Calibre nmDRC and Calibre LVS tools, has become the golden standard for verification of advanced ICs. Mentor’s comprehensive DFM solution is tightly integrated with the Calibre platform and supports the highest performance designs at advanced nodes with better control of manufacturing variability for cell libraries as well as full-chip layouts.
The Calibre DFM solution includes the Calibre LFDproduct, which provides accurate modeling of lithographic process and etch characteristics, and is the standard sign-off flow for litho hotspot and variability analysis for IP and full-chip applications.
It is fully integrated with the Calibre nmDRC, Calibre LVS (Layout vs. Schematic) and Calibre xRC products, allowing critical device and interconnect characteristics to be extracted based on accurately-modeled, “as-built” contour geometries. The resulting physical data can be plugged into a SPICE simulator to produce an accurate timing simulation of how physical blocks will actually perform.
The Calibre DFM solution includes the Calibre YieldAnalyzer and Calibre YieldEnhancer products for automated CAA analysis and fixing. The YieldEnhancer tool includes a SmartFill intelligent fill capability, which performs metal fills based on metal density and density gradients.
The Calibre CMPAnalyzer tool enables CMP planarity analysis and fill enhancement based on comprehensive, foundry-specific thickness models. Together, these products comprehensively address the variability issues of manufacturing at 65nm and below by making the physical design flow more process-aware and robust, reducing yield surprises late in the development cycle.
Fujitsu Microelectronics’ Mentor-based flow includes the sign-off standard Calibre verification platform with Calibre nmDRC, LVS, and xRC tools, and Mentor’s comprehensive DFM solution for manufacturing variability, an integrated tool suite for critical area analysis, litho-friendly design, and 3D variability.
The 3D variability solution provides improved planarity by enabling highly optimized fill based on either complex geometry-based rules, or full thickness (CMP) simulation.
“Fujitsu Microelectronics' leading-edge technologies require tight control over thickness variation. Density-based fill is a starting point and an improvement over traditional dummy fill, but at smaller features sizes our analysis shows that we need to consider more than just density,” said Noboru Yokota, General Manager of the Technology Development Division at Fujitsu Microelectronics. “The Mentor solution is unique because it can handle complex equations combining all the factors required to compute an optimum fill that achieves our planarity goals with as few added shapes as possible.”
“Our long-term partnership with Fujitsu Microelectronics has resulted in a complete solution that meets Fujitsu Microelectronics’ verification and DFM requirements for their latest IC designs regardless of which process offering is being targeted,” said Joseph Sawicki, Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics.
“Our customers are moving to all-Mentor flows because we offer both the best-in-class technology for each design task, as well as the ease of integration and use that can only be achieved with a single integrated platform and tools built from the ground up to work together seamlessly,” he added.
Mentor’s DFM solution
The Calibre nm platform, with the Calibre nmDRC and Calibre LVS tools, has become the golden standard for verification of advanced ICs. Mentor’s comprehensive DFM solution is tightly integrated with the Calibre platform and supports the highest performance designs at advanced nodes with better control of manufacturing variability for cell libraries as well as full-chip layouts.
The Calibre DFM solution includes the Calibre LFDproduct, which provides accurate modeling of lithographic process and etch characteristics, and is the standard sign-off flow for litho hotspot and variability analysis for IP and full-chip applications.
It is fully integrated with the Calibre nmDRC, Calibre LVS (Layout vs. Schematic) and Calibre xRC products, allowing critical device and interconnect characteristics to be extracted based on accurately-modeled, “as-built” contour geometries. The resulting physical data can be plugged into a SPICE simulator to produce an accurate timing simulation of how physical blocks will actually perform.
The Calibre DFM solution includes the Calibre YieldAnalyzer and Calibre YieldEnhancer products for automated CAA analysis and fixing. The YieldEnhancer tool includes a SmartFill intelligent fill capability, which performs metal fills based on metal density and density gradients.
The Calibre CMPAnalyzer tool enables CMP planarity analysis and fill enhancement based on comprehensive, foundry-specific thickness models. Together, these products comprehensively address the variability issues of manufacturing at 65nm and below by making the physical design flow more process-aware and robust, reducing yield surprises late in the development cycle.
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