Si2’s low power coalition releases CPF standard version 2.0

AUSTIN, USA: The Silicon Integration Initiative (Si2) announced release of the Common Power Format (CPF) Version 2.0, incorporating major enhancements to the widely adopted low-power intent format. CPF 2.0 was approved as an Si2 standard by the Low Power Coalition (LPC).

The enhancements and new capabilities in CPF 2.0 consist of two major categories. Guided by the Si2 Interoperability Guide for Power Format Standards released in March 2010, the release of CPF 2.0 includes the following features to improve interoperability with IEEE 1801-2009: the new concept of generic mode to model either a power mode or a functional mode; the improved hierarchical flow to support output and bi-directional virtual ports; the support of pg_type in supply net connection; more flexibility in modeling different types of isolation, level shifter and retention logic.

In addition, based on contributions from member companies and collaboration with the LPC Modeling Working Group, the following extensions are included in the CPF 2.0 release: the new concept of power design to further improve hierarchical low-power design flow; the improvements in macro-modeling of mixed-signal IP with low power features; simplified modeling methodology for I/O pads with complex power management logic; added flexibility to control the corruption semantics for power aware RTL simulation; and extensions to model new low power standard cells such as multi-bit isolation and level-shifter cells, multi-stage level-shifters, etc.

“Interoperability between power-intent file format commands and concepts is important for end user and tool developers alike. Power affects the entire verification and design flow. IBM and our OEM customers use a myriad of EDA tools in these flows for their design and verification. Easy translation between power formats eases the burden of parsing and modeling the information. Designers can more easily convert from one format to the other to run tools that support one of the formats,” says Leon Stok, VP, Electronic Design Automation Technologies, IBM Systems and Technology Group.

“Along with the practical additions to the language based on four years of use in the industry, another important addition to CPF 2.0 is the combination of functional modes with power modes of a design,” continues Stok. “This allows a designer to consider power management as an integral part of the function. Modeling these two pieces of information together as a single concept allows a design tool to understand the tradeoffs between power and function - something that design teams struggle with today.”

“The Cadence CPF-based low-power solution — with technologies spanning across our System Realization, SoC Realization and Silicon Realization product lines — delivers the most mature flow to address the challenges of modern advanced low-power designs,” said Charlie Huang, senior VP and chief strategy officer at Cadence Design Systems. “Si2’s continuous advancements of CPF enable Cadence to develop new capabilities in our low-power solution to help our customers meet the requirements for future advanced low-power designs.”

“Improvement of interoperability between CPF and IEEE 1801 stands out in CPF 2.0,” says Prabhu Krishnamurthy, senior director, Design Implementation, LSI. “Semantic equivalence to the 1801 standard is achieved by adding new options to commands to specify isolation, level shifter and retention rules. Significantly, the addition of generic mode in CPF makes it compatible with power states in 1801. These changes will help ASIC companies like LSI to more easily use mixed flows with best-in-class tools from different vendors thus enabling better quality and turnaround times.”