SAN JOSE, USA: Atrenta Inc., the leading provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow, announced that it will host seminars in Bangalore, India and Hsinchu City, Taiwan to share the latest technologies and methodologies for Early Design Closure.
During these free full-day seminars, experts from Atrenta and noted industry veterans will present useful, in-depth information on power management, modeling of physical effects at RTL, clock domain crossing verification, design for test, constraints analysis and SoC assembly methodologies for IP and architecture reuse.
The seminars will provide valuable information for engineering managers, chip architects, RTL designers, design methodology specialists and IP design/verification engineers seeking to rapidly implement correct designs through the integrated use of a variety of design automation solutions.
“We’re delighted to take our popular design technology seminars to Bangalore and Hsinchu City and share Atrenta’s expertise in Early Design Closure,” said Mike Gianfagna, vice president of marketing at Atrenta. “These seminars are led by Atrenta’s technology experts and noted veterans from industry and academia. We expect that participants will gain useful knowledge on innovative design technology that optimizes advanced SoCs before expensive and time-consuming detailed implementation begins. The result is accelerated time-to-market and reduced cost.”
Pre-registration is required for these events. The seminar schedule is:
* Achieving Early Power & Physical Closure, Thursday, March 10, 2011 in Bangalore, India.
* Advanced Technology for SoC Analysis & Assembly, Tuesday, March 15, 2011 in Hsinchu City, Taiwan.