MIPS signs license to distribute OEM version of Imperas OVP simulator

THAME, ENGLAND: Imperas, which through the Open Virtual Platforms (OVP) initiative has become the de facto source for instruction accurate processor modeling and simulation, announced that MIPS Technologies Inc. has licensed an OEM version of the OVPsim simulator to provide a fast, instruction accurate simulation product to its licensees.

The models for the MIPS processor cores support the full software view of the processor cores, including both the MIPS32 and microMIPS instruction sets as well as extensions to the instruction sets such as for floating point, DSP and multi-threading capabilities.

The functionality of these models, developed by Imperas, is verified by MIPS Technologies as part of the MIPS-Verified program, which Imperas has participated in since 2008. MIPS licensees will have access to the full range of OVP technology, enabling them to build peripheral models and full virtual platforms with OVP, and to integrate the models into SystemC/TLM-2.0 environments.

“We chose Imperas and the Open Virtual Platforms technology because of the quality of the models and technology,” said Art Swift, vice president of marketing and business development, MIPS Technologies. “We see the positive momentum and leadership position of OVP, and believe this is the best technology for instruction accurate simulation of our processor core models. MIPS Technologies has delivered the first OVP models to lead customers, and we look forward to expanding this program in the future.”

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. OVP models of the complete families of the MIPS32 and microMIPS processors, both single and multi-core are currently available for download from www.OVPworld.org.

Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP models. In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

“We have been working with MIPS Technologies for over 2 years as part of the MIPS-Verified program,” said Simon Davidmann, president and CEO, Imperas, and founding director of the OVP initiative. “During these last two years, we’ve seen OVP grow from its inception to being the industry’s leading independent supplier of instruction accurate models of processor cores. Having these two parallel efforts, the broad acceptance of OVP and our cooperative relationship with MIPS Technologies, come together to provide technology to MIPS licensees building embedded systems is a proud and exciting milestone for us.”