CEA-Leti makes R&D 20nm fully depleted SOI process available through CMP

GRENOBLE, FRANCE & TOKYO, JAPAN: CEA-Leti and CMP (Circuits Multi Projets) announced during the FDSOI Workshop at Tokyo University the launch of an Exploratory MPW (Multi Project Wafers) initiative based on FDSOI (Fully Depleted SOI) 20nm process, opening the access of its 300mm infrastructure to the design community.

This MPW offer is partly supported by EUROSOI+ network that gathers the main European academic partners on SOI.

“Leti has pioneered the SOI technology for years, leading track records in the most advanced research in FDSOI, assessing its key advantages for low power high performance applications with several industrial customers,” said Laurent Malier, CEO of CEA-Leti.

“It is time now to enlarge the diffusion of the FDSOI technology enabling test cases on 20nm process and beyond. This hit will change the game, breaking the wall of technology to give an open access to the R&D international design community and a unique opportunity to touch silicon with innovative designs.”

“CMP is very proud to offer such a very advanced process to the community. Such a process will allow researchers and engineers to experiment with the benefits of SOI on an advanced technology node,” said Bernard Courtois, head of CMP.

CEA-Leti has been involved with FDSOI R&D for a number of years and has developed internally both an advanced High-K/Metal Gate FDSOI process and a number of specific design and simulation tools based on industry-standard design-flow packages.

FDSOI technology presents key advantages over conventional bulk technology for future nodes. The electrostatic integrity of the transistors is ensured by the thinness of the body without the need for extra litho steps, like in the case of FinFETs, or of channel doping. The consequence is a planar technology that exhibits at the same time excellent short channel behavior and significant improvement of the variability as shown in a number of recent papers.

The basis of the technology offer will be the following:
* CMOS transistors with an undoped channel and a silicon film thickness of 6nm
high-k/metal gate stack.
* Single threshold voltage (Vth) n- and pMOSFET with balanced Vth of ±0.4V.
* Associated Design Kit, including SPICE model (Verilog-A language), model cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics.
* Design kit documentation.
* The first run is scheduled to be launched in September 2011. All details will be available on the CMP website.