H3C selects NetLogic's 10 Gigabit Ethernet PHYs for S12500 and S9500E series core switches

SANTA CLARA, USA: NetLogic Microsystems Inc. announced that H3C Technologies, a subsidiary of Hewlett-Packard Company and a leading global provider of IP-based products and solutions, has selected NetLogic Microsystems’ AEL2020 dual-channel 10 Gigabit Ethernet (10GE) PHY device for both its S12500 and S9500E series core switches.

The H3C S12500 is a series of core switches designed for use in next-generation data centers. Employing an advanced CLOS multi-fabric multi-plane switching fabric, the S12500 supports sustainable bandwidth upgrade. Developed on a 100GE platform, the S12500 supports the 40GE and 100GE standards and can provide 576 10GE ports for high-density 10GE applications.

It addresses the burst traffic requirement of next-generation data centers and adopts the distributed ingress buffering technology to provide 200 ms data buffering capability, which meets the burst traffic requirements of data center networks and high-performance computing networks.

In order to meet the high-reliability, high-availability, and virtualization requirements of data center networks, the S12500 adopts the innovative Intelligent Resilient Framework 2 (IRF2) design to virtualize multiple high-end devices as one logical device.

The H3C S9500E is a series of new-generation core routing switches developed for use in the core layer of campus networks and data centers. While providing large-capacity and high-performance L2/L3 switching, the S9500E further integrates intelligent features such as hardware-based IPv6 forwarding, hardware-based MPLS forwarding, security and flow analysis.

It can be used to construct a basic network platform on which integrated services can be provided in campus networks and data centers. Adopting innovative hardware design, the S9500E provides a distributed high-performance hardware forwarding mechanism and large-capacity Crossbar non-blocking switching technology to guarantee high processing performance and flexible system scalability.

The advanced S12500 and S9500E core switching designs include NetLogic Microsystems’ AEL2020 10GE PHY device that integrates a dual-channel SerDes transceiver with an integrated Electronic Dispersion Compensation (EDC) engine that is compliant with IEEE 802.3aq specifications.

The AEL2020 10GE PHY device integrates an advanced transmit pre-emphasis and receive equalization to deliver the industry’s lowest latency, lowest jitter and best-in-class power consumption.

The AEL2020 device’s small 225 pin, 16x16mm BGA package (1mm ball pitch) size makes it one of the industry’s smallest dual-port integrated EDC/PHY/SerDes and is ideal for use in dense applications, such as with SFP+ modules for 10GBASE-LRM applications, 10GBASE-SR and –LR applications, direct-attached copper SFP+ applications and Data Center Ethernet applications.

“NetLogic Microsystems’ 10GE PHY products deliver the high performance, low latency and low power consumption to enable us to develop industry-leading switches for enterprise and data center networks,” said Steven Yoe, vice president of engineering at H3C Technologies, a wholly owned subsidiary of Hewlett-Packard. “We are pleased to collaborate with technology leaders and innovators like NetLogic Microsystems to continue to develop highly competitive, best-in-class system solutions.”

“We are proud to have been selected for the highest performance switches in HP/H3C’s product lineup,” said Stefanos Sidiropoulos, vice president of Physical Layer Products at NetLogic Microsystems. “The strong and continued design win momentum of our 10/40/100GE PHY product family is a testament to both our market and technical leadership in delivering highly differentiated solutions for next-generation data center and core networks.”

NetLogic Microsystems’ AEL2020 device provides full Physical Coding Sublayer (PCS), PMA, and XGXS sub-layer functionality through the consolidation of the receiver and transmitter PHY functions on a single chip along with the integration of encode/decode/alignment logic, FIFOs, on-chip clock generation and data recovery, multiple loop-back features, PRBS Ethernet frame generation and verification for both the line- and the system-side.

The AEL2020 device also features Packet, Pseudo Random Binary Sequence (PRBS), CJPAT and CRPAT generators and checkers; Management Data Input/Output (MDIO), Joint Test Action Group (JTAG), SDA/SCL physical interfaces, and is available in RoHS 5/6 and RoHS 6/6 package options.