Accellera announces election of officers for 2010/11

NAPA, USA: Accellera , the electronics industry organization focused on the creation and adoption of Electronic Design Automation (EDA) standards and Intellectual Property (IP) standards, announced that its Board of Directors has elected officers for its 2010/11 membership year.

Shishpal Rawat, Director of Business Enabling Programs with the Design Technology Solutions group, Intel, was elected Chair. Dennis Brophy, Director of Strategic Business Development, Mentor Graphics, was re-elected Vice-Chair. Stan Krolikoski, Group Director, Standards and Interoperability, Cadence Design Systems, and Yatin Trivedi, Director, Standards and Interoperability Programs, Synopsys, were re-elected Secretary and Treasurer, respectively.

"Accellera is a very significant player in developing EDA and IP standards that drive interoperability and productivity across multiple design domains,” remarked Shishpal Rawat, Accellera chair. “I am honored to be elected chair of Accellera and lead a group that defines and delivers standards that benefit the global electronics industry.”

Accellera’s Chair
Shishpal Rawat, Director of Business Enabling Programs with Design Technology Solutions group at Intel, oversees Intel’s research investments in academia, collaboration with industry standards bodies and collaborates with Intel Capital on EDA equity investments.

He has been at Intel for 22 years and has held a variety of Design and CAD management positions. He holds M.S. and Ph.D. degrees in Computer Science from Pennsylvania State University, University Park, and a B. Tech. degree in Electrical Engineering from Indian Institute of Technology, Kanpur, India.

Accellera standards
Accellera is aligned on the path to create formal standards through the IEEE and currently has seven standardization subcommittees operating. These include: Interface Technical Committee (ITC), IPtagging ,Open Verification Library (OVL), SystemRDL (Register Description Language), Unified Coverage Interoperability (UCI), Verification IP (VIP) and Verilog Analog/Mixed Signal (AMS).

IEEE Standards based on Accellera’s technical activities include:
* VHDL or IEEE Std.1076.
* Open Compression Interface (OCI) or IEEE Std. 1450.6.1.
* Delay and Power Calculation System (DPCS) or IEEE Std. 1481.
* Standard Delay Format (SDF) or IEEE Std. 1497.
* IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows, or IEEE Std. 1685.
* SystemVerilog or IEEE Std.1800.
* Unified Power Format (UPF) or IEEE Std. 1801.
* Property Specification Language (PSL) or IEEE Std.1850.

Accellera corporate members include: ARM Ltd; Cadence Design Systems; Freescale Semiconductor; Intel; Mentor Graphics; Nokia; NXP Semiconductors; Oracle; Qualcomm; SpringSoft; ST Microelectronics; Synopsys; and Texas Instruments.

Associate members include: Aldec; AMD; Atrenta; Cisco Systems; IBM; Jasper Design Automation; Magillem Design Services; Paradigm Works; Verilab; and Xilinx.