WILSONVILLE, USA: Mentor Graphics Corp. announced that Mindtree has become a part of the Questa Vanguard Program (QVP) and adopted an advanced verification flow based on Mentor’s Questa functional verification platform and the Open Verification Methodology (OVM).
The Questa platform and OVM allow Mindtree to leverage the power of SystemVerilog to deliver high-quality verification IP.
The Questa platform and OVM ease the path to the extensive features of SystemVerilog enabling the Mindtree team to take advantage of such things as constrained randomization, assertions, and functional coverage. Mindtree used OVM to establish a functional verification process supporting automatic testbench creation, reuse, and first-pass success.
“Mentor QVP partnership and support has helped Mindtree in developing OVM- compliant SystemVerilog verification components to expedite the verification cycle and also give access to the Universal Verification Methodology Early Adopter (UVM EA) kit to partners that will provide an edge in adopting the new methodology,” said Venugopal N, program director, Mindtree Ltd. “We chose Questa and the OVM because we saw that Questa, in terms of maturity and completeness of the SystemVerilog implementation, is in a strong position.”
“Mentor Graphics has a long history of fostering win-win partnerships that offer mutual customer benefit,” said Dennis Brophy, director of strategic business development, Mentor Graphics Corporation. “The combination of the Questa functional verification platform and the OVM, with Mindtree’s expertise, enables the high level of productivity required by design teams to be successful.”
Questa functional verification platform
The Questa functional verification platform combines high performance and high capacity with the most comprehensive verification capabilities in the industry.
Assertion-based Verification (ABV), intelligent testbench automation, Multi-view Verification Components (MVCs), and Coverage-driven Verification (CDV) are supported natively by the Questa platform’s high-performance assertion engine; a modern, high-performance constraint solver; and extensive functional coverage features, including verification management leveraging the Unified Coverage Database (UCDB).
Verification of low-power design functionality can be proven in an RTL environment with power-aware functional verification. This full set of advanced verification functionality is enabled by a flexible OVM that delivers unrivaled language and feature support in any design and verification flow.