SAN JOSE, USA: Expanding its FPGA solutions for the surveillance market, Altera Corp. announced the industry's first high-definition (HD), intellectual property (IP) reference design for surveillance cameras on a single FPGA.
This unique solution features Altera's low-cost Cyclone III or Cyclone IV FPGAs and IP from Eyelytics and Apical supporting AltaSens' 1080p60 A3372E3-4T and Aptina's 720p60 MT9M033 HD Wide Dynamic Range (WDR) CMOS image sensors.
The all-in-one solution offers surveillance equipment manufacturers the ability to reduce board space, lower power consumption, increase flexibility and reduce development time compared to previous architectures using traditional digital signal processors and ASSPs.
Traditional digital signal processors and ASSPs don't have the processing power required to accept the large bandwidth of data from 1080p and 720p WDR CMOS sensors (for instance, a full HD raster is 2200x1125 pixels x 16+ bits per pixel x 60 frames per second, resulting in >2 Gbps bandwidth).
Altera's Cyclone series FPGAs deliver the bandwidth and processing performance needed, handling large amounts of data generated by today's HD WDR CMOS image sensors. In previous designs, HD WDR camera systems required FPGAs to perform the "front end" data processing while a digital signal processor or an ASSP handled the "back end" video encoding. Now, all of these chips can be replaced by a single Altera FPGA.
Altera's HD surveillance IP camera reference design functions include:
* Hot pixel removal and WDR sensor demosaic functions.
* A complete Image Signal Processor (ISP): including color pipeline, auto white balance and auto exposure (including exposure mixing for WDR).
* Apical's spatial dynamic range-compression (local tone mapping) algorithm, known as "iridix".
* Apical's 2D noise-reduction algorithm, known as "sinter".
* Eyelytics' H.264 video encoder, capable of 720-line progressive 30 frames-per-second encoding or 1080-line progressive 15 frames-per-second encoding in main profile.
* Altera's Triple-Speed Ethernet MAC IP and Nios II embedded processor cores.
By eliminating the need for digital signal processors or ASSPs and combining all of these functions into one Altera FPGA, designers can take advantage of the cost and power savings with reduced board space. Altera's single-chip solution reduces power consumption by more than 50 percent compared to previous designs.
The bundling of a comprehensive list of IP in this reference design gives designers a head start in camera development, shortening development time by as much as one year. All camera designers have to do is customize the FPGA with their own specific features, such as adding their own software for motion detection, and pan, tilt and zoom control.
"Much like the video display industry, our surveillance customers expect high-quality video images," said Michael Samuelian, director of the industrial and automotive business unit at Altera. "Altera is taking surveillance another step further by delivering a complete single-chip solution that not only addresses the trends from standard definition to high definition, standard CMOS sensors to WDR CMOS sensors, but makes it more cost effective for surveillance-camera designers to produce high-resolution images over an internet protocol network."