Mentor's Tessent YieldInsight improves IC yield through statistical analysis of test failure data

AUSTIN, USA: Mentor Graphics Corp. today announced the new Tessent YieldInsight product, adding to the company’s portfolio of yield analysis solutions for manufacturers of advanced digital ICs.

The new product statistically analyzes large volumes of production test failure diagnosis data produced by the Mentor Graphics Tessent Diagnosis tool (formerly called YieldAssist), helping manufacturers recognize, locate and fix design- and process-related yield problems to improve IC manufacturing quality levels.

“TSMC has been using Mentor Graphics failure diagnosis tools for the past year,” said Shauh-Teh Juang, senior director of Design Infrastructure Marketing at TSMC.

“We have found that Mentor’s unique chain and at-speed diagnosis capabilities accurately diagnose failing die and can effectively pin-point problem areas within the die, even when the problem is internal to a cell, which is very important for physical failure analysis. We look forward to continuing collaboration with Mentor on the new statistical analysis capabilities being announced today.”

“We have been using diagnosis-driven yield analysis flows for years,” said Davide Appello, Design-to-Test Engineering Manager at STMicroelectronics’ Automotive Products Division.

“Using the statistical analysis features of Tessent YieldInsight, we are able to identify yield issues in days, as well as determining the impact of process modifications by carefully examining the failure signatures.”

According to Olivia Riewer, DfX Logic Diagnosis Manager at STMicroelectronics Technology R&D Central CAD & Design Solutions, “We have been validating the effectiveness of Mentor Graphics’ solution for more than one year and the layout-aware diagnosis feature brings much added value. The overall solution fits well into our design and test infrastructure and it is now integrated into our automated flow for volume diagnosis, which is deployed to product groups within STMicroelectronics.”

“Mentor’s yield analysis solution will make a huge impact on our customers’ ability to rapidly ramp their production yield,” said Joseph Sawicki, Vice President and General Manager for the Design-to-Silicon Division at Mentor Graphics.

“For the first time in the industry, we are really closing the design-to-silicon loop by extracting statistical information from silicon test failure data and using it to identify precisely where in the design or manufacturing process we can best impact yield and quality.”

Meeting challenge of systematic yield issues with diagnosis-driven yield analysis
ICs being developed at advanced technology nodes of 65nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise.

Complex interactions between the manufacturing process and inherently more sensitive layout features can cause systematic yield-related issues. IC manufacturers need a yield analysis methodology capable of employing logical design and layout information along with high-volume test failure data.

The Mentor Graphics Tessent solution combines the automated scan test failure collection and diagnosis capabilities in the Tessent Diagnosis tool with advanced statistical analysis and data mining techniques in the new Tessent YieldInsight product.

The Tessent YieldInsight tool brings innovative design-correlated analysis methods that supplement traditional fab-centric yield management systems. In a manner consistent with yield and failure analysis tools, it steps the user through the process of selecting and filtering populations of failing die, grouping die that are failing for similar reasons, and analyzing various aspects of these populations to identify and locate systematic yield loss mechanisms.

Tessent YieldInsight and Tessent Diagnosis are available now.