3D‐IC and TSV interconnects 2009 reports

LYON, FRANCE: Yole Développement updated its analysis related to 3D integration with TSV interconnects. The company has released two new reports that will help the semiconductor industry, as well as its suppliers and customers, to identify remaining challenges and to assess their strategy related to the implementation of 3D TSV “Through Silicon Via” technology to high volume production within the next decade.

Market trends
The continuation of Moore’s law by conventional CMOS scaling is becoming more and more challenging, requiring huge capital investments. 3D Packaging with 3D TSV interconnects provides another path towards the “More than Moore”, with relatively smaller capital investments.

Despite the impact of the economic downturn, 3D integration investments are strategic innovations and have continued. Yole Développement has identified as of today more than 15 different 300mm 3‐D IC pilot lines running or currently being installed world‐wide (within R&D centers, at packaging houses, CMOS foundries or within IDM fabs).

This year, several initiatives of key industry leaders happened such as STMicro for 3D integration in MEMS and CMOS image sensors, Elpida for stacked DRAM memories and Sony with the introduction of Backside illuminated (BSI) technology into its camera sensor products portfolio.

Strong dynamics in MEMS, CMOS image sensors, memory, analog and logic industries continue and will drive adoption of 3D TSVs to high volumes within the next decade. Additionally, new applications such as HB‐LED silicon modules, Solar and Power components are also on the point to catch the 3D TSV trend and to benefit from this disruptive interconnect technology!

But challenges are still ahead!
Supply chain and infrastructure readiness is the biggest immediate issue Yole Développement has identified for the broad adoption of 3D ICs. As many scenarios are possible for the implementation of 3D TSV interconnects (via first/via middle/via last/via after bonding) a big question at the moment is WHO will take the risk to invest and will have the ownership of the realization of the different 3D TSV process steps (to be implemented in front‐end, mid‐end, back‐end)?

Even though equipment and material suppliers propose serious industrial solutions for the manufacturing of TSV’s, it is not clear yet which company profile is best suited to address this rising demand: as a typical mid‐end technology which addresses packaging concerns using front‐end type of equipment, the question does not seem answered yet if integrated device manufacturers, subcontracting foundries or Open Source Assembly and Test companies (OSAT’s) will seize this opportunity.

Depending on how the supply chain will evolve, different TSV technologies may prevail. As a result, the consulting and market research company has decided to release this year one new report called “3D TSV Technologies & Scenarios: Via First or Via Last?”.

The analysis is focusing on the deeper understanding of the rationale behind these strategic technology choices to be made. It puts into perspective who is doing what at the moment, what alliances are being formed, which technology choices have already been made and for which applications?

I/O standardization between interfaces such as memory to digital layers is also a serious issue that needs to be fixed rapidly. Indeed, 3D integration of memory + logic ICs together is perceived as the next big wave for volume adoption of 3D TSV in the near future.

Multiple applications are targeted, including CPU, GPU, DSP, FPGA, ASICS and basebands ICs that will be used in future cell phones, supercomputers, network/storage systems, notebooks, automotive and medical processing units among others.

Thermal management and reliability could also reduce 3D ICs application space in the longer run. However, different solutions are currently underway in response to this possible challenge.

More silicon value is moving to the package!
3D interposers, based on either silicon or glass tend to emerge as a serious alternative to traditional package substrates such organic PCB laminates or ceramic technologies for the sake of extreme miniaturization and performance.

The first “true 3D” silicon interposers are not expected in production before 2012‐2013, though. Specific features like the integration of mature logic and analog functions such as IPD (integrated passive devices) will be key components in the effective commercialization of 3D interposers in the short term. 3D integration opens up a possible supply chain value change to all players as more and more value is now moving to the package in general.

IDMs, fabless players, wafer foundries, packaging houses, MEMS players, substrate and PCB suppliers are all poised to take on more value in this new era if they all prepare for the investments it requires.

It is also astonishing to notice the rapid evolution of 3D thinking within the IC community: two years ago, the big unceasing question was “Why 3D?” Today, moving forward with the concrete implementation of the technology, questions are now “When 3D?” and “How 3D?”.

“It is terrific to realize that in less than one decade from now, looking back at what has happened, we will be wondering “Why 2D?””, explained Jérôme Baron, Principal Analyst at Yole Developpement.