SANTA CLARA, USA: Demonstrating the widespread adoption of its popular SLEC System HLS (High Level Synthesis) tool, Calypto Design Systems, a leader in sequential analysis technology, announced that Casio will incorporate SLEC into its electronic system level (ESL) design flow for new digital camera designs.
Casio plans to pair Calypto’s formal verification tool with the Cadence Design Systems' C-to-Silicon Compiler to improve design efficiency and reduce time-to-tomarket for its digital cameras.
The combination of the Cadence and Calypto technologies allows engineers to work at a much higher level of abstraction, engaging in true ESL design. Using C-to-Silicon Compiler, Casio will automatically generate synthesizable register transfer level (RTL) code from SystemC code that can then be comprehensively verified by SLEC SystemHLS.
The automated ESL flow will allow Casio to run multiple “what if” scenarios and evaluate different design implementations to ensure that the final product delivers the best combination of cost and performance possible while ensuring functional correctness.
“Digital camera design has become increasingly sophisticated, and gate complexity is now 10 times what it was just three years ago,” said Kazuyuki Kurosawa, section manager of Digital Camera Product Unit, Casio. “Before implementing an automated unified ESL flow, we were forced to engage in time-consuming RTL hand coding and verification through RTL simulation regressions to generate and verify our design –– a process that consumed valuable engineering resources and limited our ability to innovate. By automating these two complex steps, Calypto and Cadence allow us to reduce design time and focus our resources on bringing true differentiation to our products.”
“There is an ongoing effort for design teams to find ways to increase productivity and achieve faster time-to-market,” said Tom Sandoval, CEO Calypto Design Systems. “Cadence C-to-Silicon Compiler and its integration with Calypto’s SLEC SystemHLS are proven to meet this demand, allowing designers to use their valuable design time for innovation, rather than tedious simulation and coding.”
Cadence's C-to-Silicon Compiler bridges the gap between RTL design and system-level models, usually written in C/C++ and SystemC. Fulfilling the industry requirement for formal equivalence checking, designers can then perform comprehensive functional verification using the Calypto SLEC System-HLS to formally verify equivalence between SystemC ESL models and RTL implementations.
By integrating their technologies, Cadence and Calypto deliver a fully automated system-level design solution that dramatically increases designer productivity.
“Our customers now have a best-in-class comprehensive solution for system level design and verification,” said Michael McNamara, vice president and general manager of the Systems Software Group at Cadence Design Systems. “The tight integration between Calypto’s SLEC SystemHLS and Cadence C-to-Silicon Compiler gives our customers an optimal flow that is rapidly becoming a standard approach for advanced SoC design.”