Si2 to host low power coalition workshop at DAC 2009

AUSTIN, USA: The Silicon Integration Initiative (Si2) announced the Low Power Coalition workshop being hosted at the Design Automation Conference (DAC) show to be held at the Moscone Convention Center in San Francisco, CA, from July 26-31, 2009.

The “Low Power Coalition Workshop – Advances in Low Power Design throughout the design flow” will be held on July 26, from 1PM – 4:30PM in Room 130 in the Moscone Convention Center. In consideration of today’s economic conditions, Si2 is pleased to offer this workshop free of charge. Attendees can register at the DAC website: http://www.dac.com/46th/onlinereg.html

The Low Power Coalition (LPC) of Si2 has defined and published a power-aware reference flow that is recommended to the industry, including the power closure points and information available throughout the flow, from Electronic System Level (ESL) through implementation. This flow will be discussed.

To aid in automating many of the steps along the tool chain, a draft power intent data model and associated Application Procedural Interface (API) are being defined that will work seamlessly with the OpenAccess API and information model, and we will provide an early view of this data model and API.

In addition, enhancements have been made to extend the Common Power Format (CPF), an Si2 standard first released as v1.0 in March 2007 and v1.1 in September, 2008. The current status and future direction of the format will be presented, including progress since the last Low Power Workshop at DAC 2008, goals and plans for interoperability with P1801, and end-user experiences with the technology developed and implemented so far.

A panel will discuss “What’s Next,” to discuss areas in which power flows, models, and formats might be extended to support additional power-aware design approaches, such as adaptive methods, asynchronous methods, etc. A selection of advanced tools that have been developed by some of the EDA companies to improve power-aware design will also be presented.

Program
Introduction to the Low Power Coalition:
Gill Watt, AMD – Chairman of the LPC
Low Power Design Interoperability Requirements: Looking Ahead!
Qi Wang, Cadence, Vice Chair of the LPC Technical Steering Group
LPC Modeling Requirements for a Low Power Flow
Jerry Frenkil, Sequence, Member, LPC Modeling Working Group
LPC Data Model and API
Judith Richardson, AMD, Member, Data Model and API WG
End-user Adoption Aids
Jake Buurma, Si2
EDA Tool Developers for Low Power
Steve Carlson, Cadence Design Systems
Jerry Frenkil, Sequence Design, Inc.
Kiran Vittal, Atrenta, Inc.
Anmol Mathur, Calypto Design Systems, Inc.

Panel Discussion (all presenters)
“What’s next in Low Power”