Verific's tools deliver RTL language support for Xilinx ISE Design Suite

ALAMEDA, USA: Verific Design Automation announced that its register transfer level (RTL) front ends have been licensed by Xilinx (www.xilinx.com) for the latest version of ISE® Design Suite, equipping Xilinx customers with robust RTL language support for the new Virtex 6 and Spartan 6 FPGAs.

Xilinx has integrated Verific’s de facto standard Verilog and VHDL parsers, analyzers and elaborators to provide a common, proven and reliable RTL front end for its synthesis, simulation and design entry products.

ISE Design Suite 11, the latest release of the industry-leading environment for FPGA design, delivers a new generation of complete, domain-specific development environments for logic design, DSP design, embedded design and complete system level design.

“Verific has been an exceptional technology partner with a team whose expertise we value,” notes Dan Gibbons, Xilinx’s senior director for Interactive Design Tools. “Verific has delivered high-quality RTL front-end software to help us differentiate ISE Design Suite’s superior capabilities and benefits and allow us to focus on our core competencies.”

Verific’s software serves as the front end to electronic design automation (EDA) and FPGA tools such as Xilinx’s ISE Design Suite to analyze, verify, synthesize and modify designs for the past 10 years. Its products are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and comes with support and maintenance.