ARM uses eASIC devices to validate Cortex-A9 MPCore multicore processor-based devices

SANTA CLARA, USA: eASIC Corp. a provider of low up-front development cost NEW ASICs, announced that ARM has successfully validated its next-generation Cortex-A9 MPCore multicore processor using eASIC’s Nextreme NEW ASICs.

With Nextreme, ARM was able to perform at speed verification with significantly higher performance, and lower development cost compared to the high-end FPGA solution that was previously used.

The Cortex-A9 MPCore multicore processor is the latest in a strong portfolio of CPU cores now being designed-in across wireless, networking, consumer and home applications.

The processor core integrates proven ARM® MPCore technology along with further enhancements to simplify and broaden the adoption of multi-core solutions and extending peak performance to unprecedented levels, while reducing power consumption at the processor and system level. Nextreme’s fast logic fabric, dedicated memories and single Via-based interconnect were able to provide the performance required to fully test the new Cortex-A9 processor.

“We were able to develop our eASIC device in a reduced time and cost of a standard cell ASIC and with development costs that were even lower than an FPGA approach and the eASIC device worked right first time on our PBX-A9 validation and development board,” said John Goodacre, Director, Program Management of ARM Processor Division. “We see the 90nm Nextreme eASIC technology as a very cost effective way of validating and demonstrating new products to our customer base and getting them to market much earlier.”

“In addition to the growing acceptance from traditional FPGA and ASIC users, we also see considerable interest from conventional ASSP companies and IP providers who see eASIC technology as a way of developing at speed verification solutions that can even be taken into volume production,” said Jasbinder Bhoot, Vice President of Marketing, eASIC Corporation. “As process geometries shrink, eASIC will become one of the few practical solutions to perform at speed verification of IP cores and ASSPs.”