ASML, KLA-Tencor, and Lam Research to benefit from 450mm wafer transition

Dr. Robert N. Castellano, The Information Network

USA: The semiconductor industry has been increasing the size of wafers about every 10 years. In 2000, semiconductor device manufacturers migrated from 200 mm substrates to 300 mm substrates due to technological advances and manufacturing cost advantages.

300 mm wafers provide more than 2.25 times as many die per wafer, and offer significant economies of scale in the manufacturing process. Approximately 96 percent of 2012 net orders for wafer fabrication equipment were for 300 mm manufacturing systems. The next planned wafer size increase is expected to be up to 450 mm substrates.

Increases in wafer sizes have been a natural evolution and manufacturing efficiency improvement for the semiconductor industry for decades, as shown in the figure below.

The table below shows the impact of the conversion from 300mm to 450mm technology on several processing parameters.

Shown in the figure below, this illustrates the special dual “S-curve” timing required when a new wafer generation is being introduced, which was modeled after the experience with the 300 mm wafer generation ramp around 2000.

The ITRS has proposed a revision in the timing targets for the 450 mm generation semiconductor manufacturing and foundry pilot lines, which are now delayed about 2 years (2015–16, versus the previous 2013-14 target made by the ITRS in 2009).

By 2015-16, Intel Corp (INTC), Globalfoundries Inc., Samsung Electronics Co. Ltd. and Taiwan Semiconductor Manufacturing Co. Ltd. (TSM) will have 450mm wafer fabs constructed and equipment installed.  While these are only a handful of fabs so far, they represented 34% of the revenues of the entire semiconductor industry in 2012, as shown in the table below.

What’s in store for equipment suppliers?
Market share is a key determinant in what semiconductor equipment supplier will reap the benefits of sales to customers that represent a third of the total industry.  And this is important.  A vendor will not have a 450mm position unless it has a 300mm position.  In other words, the slate will not be clean going from 300mm to 450mm as far as purchases are determined.

Semiconductor manufacturers will purchase 450mm equipment from the same equipment supplier that sold them 3000mm equipment.  For an equipment company to become the supplier of record to a customer, it needs to execute well, providing best-of-breed equipment and technology.  Unless that company self-destructs, the execution they focused on to sell 300mm equipment will carry over to 450mm.

So who’s to gain in this transition?

ASML (ASML) is an easy one. Besides the fact that they dominate the lithography market with an 84 percent share (see chart below), they also dominate the EUV (extended UV) market with a 100 percent share. ASML announced they would port their EUV to 450mm only.  Intel invested $4.1 billion in ASML, as part of an effort to raise the overall confidence level in EUV and the 450mm wafer transition. TSMC and Samsung also recently invested in the Dutch-based lithography giant for similar reasons.

KLA Tencor (KLAC) dominates the process control market with tools for semiconductor inspection and metrology (measurement) and will be another winner in the 450mm transition. KLA-Tencor holds a 50 percent market share, and that share has been growing worldwide, as shown in the chart below.

Hitachi High-Tec’s process control revenue grew 16.6 percent in 2012 and will be a winner in the 450mm transition.  Hitachi purchased SII Technologies in 2013, which recorder revenues of $90 million in 2012, further escalating Hitachi’s revenues in 2013.

Applied Materials (AMAT) made claim that they gained share against KLAC in 2012, but this is not the case according to our analysis.  Applied has been hyping its process control sector of late, perhaps in response, according to rumors mind you, to the fact the now president, Gary Dickerson, was turned down for the post of CEO of KLAC when he worked there, and then resigned to become CEO of Varian Semiconductor, before being hired by Applied last year.

Based on analyzing the semiconductor equipment market for 27 years, I see erosion in Applied’s execution.  Many of the top executives left the company last year and the vacuum was filled by ex-Varian Semiconductor employees from their misguided $4.7 billion acquisition of the company in 2011.

Lam Research (LRCX) dominates the plasma etch market with nearly a 50 percent share, as shown in the chart below. If we go back to 2000, Applied Materials had led the market with a 36.6 percent share and Lam held only a 26.3 percent share. In the following 12 years, Applied’s share dropped to 27.6 percent while Lam’s increased to 48.3 percent.

Lam Research will be another winner in the 450mm transition. The company is a leading capital equipment supplier to the largest memory manufacturers including Samsung, Toshiba and Micron (MU) and also the key supplier to TSMC.

More importantly Lam recently secured a key etch win with Intel, long a stronghold for AMAT.  Lam acquired Novellus last year. Novellus went head-to-head in competition with Applied Materials in the deposition market, and there had been constant speculation that the re-badging of Novellus hardware by Lam will find its way into Intel.  It appears this may now be the case, Lam’s etch and deposition wools will share a common platform, and it will drive strong sales in Intel’s 14nm build-out.

The semiconductor equipment industry is dynamic and things change. For example, in the metal CVD market in 2000 for example, Applied led the market with a 70.6 percent share compared to 17.1 percent for Novellus. In 2011, Novellus claimed a 64 percent share to Applied’s 17.2 percent.

ST reveals new technology platform for RF front end of wireless devices

SWITZERLAND: Booming demand for faster wireless broadband connections is calling for increasingly complex circuitry inside devices such as smartphones and tablets.

STMicroelectronics is addressing that demand by perfecting an advanced component process technology specifically optimized to increase performance and reduce the size of the RF (radio frequency) front-end of mobile devices.

In wireless devices, the RF front-end circuit is typically built using individual amplifiers, switches and tuners. As new high-speed standards such as 4G mobile and Wi-Fi (IEEE 802.11ac) use multiple frequency bands to increase data throughput, the latest equipment requires additional front-end circuitry.

While current 3G phones use up to five frequency bands, the 3GPP standards for next-generation 4G LTE support up to 40 bands. Conventional separate components dramatically increase overall size whereas ST's new manufacturing process, known as H9SOI_FEM, allows production of complete integrated front-end modules.

This process is an evolution of the H9SOI Silicon-on-Insulator process; a groundbreaking technology introduced by ST in 2008 and subsequently used by customers to produce more than 400 million RF switches for mobile phones and Wi-Fi applications.

Building on that experience, ST has optimized H9SOI for creating integrated front-end modules, resulting in today's announcement of H9SOI_FEM offering the industry's best figure of merit for antenna switch and antenna tuning devices with Ron x Coff at 207fs. ST has also invested to ensure suitable manufacturing capacity for even the most demanding of customers.

From a commercial point of view, smartphones featuring high-speed multi-band wireless are driving booming demand for RF front-end components, particularly as integrated modules. The number of RF devices in a smartphone is roughly three times the number in an entry-level 2G/3G phone, while smartphone shipments are currently over one billion units annually and growing at around 30 percent according to analysis by Prismark.

Additionally OEMs require suppliers to provide smaller, thinner components with higher power efficiency. ST sees opportunities for discrete components, as well as integrated power-amplifier/switch and power-amplifier/switch/tuner modules based on its new best-in-class H9SOI_FEM process.

"The H9SOI_FEM dedicated process enables our customers to develop state of the art front-end modules that are half the size or smaller compared to today's front-end solutions," said Flavio Benetti, GM of the Mixed Process Division of STMicroelectronics. "Moreover, we have achieved a simplified process flow to enable extremely short overall lead-times and supply flexibility, which are crucial for end customers in this market."

ST is now ready to start working with customers on new designs using H9SOI_FEM. Volume ramp-up is expected by the end of this year.

ZEISS launches photomask repair tool MeRiT HR II

GERMANY: The new generation system MeRiT HR II from ZEISS offers a significantly higher degree of automation and increased flexibility in the repair of transparent and opaque defects.

Any defect geometry on all known as well as new mask types and materials can be processed: Binary, OMOG, HD MoSi and EUV. The technical specifications of the MeRiT® HR II match to the industry roadmap and sharp market requirements.

The redesigned tool includes a sound automation package which enables a new level of automation with optimized repair flow. After a short setup routine the processes are able to seamlessly repair numerous defects without the need for human interaction. A higher throughput due to lower idling time is also offered. In case of any doubt a security interlock consults the operator who can intervene when necessary.

“The significantly improved automation level of the new MeRiT HR II frees up precious operator time. Furthermore the combination of automation and manual repair provides an increased flexibility. Altogether the new system has its finger on the pulse as it includes the most relevant requirements mask shops have for repairing all kinds of photomask types in a very short time.” states Dr. Oliver Kienzle, head of the ZEISS strategic business unit Semiconductor Metrology Systems who develops and sells the MeRiT HR II.

DRAM market grows up; industry’s newfound maturity yields growth amid adversity

USA: It’s said that adversity breeds character—and that certainly seems to be the case for the global market for DRAM (dynamic random access memory). This market has achieved some maturity in the face of daunting challenges, allowing the industry to achieve a balance between supply and demand this year.

After DRAM wafer output peaked in 2008 at 16.4 million 300-millimeter-equivalent wafers, production is expected to decline by 24 percent to 13.0 million this year, according to an IHS DRAM Dynamics Market Brief.

The projected cut will be the second straight year of deliberate downsizing following an 8 percent drop-off last year. This year’s output is expected to be slashed by 5 percent compared to 2012, as shown in the attached figure.

Curtailing DRAM capacity is a positive move for the industry, resulting in a gradual normalization between supply and demand for DRAM. The industry is now believed to be perhaps slightly undersized relative to demand moving forward because of the intentional slash in output, and DRAM pricing can continue to remain firm if production remains slightly behind demand.

DRAM revenue in the first quarter rose to its highest level in nearly two years, thanks to a jump in commodity prices spurred by demand from the server PC and mobile PC segments. Pricing for the bellwether 4-gigabyte DDR3 module rose to $23 in March, up from $16 in December, an unusually large increase.

“The DRAM industry has struggled with major challenges in recent years, including chronic oversupply and slowing demand from its main market, the PC business,” said Mike Howard, senior principal analyst for DRAM and memory at IHS. “This has led to continued weak pricing, financial losses and market revenue declines. However, the DRAM industry has entered a more mature state, enacting structural changes that will allow it to grow even in challenging market conditions.”

DRAM market enters the post-PC era
In one major change, the DRAM market is adjusting to the fact that demand is diversifying away from PCs alone to servers and mobile devices.

Nearly 65 percent of all DRAM bit shipments went to a desktop or laptop 10 years ago, but that figure is less than 50 percent today and will fall further to south of 40 percent by the end of next year.

Meanwhile, servers and mobile gadgets like smartphones and tablets command an increasing share of DRAM bit shipments.

The overall result is that the travails of one segment—like the embattled PC space—won’t be able to disrupt the entire market, lacking the size and critical mass to do so. The server and mobile segments also help by using more specialized products that require a more involved design-in process, thereby reducing the commodity nature of the DRAM that the segments consume.

DRAM downsizing
In another change that has benefited the hypercompetitive industry, a number of DRAM suppliers in the past few years have either reduced their presence or have altogether exited the market.

The Taiwanese are no longer the powerhouse suppliers they used to be, while notable DRAM makers Qimonda of Germany and Elpida Memory of Japan have gone bankrupt and have been bought out by other players.

By the end of this year, only three DRAM manufacturers will remain—Samsung and SK Hynix of South Korea, and U.S.-based Micron Technology. With fewer entities to influence the market, a more conservative approach toward capacity expansion is expected, and more stable growth can follow.

Process deceleration
A final factor helping the global DRAM business is the slower pace of advancement in DRAM manufacturing processes. Each new generation of DRAM manufacturing technology is now taking longer to arrive.

The engineering challenges associated with shrinking DRAM size smaller than 30 nanometer— and eventually below 20 nanometer—are considerable.

The slowing cadence in manufacturing process evolution is resulting in slower bit growth, which is keeping supply in better balance with demand.

Challenge of constant undersupply
While the current state of intermittent undersupply is favorable to the industry, a state of persistent undersupply could backfire and prove harmful. Large, obstinate supply shortfalls will result in broader adoption of competing technologies as devices seek alternatives besides DRAM, and possible regulatory intervention could occur over perceived anticompetitive concerns.

Clearly then, it is in the best interest of the industry to manage supply so that it more closely matches demand—and thereby control its own future. Next year, manufacturers will need to seriously look at options for expanding manufacturing capacity to accommodate demand. But properly managed, DRAM prospects can remain healthy, IHS believes.

Mentor Graphics accelerates verification with emulation-ready verification IP for MIPI products

USA: Mentor Graphics Corp. announced MIPI-protocol verification IP (VIP) for use with its latest-generation Veloce hardware emulation platform.

This allows engineers to exhaustively stress test a device-under-test (DUT) that includes one or more MIPI protocol interfaces on their SoC, and run verification cycles at orders of magnitude faster than simulation.

The MIPI VIP enables the use of stimuli generated by modern simulation testbenches, including SystemVerilog/UVM, and SystemC-based environments, and applies them to a MIPI-based, design-under-test (DUT) running in the Veloce emulator. Since the connection between the testbench and the VIP is at a transaction-level rather than signal interface, a high level of performance is delivered.

The new VIP supports users of the MIPI camera and display-based protocols, CSI and DSI, and is compatible with the Questa® functional verification platform as well as the Veloce hardware emulation platform.

OCZ achieves first-pass silicon success with DesignWare IP and Synopsys professional services

USA: Synopsys Inc. announced that OCZ Technology Group Inc. (OCZ) has achieved first-pass silicon success for its NAND flash Vector SSD using Synopsys' DesignWare DDR2/3-Lite PHY, Embedded Memories, STAR Memory System solution and Professional Services.

Choosing Synopsys technology and services enabled OCZ to accelerate the completion of their project, meet their performance requirements and achieve first-pass silicon success with a production-ready design.

Targeting the high-end consumer market, the OCZ Vector SSD was designed to deliver superior sustained performance through its new, high-performance Indilinx Barefoot 3 flash controller supporting the SATA-3 protocol. For OCZ's design team to effectively focus on developing the Barefoot 3 controller while meeting their broader design goals, they needed reliable, silicon-proven IP, an integrated design flow and design expertise to augment their own. OCZ selected Synopsys' high-performance and area-optimized DDR2/3 PHY, embedded SRAMs and integrated memory test and repair solution.

To mitigate risks and accelerate the implementation process, OCZ deployed the Lynx Design System, an integrated RTL-to-GDSII block- and chip-level design environment with unique visualization capabilities for efficient design exploration and reporting of design status and trends.  In addition, Synopsys' design consultants worked closely with OCZ's engineers throughout the implementation of their chip, delivering expertise and advanced methodologies in IP integration, physical design, and physical verification that enabled OCZ to complete their implementation in less than six months.

"We were very focused on reducing schedule risk, which made it imperative that we partner with an established vendor like Synopsys that had the proven portfolio of IP, design flows and services that we needed," said Brian McMath, technical director at OCZ. "Of particular value to us was the DDR3 PHY integration expertise Synopsys Professional Services brought to the project. The combination of Synopsys' proven DesignWare IP, experienced design consultants and tapeout-proven Lynx Design System made it possible for us to achieve our performance goals while saving an estimated two months of schedule time.  The net result of our collaboration was that we got our product to market much faster than if we had done it on our own."

"Companies such as OCZ who develop innovative electronic products need design solutions they can rely on to mitigate project risks and meet tight time-to-market windows," said John Koeter, VP of marketing for IP and systems at Synopsys. "Synopsys invests heavily in developing high-quality DesignWare IP as well as providing tightly correlated tool flows and experienced design consultants so our customers can focus on the aspects of their design that differentiate them from the competition."

Micron to enjoy growth in three major product lines thanks to merger with Elpida and industry restructuring

TAIWAN: According to DRAMeXchange , a research division of Trendforce , thanks in large part to the rising spot prices of DRAM (which has grown twofold since last November), the spot market price of DDR3 2Gb has a good chance of approaching $2 in the upcoming periods.

The profits shown on Micron’s recent June 19th financial report are, in many ways, a reasonable indication of the positive trends that are currently emerging in the DRAM industry.

Observing from the market perspective, with Nanya officially transitioning into a specialty DRAM company and handing over its manufacturing responsibilities of Inotera to Micron, the US based chip maker can be said to be in a relatively strong position to increase its entire PC and server DRAM production. In the past, PC DRAM had been known to be largely unprofitable due to the intense competitions that took place within the market.

The losses incurred in the industry had been so severe that, at one point, various DRAM manufacturers felt the urge to switch to the more profitable product lines. The DRAM industry’s financial woes would not change for the better until early 2013, when the production of PC DRAM shrunk and led to a continuously declining supply bit growth.

At present, both Samsung and SK Hynix are actively lowering their PC DRAM output in favor of manufacturing mobile and server DRAM. The decision is in many ways largely beneficial to Micron, whose PC DRAM production ratio is almost 50 percent. With regards to the second half of the year, given that Micron's and Elpida's merger process is set to complete during Q3 (a process which would in effect help to increase the wafer production volumes from 190K to 370K), it is reasonable to expect the new Micron group's presence in the mobile DRAM market to increase.

As the DRAM market moves further towards an oligopoly, the company is expected to be able to pose legitimate challenges to both of the aforementioned Korean DRAM manufacturers.

Looking at the NAND Flash industry, given that the supplies in the NAND Flash market are being regulated more tightly this year, and considering how more and more manufacturers are transitioning to system products as a means to offset the weak sales effects in retail market, the contract prices in the NAND Flash market have, for the most part, remained flat throughout Q2 (from April to June).

The severe oversupply situation in 2H12, it should be noted, has also experienced a notable improvement this year. With the manufacturing costs being lowered, Micron has continued its efforts to migrate from the 25nm processes to the 20nm processes, and is beginning to place a greater amount of emphasis on the more profitable 20nm-class NAND Flash products.

In the second quarter, Micron's 20nm production proportion has officially surpassed 50 percent. As the manufacturing costs of making the 20nm products drop below those of the 25nm products, there is a chance for the US based chip maker to begin emerging as a more effective cost leader within the industry. Micron's NAND Flash production capacity, as of this moment, is at 180 thousand. Considering that the company's Tech plant in Singapore has been allocating production capacity from DRAM to NAND Flash, it is likely that in Q4, the number of the NAND Flash output will increase to 200 thousand.  

In the event that Micron sticks to its original plan of manufacturing embedded-type products, it is predicted that the chip maker will not only be able to secure the market share it already owns for SSD and specialty Flash products, but that it will also exert a noticeably greater impact on the eMMC and eMCP markets during 2H13. Because of this, we believe that the revenue of the NSG department will remain stable, and that the performances of the ESG and WSG departments will help provide a further boost to Micron's future NAND Flash revenue (given the increased use of NAND Flash in embedded applications as well as mobile devices).

Thanks to the merger with Elpida, PC DRAM, mobile DRAM, and NAND Flash are all expected to be Micron's major product lines. As the use of the 2Xnm processes intended for DRAM products increases in the next few quarters, and as the migration towards the 1Xnm NAND Flash process gradually intensifies, there is a good chance that Micron will experience at least a few more stable quarters with good operating margins (whether for DRAM or NAND Flash products).

As long as the market gradually rebounds and Micron continues developing its core technologies, the company is poised to become a big winner in both the DRAM and NAND Flash industry.

TowerJazz to service high volume, commercial infrared markets

USA: TowerJazz, the global specialty foundry leader, will be the wafer manufacturer for infrared sensing and camera devices using its proven specialty process technologies.

In addition to traditional infrared applications, TowerJazz will facilitate expansion into other consumer markets such as gaming, personal security, and application driven platforms, market segments which are already well served by the company.

The advanced CMOS-based process at TowerJazz’s US location is a viable, commercially sustainable foundry offering to support its commercial as well as its aerospace and defense customers.

“This development is a natural fit for TowerJazz. Our leading edge CMOS for custom imaging products and our expertise in bringing specialty processing and MEMS to volume manufacturing fits extremely well with the proven capabilities of our customer,” said David Howard, executive director and fellow, TowerJazz.

Atrenta announces design service alliance network in Israel

ISRAEL: Atrenta Inc. announced an alliance program with several design service providers in Israel.

The goal of the program is to bring the benefits of Atrenta’s SpyGlass RTL platform to a wider range of customers. The terms of the alliance will be managed as part of Atrenta’s SpyLinks partner program.

Design service providers that specialize in everything from FPGAs to leading edge SoCs are part of the program. Organizations that are part of the program include Inomize, Rachip and Veriest Venture. Under the terms of the program, these design service providers will collaborate with Atrenta to develop SpyGlass expertise that can be deployed as part of their service offerings.

Eliminate complicated wireless set up with TI’s new low-cost, easy-to-use NFC solutions in the Internet of Things

USA: Texas Instruments Inc. (TI) continues to deliver new near field communications (NFC) innovations in its broad portfolio of solutions that make entry to NFC development easier and lower cost.

TI introduced the Dynamic NFC Transponder RF430CL330H hardware to enable uncomplicated and inexpensive wireless set up. Also announced today, the NFCLink software is a standard NFC library for the TRF79xx NFC transceiver family to ease NFC development on TI embedded processors.

The new Dynamic NFC Transponder Interface RF430CL330H is low cost, bringing a secure, simplified pairing process for Bluetooth® and Wi-Fi connections to products, such as printers, speakers, headsets, and remote controls, as well as wireless keyboards, mice, switches and sensors. It is the only dynamic NFC tag device designed specifically for NFC connection handover and service interface functions, including host diagnostics and software upgrades.

Streamlining NFC development across TI’s entire embedded processing portfolio, the NFCLink software firmware library, in partnership with Stollman E+V GmbH and Kronegger GmbH, enables developers to quickly and easily create NFC applications for TRF79xx NFC transceivers using TI’s ultra-low-power MSP430 microcontrollers (MCUs), Tiva C Series ARM MCUs and OMAP processors.

Additional TI embedded processor platforms will be supported in the future. NFC applications running on operating systems include point-of-service devices, routers, set-top boxes, automotive infotainment and other various consumer devices.

AMD unveils server strategy and roadmap

USA:  AMD publicly disclosed its strategy and roadmap to recapture market share in enterprise and data center servers by unveiling innovative products that address key technologies and meet the requirements of the fastest-growing data center and cloud computing workloads.

Additionally, AMD revealed details of its 2014 server portfolio including best-in-class Accelerated Processing Units (APUs), two- and four-socket CPUs, and details on what it expects to be the industry's premier ARM server processor. This is on the heels of announcing the general availability of the AMD Opteron X-Series processor, code named "Kyoto," which dominates the small-core server market on every performance benchmark.

These forthcoming AMD Opteron processors bring important innovations to the rapidly changing compute market, including integrated CPU and GPU compute (APU); high core-count ARM servers for high-density compute in the data center; and substantial improvements in compute per-watt per-dollar and total cost of ownership.

In 2014, AMD will set the bar in power-efficient server compute with the industry's premier ARM server CPU. The 64-bit CPU, code named "Seattle," is based on ARM Cortex-A57 cores and is expected to provide category-leading throughput as well as setting the bar in performance-per-watt.

AMD will also deliver a best-in-class APU, code named "Berlin." "Berlin" is an x86 CPU and APU, based on a new generation of cores named "Steamroller." Designed to double the performance of the recently available "Kyoto" part, "Berlin" will offer extraordinary compute-per-watt that will enable massive rack density.

The third processor announced is code named "Warsaw," AMD's next-generation 2P/4P offering. It is optimized to handle the heavily virtualized workloads found in enterprise environments including the more complex compute needs of data analytics, xSQL and traditional databases. "Warsaw" will provide significantly improved performance-per-watt over today's AMD Opteron 6300 family.

ST signs comprehensive agreement with Rambus

SWITZERLAND: STMicroelectronics has signed a comprehensive agreement with Rambus Inc. that expands existing licenses between the two companies, settles all outstanding claims, and commits both organizations to explore additional opportunities for collaboration.

The multifaceted agreement gives Rambus access to ST's Fully-Depleted Silicon On Insulator (FD-SOI) process-technology design environment. With this, Rambus will be able to benefit from FD-SOI's reduced silicon geometries and lower power consumption at 28nm and below in its future memory and interface solutions.

For its part, ST has secured license terms from the Cryptography Research Inc. (CRI) division of Rambus to make it possible for ST to deploy Differential Power Analysis (DPA) countermeasures and CryptoFirewall core security technology across a wider range of products.

DPA is a form of attack that involves monitoring the fluctuating electrical power consumption of a target device and then using statistical methods to derive cryptographic keys and other secrets. DPA countermeasures are used to protect secret cryptographic keys, including those used to secure transactions for banking, identity, pay television, video gaming, smartphones, government, and other applications.

CryptoFirewall cores are complete hardware-based security blocks designed by CRI to protect against a wide range of attacks and tampering techniques.

The new terms allow ST to further strengthen the security robustness of its leading-edge set-top box ICs and gateways for multimedia services including PayTV.

Real Intent delivers next release of Meridian CDC for clock domain crossing sign-off of SoC designs

USA: Real Intent Inc. announced the Version 5.0 release of its Meridian CDC product for comprehensive clock domain crossing analysis.

This new software release adds enhanced speed, analysis and SystemVerilog language support, maintaining Real Intent’s product leadership in delivering what the company believes is the industry’s fastest-performance, highest-capacity and most precise CDC solution in the market.

Meridian CDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC or FPGA devices are received reliably. With a giga-scale capacity, Meridian CDC is the only solution that enables all aspects of CDC sign-off.

Meridian CDC excels in speed and low-noise analysis of asynchronous clock domains in SoC designs, with an enhanced formal engine that now goes even further and faster to find hidden CDC problems. Its design language support now includes the SystemVerilog synthesizable subset.

In addition, Real Intent has substantially enhanced the user experience with a new front-end interface that incorporates the latest Verdi Automated Debug System from Synopsys, and delivers improved analysis setup, debug features and ease of use.

New features of Meridian CDC Version 5.0 include:
* A hierarchical flow that supports partitioned analysis of designs without waivers or sacrifice of top-level full-chip precision to achieve sign-off of giga-scale designs.
* A new correct-by-configuration design setup to enhance analysis and reporting clarity for clock crossings to ease the sign-off process.
* Enriched SDC design constraint support with the addition of set clock groups and naming schemes.
* “Cleaner and meaner” issue reporting for: bus handling; reset analysis, including glitches in both asynchronous and synchronous domains; and crossings that may be blocked by environment definition.
* An enhanced formal analysis engine with greater speed and coverage.
* Significant enhancements to the SystemVerilog support for interface elements.
* Verdi3 integration - the industry-leading debug platform from Synopsys (formerly SpringSoft).

Camtek in frame engagement for 10 semiconductor inspection systems with Asian OSAT firm

ISRAEL: Camtek Ltd has entered into a frame engagement for 10 semiconductor inspection systems with an Asian OSAT (outsourced semiconductor assembly and test) company.

The first systems' order, in excess of $2 million, will be installed during the second and third quarters, with expectations for additional systems' orders over the next few quarters.

Camtek's line of automated wafer inspection systems enables semiconductor manufacturers, bumping houses and packaging foundries, to monitor processes and enhance yield by detecting defects. Camtek's systems deliver unparalleled 2D and 3D inspection and metrology capabilities for wafers, both before or after test, along the bumping process or after dicing, and address the specialized needs of the most advanced applications.

X-FAB optimizes 180nm process for portable analog apps

GERMANY:  X-FAB Silicon Foundries has enhanced the XP018 process with multiple options to lower chip costs for high-performance analog applications such as audio, sensor interface and 5V-environment power management applications. These options make the XP018 ideal for cost-sensitive consumer applications that require analog integration in 180nm technologies.

X-FAB lowers chip cost for analog designs in several ways with its XP018 process. The newly introduced single-voltage 5V option reduces overall mask count by eliminating the 1.8V portion, a valuable consideration for cost-sensitive mobile applications.

The 5V environment with I/O cells, digital library, OTP memory and analog blocks comes fully compatible with all XP018 high-voltage options, making it ideal for any type of device drivers. Combining it with new Ron-optimized 12V transistors minimizes the required silicon area for piezo or capacitive device driver applications. In addition, an OTP memory compiler for the 5V module is available for trimming purposes up to 16k bit; it complements the existing poly fuses for low trim bit count.

Application-adaptable metal wiring – a novel metal module concept first introduced in the XP018 platform – also saves design costs. It allows flexible, area-efficient placement of MIM capacitors within the metal stack.

Finally, a 60V metal fringe capacitor and a medium-resistance poly with 1kOhm per square make it easier to design high-voltage applications within a 60V power supply environment.

Sebastian Schmidt, product marketing manager for X-FAB’s High Voltage product line, said: “This new process capability really offers some great benefits for our customers. With this competitive 20-layer process, they can build their mixed-signal SoCs by taking advantage of the 180nm logic packing density and competitive push-pull drivers for voltage ranges of 5V, 12V and up to 50V – further enhanced by the availability of NVM blocks. Therefore, this is the ideal technology to use for smart drivers and smart analog ICs.”

The newly enhanced XP018 is automotive qualified – an X-FAB standard feature, – and offers full PDK support and operating temperatures from -40 to 175 degrees Celsius.

The enhanced XP018 platform is available now, so designers can benefit from these options right away.

Rockchip launches tablet SoCs on GLOBALFOUNDRIES’ 28nm HKMG process technology

USA & CHINA: GLOBALFOUNDRIES and Fuzhou Rockchip Electronics Co. Ltd announced that Rockchip’s next-generation mobile processors are ramping to production on GLOBALFOUNDRIES’ 28nm High-K Metal Gate (HKMG) process technology.

Based on a multi-core ARM Cortex-A9 design, the RK3188 and RK3168 chips are optimized for tomorrow’s high-performance, low-cost tablets that require long-lasting battery life.

The combination of Rockchip’s design and GLOBALFOUNDRIES’ 28nm HKMG process technology resulted in a mainstream tablet System-on-Chip (SoC) capable of operating at up to 1.8 GHz performance, while still maintaining the power efficiency expected by mobile device users. The chips began sampling to OEMs in early 2013 and are now ramping to support a wide range of manufacturers.

GLOBALFOUNDRIES’ 28nm-SLP technology is ideally suited for the next generation of smart mobile devices, enabling designs with faster processing speeds, smaller feature sizes, lower standby power and longer battery life. The technology is based on GLOBALFOUNDRIES’ “Gate First” approach to HKMG, which has been in volume production for more than two years. The technology offers a combination of performance, power-efficiency and cost that are ideally suited for the cost-sensitive mainstream mobile market.

StarChip announces sampling of SCF136H SIM controller for native apps

FRANCE: StarChip, experts in designing, qualifying and industrializing Smart Card ICs announced that it is currently sampling the SCF136H product, its latest SIM controller designed to serve the Native market.

The addition of the SCF136H to its product portfolio makes StarChip a broad range supplier of SIM controllers delivering solutions for the whole Telecom market. Several innovative technologies that will shape the next generation StarChip products have been embedded in the SCF136H to deliver a state of the art solution.

While most products for this segment are based on 8/16 bit architecture, SCF136H is based on Cortus APS3cd 32bit CPU, enabling 10Mips@20MHz across a broad spectrum of temperatures and offers advanced low power modes. Special care has been taken regarding the optimization of the instruction set making the APS3cd perfectly suited for applications highly demanding in terms of code density.

Alongside its 136KB of unified flash memory the SCF136H integrates a 3.5KB static RAM. Pre-loaded bootloader can also be delivered with the SCF136H.

The feature set of the SCF136H and its associated unmatched performance allow new possibilities in terms of software development. Not only developers will be able to enhance the efficiency of their applications but they will also be able to add applications and related performance where they were usually limited due to the hardware performance.

Indeed as Native requirements have evolved in the past years, the combination of the performance and cost optimization of the SCF136H makes it perfectly suited for this growing market.

“Unveiling the SCF136H is a great satisfaction as it definitively completes our product portfolio and positions StarChip as a global provider addressing all the Telecom segments from Native to USIM Java Card and 4G/LTE”, said Lucien Brau, CEO of StarChip. “This product also embeds new features boosting the overall performance of the software running on the chip. This is particularly important as those innovations will be re-used for our next products. SCF136H can therefore be seen as the link between the current generation and the next one”.

1H'June NAND flash contract prices benefit from recent replenishment momentum, show slight increase

TAIWAN: According to DRAMeXchange , a research division of TrendForce , 1H'June NAND Flash contract prices have risen by 2-4 percent following the recent increase in replenishment demand from the OEM customers.

The system OEM clients have been attempting to replenish their inventory since 1H’June as a means to prepare for the upcoming peak quarters and the arrival of new smartphones and tablets. As a result of the rising replenishment demand, the NAND Flash vendors have begun prioritizing the majority of their products for the system OEMs, which in turn limited the amount of NAND Flash parts that are available to the channel customers and, subsequently, caused the supplies in the channel market to tighten.

Due in large part to the off-peak quarter effects and the price reduction strategies implemented by various UFD and memory card manufacturers, the shipment and pricing-related pressures encountered by the UFD and memory card markets tended to be more intense in 2Q13 than it was during 1Q13.

Concerned that they might be unable to accumulate enough inventory to prepare for 2H13, and believing that the demands as well as prices for the NAND Flash products will continue to rise, the channel customers have taken active measures to ensure that a sufficient amount of inventory is secured for their major clients. Due to the tightened supply and rising demand resulting from the aforementioned events, the NAND Flash contract prices have showed a slight decline in 1H'June compared to 2H'May.

Aside from Toshiba, which will begin recovering its previously reduced production output, the other NAND Flash vendors are unlikely to raise their capacity any further during the third quarter. As various manufacturers continue to slow down their transition into the 1xnm manufacturing processes, the 3Q supply growth rate will be expected to end up at somewhere below 10 percent.

On the demand side, given that the earlier mentioned system OEMs are planning to gradually accelerate their replenishment efforts, the demands for eMMC and SSD will both be expected to increase. In the event that this occurs, the UFD and the memory card markets—which are traditionally known to experience sluggish demand—can be expected to rebound during the third quarter. For the memory card products, the sales are expected to improve in 2H13 thanks to the emergence of the non-Apple smartphones and tablets;

A similar scenario is anticipated for the UFD market, which will likely benefit from the influence of the traditional peak quarter effects, the growing appeal of the USB 3.0 prices, and the easing price wars among the manufacturers. Compared with the previous quarter, the possibility of there being increased shipment is noticeably higher.

Based on recent statistics, demand will likely show a growth of 10 percent QoQ (due to the consumption of NAND Flash products), whereas starting from the second half of June, the NAND Flash contract prices are likely to be affected by the widening supply-demand gap and will have a good chance of growing even further.

SEMATECH to address critical supply chain challenges

SEMICON West 2013, USA: Through a series of lectures and workshops, SEMATECH will address R&D challenges and closing key infrastructure technology gaps from July 8–12 at SEMICON West in San Francisco, CA.

SEMATECH experts will discuss the challenges which are affecting progress in next-generation lithography techniques, new materials and processes for sub-20 nm manufacturing as well as present a variety of advances in new materials and device structures and lithography.

“In order to prepare for major industry transitions that will stress the industry’s resources over the next decade, we must evolve our infrastructure collaborations to address rapidly evolving technical and business model challenges,” said Dan Armbrust, president and CEO of SEMATECH.

“SEMICON West is an important conference that brings together manufacturers, suppliers, developers, academia and research consortia to share knowledge and discuss how to meet these challenges in order to sustain growth into the future.”

EV Group and Dynaloy develop complete single-wafer cleaning solution

USA: EV Group (EVG), a leading supplier of wafer bonding and lithography equipment, and Dynaloy, LLC, an international manufacturer of chemicals for the electronics industry and wholly owned subsidiary of Eastman Chemical Co., introduced CoatsClean.

It is an innovative single-wafer photoresist and residue removal technology designed to address thick films and difficult-to-remove material layers for the 3D-ICs/through-silicon vias (TSVs), advanced packaging, microelectromechanical systems (MEMS) and compound semiconductor markets.

CoatsClean provides a complete wafer cleaning solution that offers significant efficiency, performance and cost-of-ownership (CoO) advantages compared to traditional resist stripping and post-etch residue removal methods.

CoatsClean incorporates a number of key features to boost performance and productivity, as well as reduce CoO, compared to wet bench and other traditional wafer cleaning approaches. The CoatsClean process and chemical formulation are engineered to perform at higher temperatures, resulting in faster stripping rates and cycle times. This enables CoatsClean to operate as a single-wafer process for thick resist films and difficult-to-remove resists—resulting in improved performance, consistency, reproducibility and repeatability. The engineered formulation also enables selective stripping of the resist.

CoatsClean is also unique in its ability to dispense a small amount of material on the top of the wafer, and then activate the material with direct heat. This direct utilization of the material and heat dramatically reduces the strip material used.  CoatsClean uses fresh solution for each processed wafer compared to competing techniques that use an immersion bath—resulting in greater process efficiency and eliminating cross contamination.

The highly selective application of resist strip material eliminates damage to the wafer backside. The entire CoatsClean process is performed in a single bowl, which reduces tool footprint.

ON Semiconductor and Airbus complete collaborative development of complex ASIC for A350 XWB flight control computer

Paris Air Show 2013, FRANCE: ON Semiconductor have collaboratively developed and released to production a complex Application Specific Integrated Circuit (ASIC) for the A350 XWB Flight Control Computer. Code named JEKYLL.

This custom silicon solution was designed using ON Semiconductor’s internal 110 nanometer (nm) process technology and manufactured at the company’s Gresham, Oregon, facility. Completion of the JEKYLL project reflects a successful collaboration from feasibility evaluation to delivery of first-time-right prototypes and on-schedule transfer to production for the A350 XWB.

Designed in compliance with the D0-254 aerospace requirements and satisfying Airbus’ demanding reliability and product longevity needs, the ASIC provides optimized performance for the Flight Control Primary Computer on the A350 XWB. ON Semiconductor was chosen for this project for a number of reasons including its expertise in complex ASIC development, its focus on military and avionics, best-in-class quality levels, undisputed long-term product support, and a deep knowledge of D0-254 requirements.

Microchip announces PIC32MX 32-bit MCU portfolio

USA: Microchip Technology Inc. announced a new family of PIC32MX3/4 microcontrollers (MCUs) in 64/16 KB, 256/64 KB and 512/128 KB Flash/Ram configurations.

These new MCUs are coupled with comprehensive software and tools from Microchip for designs in connectivity, graphics, digital audio and general-purpose embedded control.

The MCUs are an expansion to the popular PIC32MX3/4 series of high-performance 32-bit microcontrollers. They offer higher RAM memory options and higher integration of peripherals at a lower cost. The PIC32MX3/4 feature 28 x 10-bit ADCs and 5 UARTS, 105 DMIPS performance, serial peripherals, graphic-display, capacitive-touch, connectivity and digital audio support.

IDT RapidIO 20Gbps-per-port switches provide high-performance interconnect for low-power BrownDwarf supercomputer

International Supercomputing Conference 2013, USA: Integrated Device Technology Inc. (IDT) announced that the IDT CPS-1848 and CPS-1616 Gen 2 Serial RapidIO switches provide the key system interconnect for the low-power BrownDwarf Supercomputer developed by nCore HPC and Prodrive.

IDT's RapidIO switches offer 20 Gbps throughput per port with the lowest latency and the highest performance-per-watt compared to other interconnects, enabling nCore and Prodrive to use Texas Instruments’ (TI) RapidIO-equipped processors and leapfrog supercomputing incumbents.

The BrownDwarf supercomputer leverages TI's Keystone-II, which integrates multiple ARM Cortex-A15 MPCore processors, and TMS320C66x digital signal processors (DSPs) that feature embedded RapidIO Gen2 endpoints developed by IDT.

BrownDwarf's three-shelf ATCA-based system delivers 70 teraflops of performance with 144 AMC-based nodes and 4032 processing cores. Taking into account the entire system power consumption, including processing, interconnect, and infrastructure, this equates to a very impressive 6.4 gigaflops per watt. In addition, the supercomputer is designed to easily scale using open standard RapidIO-based inter-cabinet switching, creating large multi-cabinet systems with up to 64K computing nodes.

DeepCover secure authenticator from Maxim protects designs with strong public-key cryptography

USA: Maxim Integrated Products Inc. announced that it is now sampling the DS28E35 DeepCover Secure Authenticator, a highly secure cryptographic solution for a host controller to authenticate peripherals.

The DS28E35 integrates a FIPS 186-based, Elliptic Curve Digital Signature Algorithm (ECDSA) engine to implement asymmetric (public-key) cryptography to operate a challenge-and-response authentication protocol between a host controller and attached peripherals, sensors, or modules.

Operating over a single pin on the 1-Wire interface, the DS28E35 reduces interconnect complexity, simplifies designs, and reduces cost. It provides crypto-strong authentication security for many applications, including medical sensors, industrial programmable logic controller (PLC) modules, and consumer devices.

The use of ECDSA public-key cryptography saves cost and reduces key management complexity by eliminating the need for the host controller to store and protect the authentication key, which is required for comparable symmetric (secret-key) solutions. The DS28E35 operates with a key pair: a public key that resides with the host and an associated private key stored in the DS28E35.

As a primary benefit of ECDSA, there is no security requirement to protect the host public key. It is imperative, however, to protect the private key stored in the DS28E35. This is accomplished through Maxim's DeepCover security technologies, which provide the strongest affordable protection against die-level attacks that attempt to discover the private key.

DeepCover technologies include advanced die routing and layout techniques, additional proprietary methods for private key protection, and circuits that actively monitor for tampering.

Synopsys delivers 2X speedup for implementing and verifying functional ECOs

USA: Synopsys Inc. has announced Formality Ultra, a new configuration of the Formality equivalency checking solution.

Formality Ultra includes innovative matching and verification technologies to efficiently guide designers through the implementation of functional ECOs with minimal impact to the design and verify the correctness of the ECOs in minutes for multimillion instance designs. These new capabilities will help designers cut in half the time they spend implementing ECOs late in the design cycle and result in shorter, more predictable schedules.

Complex designs often undergo multiple functional ECOs late in the design process due to changing specifications and functional errors. Each ECO change can adversely impact schedule and predictability of design closure, which causes designers to invest days trying to minimize the impact of every change to the design. This process can add weeks in the late stages of the design cycle.

"With the new ECO capabilities in Formality Ultra, we can cut in half the time needed for implementing functional ECOs and shorten our design schedules," said Bruce Fishbein, VP of NCD IC Engineering at Cavium. "It will also enable us to implement more complex functional changes as ECOs rather than wait for the next derivative of the design. We are planning to deploy Formality Ultra on our next project."

The new Formality Ultra adds advanced matching techniques that visually highlight the mismatch between the RTL and netlist representations of a design, allowing designers to efficiently zoom in on the changes required to implement an ECO. In addition, a new multi-point verification technology very quickly checks multiple changes made to the design enabling designers to verify the correctness of their ECOs in a matter of minutes on multi-million instance designs.

"Designers worldwide rely on Formality's equivalency checking technology to verify their complex, high-frequency designs without sacrificing chip performance or design schedules," said Antun Domic, senior VP and GM of Synopsys' Implementation Group. "Formality Ultra extends this technology to address another key challenge they face – functional ECOs. It enables designers to significantly reduce the time and effort required to implement those ECOs, increase schedule predictability and close their designs on time."

DECT SoC from DSP Group enables CAT-iq 2.0 in Orange's Livebox gateways

USA: DSP Group announced that its state-of-the-art DECT/CAT-iq 2.0 DCX System-on-a-Chip (SoC) is integrated in Orange's recently-launched third generation gateways (Livebox Play and Livebox Pro).

DSP Group's DCX family of highly-integrated single-chip solutions cost effectively delivers full residence DECT coverage with multi-line, multi-handset support and crystal clear HD voice. The SoC is embedded with a certified CAT-iq 2.0 firmware, offering a rich set of advanced features, including phone book and call list synchronization.

The DCX SoC's in-field software upgradability allows providers to rapidly bring to market products complying not only with emerging standards like CAT-iq 2.1 and 3.0, but also with the DECT ULE (Ultra Low Energy) standard for home automation. DECT ULE support by residential gateways is forecasted to enable a vast market of Ultra-Low-Energy devices for home control, security and monitoring.

Cavium's OCTEON III family of processors feature latest Imagination MIPSr5 architecture

ENGLAND & USA: Imagination Technologies announced that long-time MIPS licensee Cavium Inc. has licensed and incorporated the latest Release 5 MIPS architecture (MIPSr5) features, including hardware virtualization, in all members of its ultra-high-performance 1 -- 48 core OCTEON III family of products.

Jim Whittaker, EVP, Processor Group, Imagination, says: "With MIPS, Cavium has created some of the industry's highest performance and most advanced 64-bit multi-core processors for networking, wireless and storage. We're now working even more closely with Cavium to take MIPS, the industry's most successful and widely deployed 64-bit architecture, to even higher levels of performance and innovation.

"Imagination's ownership of MIPS has significantly increased the level of investment in, and support for, MIPS CPU IP core development across the entire range of 32-bit and 64-bit solutions, with a focus on hardware, software, tools and ecosystem. We are delighted that Cavium has re-affirmed its commitment to MIPS as a result."

NXP tops NFC IC cendor competitive assessment

ENGLAND: NXP, Inside Secure, and STMicroelectronics were judged to be the top rated vendors of NFC ICs in ABI Research’s Competitive Assessment.

Companies were scored for eight key criteria under the categories of Implementation and Innovation across both NFC modems/controllers and secure elements. NXP ranked in first position overall and topped the Implementation category.

It was the most successful vendor in 2012 and scored multiple design wins with a broad cross-section of OEMs and product categories. NXP was also one of three equal scoring companies coming in joint second for Innovation because of its work highlighting new use cases for NFC across its broad portfolio.

Inside Secure ranked second for Innovation and third for Implementation because it was the first vendor to announce a major OEM contract (with RIM using a SE from Infineon), its input into new standards, and its efforts to develop NFC in new device categories. It continues to develop new form-factors, features and is working with partners to better embed NFC technology into new devices.

STMicroelectronics found some traction in the eSE space and was the leading SWP SIM card IC vendor. This combined with its growing success in new device wins contributed to it achieving the second highest Implementation score. Other notable findings include:

* Broadcom topped the Innovation category with its strong feature set, market positioning, breadth of applications, and targeted and innovative approach, which has resulted in recent CLF design wins in smartphones and tablets.

* Sony’s knowledge of contactless with FeliCa has been one of the most active companies in showcasing NFC’s capabilities across a range of products and devices. As a direct result of this Sony has strong partner relationships and technical knowledge.

* Infineon achieved third position within the Implementation criteria. It does not offer a CLF but it has utilized its strengths in security to develop new standards and features to enable the NFC market take off.

Altatech delivers CVD system to Fraunhofer Institution for advanced research in polysilicon deposition for ICS and MEMS

FRANCE: Altatech, a subsidiary of Soitec, announced today that it has installed and qualified an AltaCVD system at the Fraunhofer Research Institution for Modular Solid State Technology EMFT in Munich where it will be used to deposit poly-silicon films for CMOS and MEMS applications. This repeat order from Fraunhofer EMFT reinforces the AltaCVD system's leadership position in advanced material deposition for semiconductor applications.

The high-temperature CVD reactor system was qualified in November 2012 for the first set of applications, including thin-film deposition of doped and undoped poly-silicon. Currently, Fraunhofer EMFT is using the high-temperature CVD system to develop advanced deposition technologies for thin and thick poly-silicon layers. The AltaCVD system was selected for its ability to tightly control layer thicknesses, achieve precise doping levels, and perform highly efficiency cleaning system.

"The AltaCVD tool provides both the flexibility and the performance we need to conduct our various research projects in which we are using single-wafer deposition technology in a multi-chamber platform to develop process integration with high throughput and extremely low level of contamination," said Prof. Ignaz Eisele, head of Fraunhofer's Nano Materials and Silicon Technology Division.

"Our single wafer CVD system's ability to deposit crystalline, polycrystalline and amorphous materials with extremely low defectivity and high uniformity of dopants and film thickness control are key to enabling thin- and thick-film deposition needed for semiconductor and MEMS applications," said Jean-Luc Delcarri, GM of Soitec's Altatech Division. "Following the release of our advanced CVD systems for front-end and memory processing and the roll out of our deposition tools for TSV (through-silicon-via) isolation and conductive layers, we are now applying our proven technology in depositing poly-silicon layers for new applications."

The versatile AltaCVD system is a multi-chamber tool designed for plasma-enhanced or high temperature CVD of advanced semiconductor materials using liquid or gaseous precursors.

Cadence completes acquisition of Evatronix IP business

USA: Cadence Design Systems Inc. has completed the acquisition of the IP business of Poland-based Evatronix, SA SKA.

Further strengthening Cadence's portfolio of intellectual property cores, Evatronix delivers a silicon-proven IP portfolio, which includes certified USB 2.0/3.0, MIPI, display, and storage controllers, which are highly complementary to Cadence's IP product line.

The Evatronix team will report to Martin Lund, Cadence's senior VP of R&D, SoC Realization Group.

The acquisition is not expected to have a material impact on Cadence's balance sheet or second quarter or fiscal 2013 results of operations. Terms of the transaction were not disclosed.

Toshiba develops world's first multi-level-cell structure MROM cell

JAPAN: Toshiba Corp. announced that the development of the world's first MROM cell to offer improved cell current characteristics without any increase in cell size.

This advance was achieved by adopting a multi-level-cell structure, which also secures high speed operation. Details will be presented on June 14 at the 2013 Symposia on VLSI Technology and Circuits, held in Kyoto, Japan, June 11-14, 2013.

MROM's main role is to store the boot loader or firmware. The density of MROM implemented is SoC for such digital applications as smartphones and tablet PCs is increasing year by year, and in order to improve access time it is necessary to halve the MROM cell area with every generation.

In a typical MROM bit cell, a single-level cell, variations in fabrication are increasing as SoC process technology advances, with the narrowing of the channel area of the cell transistors. The result is a slower access time for the 40nm generation than for the previous process generation. Improving access time requires a larger transistor, as a bigger cell area secures a wider channel area.

Toshiba has developed a multi-bit cell that uses twice the area of a standard single level cell, successfully expanding channel width in the cell transistor by three times. This also triples the current characteristic of the cell without any change in the memory capacity per area. It reduces the influence of the variation in fabrication by 42 percent.

Toshiba has developed of MROM cell with the 40nm process generation and aims to ship SoC for digital applications that implement the cell in 2014.

Microsemi announces System Builder design tool for ARM-based SmartFusion2 SoC FPGA designs

USA: Microsemi Corp. announced SmartFusion2 SoC FPGA users can now benefit from its newly released design tool, System Builder.

System Builder is a powerful new design tool within the Libero System-on-Chip (SoC) Design Environment version 11.0 and is specifically targeted at accelerating customer definition and implementation of ARM-based systems using SmartFusion2 SoC FPGAs.

The output from System Builder is automatically generated and correct-by-construction, thus eliminating the errors that are created when the architecture is specified 'by hand' as in more traditional tool flows. Thus, System Builder dramatically shortens the design cycle time for complex SoC FPGAs.

Additionally, software-oriented engineers can easily create an embedded architecture and begin code development all on their own. This simplifies the adoption of Microsemi SmartFusion2 devices and provides a much broader set of design engineers with access to SoC FPGA technology.

The enhanced System Builder flow also enables Microsemi to easily support more customers with its internal design services team that offers digital or mixed signal design for custom functional blocks, Soft IP, firmware development and even complete designs to end customers.

Broadcom intros quad-core HSPA+ processor

USA: Broadcom Corp. announced a quad-core HSPA+ processor designed for high-performance, entry-level smartphones. The BCM23550 is the company's newest smartphone platform optimized for the Android 4.2 Jelly Bean operating system (OS).

According to research firm International Data Corp. (IDC), the first quarter of 2013 marked the first time that smartphones comprised more than half of all phones shipped globally. This growth is driven by mass market consumers who demand affordable devices that deliver increased functionality and a level of performance that was previously available only in higher-end superphones.

The BCM23550, and its turnkey design, are powered by a quad-core processor running at 1.2GHz, VideoCore multimedia and an integrated HSPA+ cellular baseband that provides enhanced, power-efficient features for entry-level smartphones.

The BCM23550 supports "dual HD," allowing users to simultaneously share high-definition content from a small handheld screen to a larger, Miracast-enabled display.  It includes leading VideoCore technology for fluid, responsive graphics and incorporates power management techniques to optimize battery life and reduce power consumption without compromising the user experience.

The platform provides an integrated Image Signal Processor (ISP) that supports up to 12-megapixel sensors with advanced imaging capabilities such as blink and smile detection, face tracking, red eye reduction, fast shot to shot (burst capture), zero shutter lag, and best picture selection. With contactless terminals proliferating worldwide, the BCM23550 platform also integrates NFC with native support for simplified connectivity and mobile payments systems like QuickTap from China UnionPay.

Microchip launches MPLABR REAL ICET power monitor module

USA: Microchip Technology Inc. has launched the MPLAB REAL ICE Power Monitor Module, which enables designers to identify and eliminate code that consumes high current, in real time.

Combined with the MPLAB REAL ICE in-circuit emulator and MPLAB X IDE, this development platform allows users to measure, graphically profile and optimise code power consumption for all of Microchip's more than 1000 8-bit, 16-bit and 32-bit PIC microcontrollers.

Additionally, it offers unsurpassed micro-Amp current measurement, with an overall dynamic range up to 1 Amp, and a voltage range of 1.25V to 5.5V.  Microchip's Power Monitor Module is significantly more cost-effective than similar tools, making it ideal for a broad range of battery-powered, digital power-supply, motor-control and metering applications.

Embedded designers continue to seek new ways to optimise power consumption for both extended battery life and greater line-power efficiency.  As MCU vendors and users have greatly reduced hardware power consumption – such as the 9 nA sleep and 30 µA/MHz active current consumption of Microchip's eXtreme Low Power (XLP) PIC MCUs – application software is the next place for engineers to focus.
 
Microchip's Power Monitor Module provides programmable power to the target, as well as sampling intervals, enabling users to run at specific voltage levels and see tailored measurements.  Designers can also set a "current break" threshold level that breaks when exceeded, allowing them to pinpoint the code causing the spike and debug it.  All of these measurements can be displayed graphically, via the "Current Profile Graphing" feature, enabling engineers to better understand which sections of their code are consuming higher current.

"The MPLAB REAL ICE Power Monitor Module meets our customers' need for a low-cost software optimisation tool that enables them to squeeze every last drop of power efficiency out of their code," said Derek Carlson, Microchip's VP of Development Tools. "Together with our XLP PIC microcontrollers for battery-powered applications, and our MCUs and dsPIC® digital signal controllers for digital power conversion, motor control and metering, Microchip now provides the industry's first complete low-power embedded design platform."

The MPLAB REAL ICE Power Monitor Module (part # AC244008) is available today.

Adesto CBRAM memory demos ultra low-power operation

USA:  Adesto Technologies , a memory solutions provider delivering innovative products for code and data storage applications, will demonstrate ultra-low power operation of its proprietary CBRAM memory in a paper to be presented at the 2013 Symposia on VLSI Technology and Circuits in Kyoto, Japan, June 11-14, 2013.

The paper explores the use of the non-volatile memory technology embedded in a body sensor, a device developed to operate without a battery in the system, through the use of energy harvesting.

The paper follows the successful completion of a project in cooperation with a team of technologists from the University of Virginia to create a low energy device to acquire physiological data from the human body, process that data, and transfer it through wireless communication. The project was partially funded by DARPA through the US government’s program to invest in and award small business innovation research (SBIR).

CBRAM is an emerging, disruptive memory technology which can be integrated in standard CMOS processes, function as a discrete memory device or be embedded in microcontrollers, System-on-Chip (SOC) or Field Programmable Gate Arrays (FPGA).

The paper demonstrates the ability of a non-volatile CBRAM memory block to operate at less than 1V supply voltage for read, program and erase functions without the need for charge pumps.  This low-power functionality translates to 3x lower write voltage and approximately 10x lower write energy compared to other low energy non-volatile memory devices.

"We have built some exciting wearable wireless body sensors that run completely without batteries from body heat, but one key missing piece was non-volatile memory (NVM). Existing NVM devices are way too power hungry for our aggressive power budgets,” said Ben Calhoun, associate professor at the University of Virginia, “This integrated ultra low-power CBRAM from Adesto is an important advance for self-powered systems."

“Ultra-low energy non-volatile memory like CBRAM is essential to the development of energy starved technologies that require stored instructions and data collection over an extended period,” said Shane Hollmer, VP of Engineering at Adesto. “These devices must preserve data even in the event of power interruptions and failures. CBRAM is a natural fit for these applications.”

Arasan intros USB 3.0 SSIC bridge IP

USA: Arasan Chip Systems Inc. released its SSIC Adapter IP, supporting the USB 3.0 specification for USB Superspeed Inter-Chip (SSIC).

The SSIC IP provides low power, high speed chip to chip interconnect which leverages existing investments in USB software and system investments.  High performance and reduced power are achieved by using the MIPI M-PHY  as the physical layer interface. Leveraging the MIPI M-PHY power management, the SSIC interface lowers the active power and idle power. The SSIC adapter layer IP is optimized for power, area, and EMI robustness for embedded inter-chip interfaces.

Arasan's Superspeed Inter-Chip controller is a PHY adapter layer that provides a bridge between a USB 3.0 Host, Device or OTG controllers' PIPE interface and the MIPI M-PHY RMM I interface. The Arasan USB 3.0 SSIC controller interfaces directly to Arasan's MIPI M-PHY IP to implement the SSIC adaptation to the USB 3.0 PIPE interface.

The Arasan USB 3.0 SSIC controller is compliant with the "Super Speed Inter-Chip" supplement to the USB revision 3.0 specification, version 1.0 and the MIPI M-PHY specification revision 3.0-r.03 and provides an effective data rate of up to 5.0 Gbps per lane over 1 to 4 lanes of M-PHY. The Arasan USB 3.0 SSIC controller interfaces to the USB 3.0 Device or Host controller with PIPE3 interface at 8/16/32-bit data width.

Conexant launches 4-channel USB voice capture IC

USA: Conexant Systems Inc. has introduced the CX20820, its new high-performance USB voice capture IC targeted to voice interactive products, voice conferencing systems, Skype TV/STB webcam, and surveillance applications.

The CX20820 is the industry’s first USB Microphone analog-to-digital converter (ADC) with integrated preamplifier, gain calibration, and sync control. This product is a part of Conexant’s extensive portfolio of Voice Capture Products, enabling a best-in-class performance.

The isochronous, full-speed USB interface provides universal compatibility with major CE devices and appliances, making it easy to add state-of-the-art voice capture capability to existing hardware and OS platforms. The integrated Sync Control feature eliminates clock jitter by synchronizing the ADC to the playback clock domain, a critical advantage for systems running acoustic echo cancellation algorithms.

There are a total of four independent voice input channels with integrated anti-aliasing filters for microphone array applications. The major challenge with microphone arrays, which are used for voice localization and beamforming, is unmatched microphones in an assembled microphone module. This problem often leads to inaccurate estimation of the shape of the beam, and issues in noise suppression and precision localization.

The CX20820 includes a self-gain calibration feature that corrects for the mismatch down to maximum 1 dB variance—another innovation in the CX20820 that stands out from the typical microphone ADC.

Synopsys announces design kit optimized for all SoC processor cores

USA: Synopsys Inc. announced an extension to its DesignWare Duet Embedded Memory and Logic Library IP portfolio specifically designed to enable the optimized implementation of a broad range of processor cores.

The new DesignWare HPC (High Performance Core) Design Kit contains a suite of high-speed and high-density memory instances and standard cell libraries that allow system-on-chip (SoC) designers to optimize their on-chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power – or to achieve an optimum balance of the three for their specific application.

"Our work with Synopsys has resulted in significant improvements in the area and energy efficiency implementations of our IP cores utilizing Synopsys' memories and standard cell libraries," said Mark Dunn, executive VP of IMGworks SoC Design at Imagination Technologies.

"Our most recent project was building a PowerVR Series6 GPU core using cells and memories from Synopsys' HPC Design Kit. We achieved an overall reduction of 25 percent in dynamic power as well as a 10 percent area savings, with some blocks achieving a 14 percent area improvement. We also created a tuned design flow that has delivered a 30 percent improvement in implementation turnaround time."

Synopsys' broad portfolio of DesignWare IP includes silicon-proven embedded memory compilers and standard cell libraries that support a range of foundries and processes from 180 to 28 nanometers (nm) and have shipped in more than three billion chips. The DesignWare Duet Package of Embedded Memories and Logic Libraries contains all the physical IP elements needed to implement a complete SoC including standard cells, SRAM compilers, register files, ROMs, datapath libraries and Power Optimization Kits (POKs).

Options for overdrive/low- voltage process, voltage and temperature (PVT) corners, multi-channel cells, and memory built-in self-test (BIST) and repair are also available. The DesignWare HPC Design Kit adds performance-, power- and area-optimized standard cells and memory instances tuned for the special speed and density requirements of advanced CPU, GPU and DSP cores.

"The physical IP used for implementing processor cores has a tremendous impact on the achievable power, performance and area of the design," said Nianfeng Li, corporate VP of design methodologies and program management at VeriSilicon.

"When we consider all the factors that contribute to an optimized implementation, the DesignWare Duet Embedded Memories and Logic Libraries have been a primary contributor to the performance gains we realized on the recent hardening of a leading CPU core.  The new DesignWare HPC Design Kit contains the specialty cells and SRAMs we need to achieve the highest possible performance on advanced processor cores while minimizing area and power consumption."

"DSPs are a fundamental component of every advanced electronic product, from smartphones and tablets to smart TVs and base stations, and each design has unique optimization requirements," said Eran Briman, VP of marketing at CEVA Inc. "In addition to extreme performance, designers rely on our DSP cores to consume as little power and occupy as little silicon area as possible. We look forward to continued collaboration with Synopsys in helping our mutual customers achieve their strict design goals."

The HPC Design Kit contains fast cache memory instances and performance-tuned flip-flops that enable speed improvement of up to 10 percent over the standard Duet package. To minimize dynamic and leakage power as well as die area, the new kit provides area-optimized and multi-bit flip-flops and an ultra-high-density two-port SRAM, delivering demonstrated reductions in area and power of up to 25 percent while maintaining processor performance.

Optimized design flow scripts and expert core optimization consulting, including FastOpt implementation services, are also available from Synopsys to help design teams achieve their processor and SoC design goals in the shortest possible time.

"Designers using any of Imagination's IP, including PowerVR graphics and video, MIPS processors and Ensigma communications processors, will ultimately be able to reap benefits from leveraging Synopsys' HPC Design Kit, thanks to their deep experience working with Imagination and delivering services to our customers over many years," added Mark Dunn. "Through projects including our strategic collaboration with Synopsys, we're putting practical solutions in place to help our customers achieve performance-, power- and area-optimized designs utilizing our IP in the shortest time."

"Designers implementing processor cores must make tradeoffs in speed, power and area that will result in the best implementation for their specific application, and physical IP plays an important role in achieving that optimum design," said John Koeter, VP of marketing for IP and systems at Synopsys. "We have worked closely with leading customers and IP partners that implement a broad range of processor cores to gain insight on how to achieve the absolute best results on their design and reflected that collective learning in the new DesignWare HPC Design Kit. In one package, designers now have access to the specialty cells and memories they need to optimize their CPU, GPU and DSP cores across the full speed, power and area spectrum."

The DesignWare HPC Design Kit will be available for leading 28-nm processes starting in July 2013.

Rambus and SK Hynix sign patent license agreement

SOUTH KOREA & USA: Rambus Inc. and SK Hynix have signed a five-year patent license agreement for the use of Rambus memory-related patented innovations in SK Hynix semiconductor products and have also settled all outstanding claims.

The agreement includes a license to certain DRAM products for payments of $12 million per quarter for the next five years. Other terms of the agreement are confidential.

“This is a milestone agreement for both companies that puts years of legal disputes behind us and gives us the opportunity for collaboration,” said Dr. Ron Black, president and CEO at Rambus. “With this agreement, we can focus more on engaging with the industry as we work on future challenges where we can bring invention and value to the market with superior solutions and products.”

Alchimer to collaborate with Imec on advanced nano-interconnect technologies at sub-22nm manufacturing

FRANCE: Alchimer, S.A., a leading provider of wet deposition technologies for dual damascene, through-silicon vias (TSVs), MEMS and solar, announced a joint development project with imec to evaluate and implement Copper (Cu) filling solutions for advanced nano-interconnect technologies.

The focus will be on Alchimer's Electrografting (eG) product family that has demonstrated void-free filling on 7nm node devices and allows direct Cu fill on barrier with no seed layer required for damascene processes.

As CMOS scaling creates finer features, market requirements for copper damascene include smaller dimensions (≤16/14 nm) with a thin barrier layer, and thin or no Cu seed layer.

Filling processes must be defect/void free to meet reliability specifications, and achieve high yields. Conventional physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes are not meeting these requirements. Alchimer's wet deposition technologies are based on a molecular build-up process that breaks through the limitations of dry deposition processes.

The goal of the JDP is to obtain reliability data and electrical performance for eG wet deposition processes in a 300mm manufacturing environment for sub-22nm technologies. As part of the JDP, the companies will assess the plating chemistry and work to identify the optimal process conditions for 300mm wafer-level advanced damascene plating applications.

WiLAN acquires Cypress Semiconductor portfolio

CANADA: Wi-LAN Inc. has acquired a portfolio of patents from Cypress Semiconductor Corp. related to phase locked loop technology used in a wide range of semiconductor products.

WiLAN believes the portfolio has current applicability to memory and other semiconductor products using clock control circuitry.

"WiLAN has already established successful licensing programs in the areas or wireless and display technologies, programs from which we continue to see tremendous revenue potential. In addition, we are in the process of building new licensing programs in the areas of semiconductor, medical and cloud related technologies," said Jim Skippen, president and CEO.

"This acquisition is an important step towards building our semiconductor portfolio, an area in which we see significant licensing opportunities."

SEMI reports Q1 2013 worldwide semiconductor equipment figures; billings $7.31 billion

USA: SEMI reported that worldwide semiconductor manufacturing equipment billings reached $7.31 billion in the first quarter of 2013.

The quarterly billings data by region in billions of US dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

The billings figure is 8 percent higher than the fourth quarter of 2012 and 32 percent lower than the same quarter a year ago. The data is gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 100 global equipment companies that provide data on a monthly basis.

Worldwide semiconductor equipment bookings were $7.78 billion in the first quarter of 2013. The figure is 23 percent lower than the same quarter a year ago and 14 percent higher than the bookings figure for the fourth quarter of 2012.

Bosch and STM hold joint honors as no. 1 MEMS suppliers for 2012

USA: For the first time ever, no clear winner has emerged to claim top honors in the microelectromechanical systems (MEMS) business for 2012, with Bosch of Germany and French-Italian STMicroelectronics ending up evenly splitting the title of No. 1 supplier for the year, according to a MEMS Competitive Analysis Report from information and analytics provider IHS.

With both companies just shy of the $800 million mark, Bosch and STMicroelectronics each had MEMS revenue of approximately $793 million in 2012. The two companies do not use the same exchange rates every quarter when converting their revenue from euros to the U.S. dollar, and as a difference of less than 1 percent separates the revenue levels of both, IHS found it was not possible this time to declare a clear winner as to who was No. 1 for 2012.

“With billions of dollars up for grabs, competition in the MEMS market is intense,” said Jérémie Bouchaud, director and senior principal analyst for MEMS & sensors at IHS. “Nowhere is the rivalry more furious than the battle for the market’s top spot. In fact, the content for number one is so closely contested that Bosch and STMicroelectronics battled each other to a draw in 2012.”

MEMS in the money
Overall, the top 20 MEMS manufacturers last year accounted for a whopping 77 percent of the industry total of some $8.3 billion. The figure excludes foundry revenue in order to avoid double-counting of fabless and foundry takings within the same ranking. For instance, excluded is MEMS foundry revenue from STMicroelectronics for its fabrication of Hewlett-Packard inkjet print heads, or similar foundry revenue from Texas Instruments for Lexmark inkjet print heads.

Foremost among all the players were the four companies at the top, each with revenue ranging from $675 million to $800 million, and collectively well ahead of the rest of the pack.

Bosch vs. STMicroelectronics
Bosch, the No. 3 entity in 2011, enjoyed a MEMS revenue boost of 8 percent last year including a nearly 5 percent uptick in its primary automotive MEMS business, which accounted for 82 percent of overall Bosch MEMS takings.

Bosch is unchallenged as the top automotive MEMS supplier with 27 percent share of the market. The company also has a growing consumer and mobile MEMS trade—up 17 percent for the year—thanks to the soaring sales of pressure sensors in handsets, compensating for slightly down revenues in accelerometers and microphones. But, while the company did well in 2012, its result was impacted by an unfavorable exchange currency rate, especially in its US automotive business.

STMicroelectronics, the No. 4 player in 2011, counted on a robust consumer and mobile business as its main source of MEMS revenue. While rival Bosch dominates automotive, STM leads in consumer and mobile MEMS with 32 percent of the market. STM also made inroads into automotive with $15 million in 2012, up from $10 million the year earlier. Gyroscopes were ahead of accelerometers in contributing to STM’s cache, and similar to Bosch, pressure sensors for handsets boomed because of shipments into smartphones like the Samsung Galaxy S III.

Texas Instruments tumbles from the top
Falling out of the No. 1 spot was Texas Instruments, down to No. 3, with revenue down 3 percent to $751 million. While front projectors for business and education still formed the majority of its digital light processing (DLP) chip revenue, the segment was flat last year.

In particular, DLP revenue in home theater and rear-projection TVs was down, especially with the exit of Mitsubishi as the last remaining rear-projection TV brand in North America. DLP revenue for pico-projectors also has not taken off as expected, with the chipset still too expensive and its adoption slow in the consumer and mobile markets.

At the No. 4 spot was Hewlett-Packard with revenue of $677 million. HP also suffered a drop in ranking, down from No. 2 in 2011, as revenue associated with its inkjet printer heads contracted 10 percent last year. This follows a 15 percent decline in the shipment of inkjet printers. Moreover, HP’s revenue from the replacement of disposable print heads has been shrinking continually as the company long ago started to move to printers with permanent print heads.

Rounding out the Top 5 but at a relatively far remove from the four other companies above it was Canon of Japan, with revenue of $377 million.

InvenSense on the rise
In all, revenue for companies from the succeeding sixth spot all the way to No. 15 each had takings between $100 million to just under $300 million.

Worth noting outside of the Top 5 was California-based InvenSense at No. 13, with revenue up 30 percent to $186 million. InvenSense is the most successful MEMS startup ever, its market breakthrough coming in 2009 thanks to its design in the Nintendo Wii Motion Plus gaming accessory. While InvenSense initially had been heavily dependent on gaming, the company wisely diversified its business and now looks to handsets and tablets as even more important sources of revenue.

InvenSense has also pioneered serial production of 6-axis inertial measurement unit comprising accelerometers and gyroscopes in a 4 x 4-millimeter package. Combo sensors last year accounted for half of the company’s revenue, and InvenSense is now producing a very small 9-axis inertial measurement unit also containing a 3-axis magnetometer that measures only 3 x 3 millimeters.

Synopsys unveils synthesis-based test technology delivering up to 3X higher compression

USA: Synopsys Inc. unveiled a new, innovative test technology to further reduce the cost of testing silicon devices by delivering up to 3x higher test compression and minimizing the time required to test each silicon die.

The new technology also uses fewer pins and higher-frequency on-chip design-for-test (DFT) circuitry, enabling design teams to test several die in parallel and use the maximum performance of their tester equipment to achieve additional reduction in test time and cost. Embedded in Synopsys' Design Compiler RTL synthesis and TetraMAX ATPG solutions, the new test technology delivers faster test time and higher test quality without adversely impacting design goals and schedules.

"Our initial review of Synopsys' new test technology shows it can achieve up to three times higher compression compared to existing solutions," said Roberto Mattiuzzo, SoC test and diagnosis manager at STMicroelectronics' Central CAD and Design Solutions. "The technology can be deployed on a variety of design styles with any number of test pins and supports high-speed test clocks. It is well aligned with our ever-increasing requirements to lower the cost and raise the quality of test for our silicon products using our current and ready-for-production fabrication process."

Engineers are increasingly testing silicon parts in parallel and at faster frequencies while adding more tests. Synopsys' new synthesis-based test technology uses an innovative method to efficiently stream compressed test data in and out of the DFT circuitry, significantly lowering the amount of data required to achieve high test quality.

This method requires fewer test pins and enables silicon parts to operate at higher frequencies while in test mode. As a result, more die can be tested in parallel, and the time required to test each die is further reduced. To deliver superior quality of results and faster turnaround time, design teams implement the DFT for the new technology with the Synopsys Galaxy Implementation Platform suite of tools, concurrently balancing design constraints by performing intelligent tradeoffs between speed, area, power, test and yield.

"Designers across different industry segments have widely adopted and relied on our DFTMAX compression to reduce cost, improve quality and get their products to market on time," said Antun Domic, senior VP and GM of Synopsys' Implementation Group. "Our latest synthesis-based test innovation will help them meet more stringent test cost and quality goals within tighter design schedules."

EMCORE launches HDBaseT/CATx solutions for HD video with audio

USA: EMCORE Corp. announced a new product line to support HDBaseT video and audio extension and distribution for the professional audio/visual (Pro AV) and broadcast markets.

These HDBaseT CAT5e/6 products will be demonstrated at InfoComm 2013, June 12-14 in booth 3525 at the Orange County Convention Center in Orlando, Florida.

HDBaseT technology enables the 5Play feature set for the delivery of uncompressed high-definition video, audio, control signals and power over a single CAT5e/6 cable. HDBaseT is simpler and more cost-effective
to implement for video applications up to 100 meters, eliminating the common issues professional installers face concerning cable distance and the location of available power outlets.

The Opticomm-EMCORE HDBaseT line includes the new OTC Series of insert cards for the Optiva platform, the c-linx Series of stand-alone extenders, and the High-Definition Multimedia Matrix (HDMX), which switches, converts and extends CAT5e/6 in addition to other video formats.

The OTC Series products are designed for Optiva platform 6- or 16-slot 19" rack-mount enclosures, or 1- or 2-slot tabletop, or wall-mountable enclosures and can be combined in the same frame with other Optiva family fiber optic cards. The HDMX is a multi-format, cross-point switch that supports HDBaseT inputs and outputs along with many other signal types including DVI, HDMI with HDCP, 3G HD-SDI with embedded audio, as well as analog video interfaces component, composite and VGA.

Reflex CES records four consecutive years of growth

FRANCE: Reflex CES, a leading provider of custom embedded and complex systems, announced financial results for its fiscal 2012.

The company posted annual revenues of €7.8 million and annual net profits of €1 million (15 percent). These figures represent an increase of 13.2 percent over 2011 and 22 percent of compound annual growth rate for the last four years, giving Reflex CES four consecutive years with net profits representing more than 13 percent of revenue.

The strong results are primarily due to the success of the company’s embedded systems design and manufacturing skills in the military and defense sectors and of Reflex CES‘s commitment to embrace new international business.

“We are delighted with the consistent increase of revenues thereby reinforcing Reflex CES‘s global expertise in complex high-speed electronics boards, high-density FPGAs and rugged systems design," stated Sylvain Neveu, Reflex CES co-founder and CEO. “We are building on the success of the past four years to further develop Reflex CES business internationally. Several influential new partnerships and distribution agreements are in their final stages, which will broaden the scope of our offering to a full embedded solution, including COTS and custom electronic designs.”

The company generates most of its revenue through major French customers serving military and defense markets.  Another significant portion of its business lies in other markets demanding the same high performance technology, including medical, transportation, industrial and telecommunications segments.

In 2012, Reflex CES initiated its international growth with major agreements in USA and China, for example with Golden Sea (China) for the design of HDMI video boards.

In 2013, Reflex CES has already launched a number of new « industry’s first” products, including its Aurora-like IP core, based on Altera FPGAs, an innovative and cost effective FPGA prototyping FPP25 platform, as well as advanced high-speed data recorders. Together with its sister company, PLDA, Reflex CES unveiled a new line of programmable ARM-FPGA based System-on-Module (SoM) platforms at Embedded World 2013.