Arasan Chip Systems announces MIPI compliant low latency interface (LLI) IP solution

SAN JOSE, USA: Arasan Chip Systems Inc., a leading provider of Total IP Solutions, announced the availability of their MIPI LLI controller IP along with a matching Type 1 M-PHY, the latest additions to its prominent MIPI portfolio.

Both the Applications Processor and the Baseband Processor for mobile platforms are complex SOC's. Although the two chips are often integrated into one SoC by a number of chip vendors, a number of high end mobile chipsets are still split into two separate processors.

They each have their own system level memory to allow efficient cache refills. LLI is a chip-to-chip link layer interconnect protocol that allows efficient , low-latency cache refills from the DRAM associated with a companion chip, thereby removing the need for two separate sets of DRAM's and substantially reducing the cost of mobile platforms. LLI requires M-PHY Type 1 as the physical layer.

Arasan has developed a combined LLI controller and M-PHY Type 1 solution, which can be configured for a variety of host buses (like AHB, AXI and OCP), and bandwidth/latency requirements across multiple traffic classes. Using up to six lanes of M-PHY's this solution offers up to 17 Gbps bandwidth in each direction, with only one clock domain crossing in the LLI controller. Customers are given a choice of either source synchronous or independent clocking in the M-PHY's for clock and data recovery mechanisms in the analog receivers.